CN110632568A - Test Signal Source for Synthetic Aperture Radar Real-time Imaging Processor - Google Patents

Abstract

The present disclosure provides a test signal source for a synthetic aperture radar real-time imaging processor, including: a control computer for storing, reading, and analyzing radar echo data, and issuing work parameters, work instructions and data, and the control computer includes A data flow controller; and a data output controller, connected to the control computer, receiving the working parameters and work instructions sent by the control computer and generating a flow control signal accordingly; the data flow controller according to the flow control signal , sending data to the data output controller, and the data output controller sends test data and test control signals to the measured synthetic aperture radar real-time imaging processor according to test requirements; it can realize real-time imaging of synthetic aperture radar on the ground Processors are fully tested.

Description

Test Signal Source for Synthetic Aperture Radar Real-time Imaging Processor

technical field

The present disclosure relates to the technical field of synthetic aperture radar, in particular to a test signal source of a real-time imaging processor of synthetic aperture radar.

Background technique

Synthetic aperture radar is a remote sensing device capable of all-day and all-weather high-resolution imaging of the earth's surface. Synthetic aperture radar uses pulse compression to achieve high resolution in the range direction, and high resolution in azimuth direction through synthetic aperture.

During the SAR flight process, the radar echo data is obtained in real time, and the SAR image is obtained through real-time or off-line imaging processing. Due to the processing of two-dimensional images, motion compensation processing must be performed synchronously during the processing process. Compared with other radar signal processing, the imaging algorithm of synthetic aperture radar is very complex, with a huge amount of calculation and a high data rate. Therefore, The real-time imaging processor of synthetic aperture radar needs to adopt special-purpose signal processor to realize.

The real-time imaging processor is an important part of synthetic aperture radars such as airborne and missile-borne, and is used for imaging processing of radar echo data to obtain radar images. For the test of the synthetic aperture radar real-time imaging processor, the best way is to input the radar echo data obtained from the actual flight. In special cases, the simulated radar echo data can also be input. During the process, at least two-dimensional test data of two azimuth processing apertures must be provided. For the usual airborne synthetic aperture radar, the data volume of this test data is on the order of GB, and it is also necessary to follow the data under actual flight conditions. format, time interval and data rate, and input the test data to the real-time imaging processor; however, there are problems such as complex parameter control, frame synchronization and pulse synchronization that cannot be synchronized with the actual flight or simulated flight in this imaging processor test technology. For the above test requirements of the SAR real-time imaging processor, a dedicated test signal source is generally used to output appropriate two-dimensional test data and control signals to the SAR real-time imaging processor according to different imaging modes and radar system parameters.

Therefore, there is a need in the art for a dedicated test signal source capable of flexibly and comprehensively testing a synthetic aperture radar real-time imaging processor.

public content

(1) Technical problems to be solved

Based on the above requirements, the present disclosure provides a test signal source for a synthetic aperture radar real-time imaging processor to alleviate the complexity of parameter control, frame synchronization and pulse synchronization in the existing synthetic aperture radar real-time imaging processor test technology. Simulate technical issues such as flight synchronization.

(2) Technical solution

The present disclosure provides a test signal source for a synthetic aperture radar real-time imaging processor, including: a control computer for storing, reading, and analyzing radar echo data, and issuing work parameters, work instructions and data, and the control computer includes A data flow controller; and a data output controller, connected to the control computer, receiving the working parameters and work instructions sent by the control computer and generating a flow control signal accordingly; the data flow controller according to the flow control signal , sending data to the data output controller, and the data output controller sends test data and test control signals to the real-time imaging processor of the synthetic aperture radar under test according to test requirements.

In the embodiment of the present disclosure, the control computer further includes a CPU, a bus controller, a memory, a non-volatile memory, and a first asynchronous control interface.

In the embodiment of the present disclosure, the data flow controller sends the control data to the data output controller in a synchronous manner with the pulse trigger signal and the frame trigger signal according to the frame trigger and the pulse trigger determined by the flow control signal.

In the embodiment of the present disclosure, the data output controller includes: a second asynchronous control interface, a decoder, a counter, a system clock circuit, a synchronous control circuit, a front data switch, a rear data switch, a buffer circuit A and a buffer circuit B.

In the embodiment of the present disclosure, the second asynchronous control interface is used to receive the working parameters and working instructions sent by the first asynchronous control interface in the control computer, and send them to the decoder and the synchronous control circuit.

In the embodiment of the present disclosure, the decoder is configured to receive the working parameters and the working instructions sent by the second asynchronous control interface, respectively decode the working parameters and the working instructions to form a control code, and the control code includes a frequency code or Cycle encoding.

In the embodiment of the present disclosure, the counter is used to control and generate the control pulse signal according to the frequency code or period code in the control code, and the counter can be realized by a digital circuit.

In the embodiment of the present disclosure, the synchronous control circuit is used to generate a flow control signal acting on the data flow controller according to the control pulse signal and the control code; generate a test control signal acting on the real-time imaging processor of the tested synthetic aperture radar Signal; generate a channel control signal that acts on the front data switch, the rear data switch, the buffer circuit A, and the buffer circuit B.

In the embodiment of the present disclosure, when testing the synthetic aperture radar real-time imaging processor, the test data corresponding to an imaging mode is firstly selected, that is, the actual flight data or simulation data corresponding to the imaging mode.

In the embodiment of the present disclosure, the working parameters include: pulse repetition frequency, data length per pulse, number of pulses per frame; the close working instruction includes: working mode, frame start, pulse start; the test control signal Including: pulse trigger signal, frame trigger signal.

(3) Beneficial effects

It can be seen from the above technical solutions that the test signal source of the synthetic aperture radar real-time imaging processor of the present disclosure has at least one or part of the following beneficial effects:

(1) It can use the original echo data of synthetic aperture radar obtained in actual flight, or use the original echo data of simulated synthetic aperture radar as test data, automatically extract the working parameters and work instructions of synthetic aperture radar included in the test data, and automatically Control the working mode of real-time imaging processing, and control the output of test data close to the data output of data flight state or simulated flight state, and provide test data and test signals close to actual flight conditions for the synthetic aperture radar real-time imaging processor.

(2) A comprehensive test of the synthetic aperture radar real-time imaging processor can be realized on the ground;

(3) Compared with the actual flight test verification technology risk is greatly reduced;

(4) Compared with the actual flight test verification cost is greatly reduced.

Description of drawings

1 is a schematic diagram of the composition of the test signal source of the synthetic aperture radar real-time imaging processor of the present disclosure;

2 is a schematic diagram of the composition of a computer with a data flow controller of a test signal source of a synthetic aperture radar real-time imaging processor of the present disclosure;

3 is a schematic diagram of the composition of the data output controller of the test signal source of the synthetic aperture radar real-time imaging processor of the present disclosure;

FIG. 4 is a working schematic diagram of a test signal source of the synthetic aperture radar real-time imaging processor of the present disclosure.

Detailed ways

The disclosure provides a test signal source of a synthetic aperture radar real-time imaging processor, which can provide test data and test signals close to actual flight conditions for the test of a synthetic aperture radar real-time imaging processor, and realize real-time synthetic aperture radar imaging on the ground. Imaging processors are tested flexibly and comprehensively.

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

In an embodiment of the present disclosure, a test signal source of a synthetic aperture radar real-time imaging processor is provided. As shown in FIG. 1 , the test signal source of the synthetic aperture radar real-time imaging processor includes:

The control computer is used to store, read and analyze radar echo data, and issue working parameters, working instructions and data;

A data output controller, connected to the control computer, receives the working parameters and work instructions sent by the control computer and generates a flow control signal accordingly;

The control computer includes a data flow controller, the data flow controller in the control computer determines the frame trigger signal and the pulse trigger signal according to the flow control signal, and the control data is sent to the Data output controller. , the data output controller sends test data and test control signals to the real-time imaging processor of the SAR under test according to test requirements.

The control computer reads the radar echo data stored in the non-volatile memory, parses out the synthetic aperture radar operating mode and operating parameters corresponding to this radar echo data, sends them to the data output controller, and receives the data output controller According to the flow control signal fed back, the data flow controller is controlled to send test data to the data output controller according to the flow control signal, and the data output controller sends test data and test control signals to the SAR under test according to test requirements Real-time imaging processor.

In the embodiment of the present disclosure, as shown in FIG. 2, the control computer includes a data flow controller, and may also include a CPU (ie, a central processing unit), a bus controller, a memory, a nonvolatile memory, a first asynchronous control Interface; mainly used to store test data, analyze test data, receive synchronous control of data flow controller, send test data to data flow controller, and directly send work parameters and work instructions to data output controller.

The control computer can be implemented by a general server, a general workstation, a high-configuration compatible computer or a high-configuration industrial control computer, or a high-configuration hardened computer.

The control computer and the data flow controller are connected by a system bus. According to the selected control computer, the system bus can use PCI bus, PCI-E bus, VPX bus, PXI bus, PXI-E bus and other bus forms.

The data flow controller is a high-speed data exchange circuit relying on the system bus, which is used to generate bus control signals, trigger the control computer to send test data stored in the memory or non-volatile memory, and receive the control computer to output test data; according to the flow The frame trigger and the pulse trigger determined by the control signal, and the control data is sent to the data output controller in a synchronous manner with the pulse trigger signal and the frame trigger signal.

In the embodiment of the present disclosure, as shown in FIG. 3 , the data output controller includes: a second asynchronous control interface, a decoder, a counter, a system clock circuit, a synchronous control circuit, a synchronous control circuit, a front data switch, a rear data switch, A buffer circuit A and a buffer circuit B are composed, wherein,

The second asynchronous control interface is used to receive the operating parameters and operating instructions sent by the first asynchronous control interface in the control computer, and send them to the decoder and the synchronous control circuit. The second asynchronous control interface can be realized by a digital circuit;

The decoder is used to receive the working parameters and working instructions sent by the second asynchronous control interface, respectively decode the working parameters and working instructions to form control codes, the control codes include frequency codes or cycle codes, control counters and synchronous control circuits , the decoder can be realized by digital circuit;

The counter is used to control and generate a control pulse signal according to the frequency code or period code in the control code, and the counter can be realized by a digital circuit;

The system clock circuit is used to generate a synchronous clock for system work. The system clock circuit can be realized by using a crystal oscillator combined with a dedicated clock chip;

The synchronous control circuit is used to generate a flow control signal that acts on the data flow controller according to the control pulse signal and the control code, generate a test control signal that acts on the real-time imaging processor of the synthetic aperture radar under test, and generate a test control signal that acts on the front data switch, The channel control signals of the rear data switch, buffer circuit A, and buffer circuit B, and the synchronous control circuit can be realized by digital circuits;

The front data switch is used to control the output of the data output by the data flow controller to the buffer circuit A, or output to the buffer circuit B, and the front data switch can be realized by a digital circuit;

The rear data switch is used to control the data output by the buffer circuit A, or the data output by the output buffer circuit B, to output to the real-time imaging processor of the measured synthetic aperture radar, and the rear data switch can be realized by a digital circuit;

A buffer circuit A is used for buffering test data, and the buffer circuit A may be implemented by a digital circuit;

The buffer circuit B is used for buffering test data, and the buffer circuit B can be realized by a digital circuit.

In addition to the system clock circuit and some interface driver chips, the digital circuit implementation of other components of the data flow controller can be integrated in the programmable logic device.

FIG. 4 is a working schematic diagram of a test signal source of the synthetic aperture radar real-time imaging processor of the present disclosure.

When testing the synthetic aperture radar real-time imaging processor, first select the test data corresponding to an imaging mode, that is, the actual flight data or simulation data corresponding to the imaging mode;

These test data are stored in the non-volatile memory of the control computer, and then transferred to the memory of the control computer. The CPU of the control computer extracts the relevant working parameters and work instructions in the test data, and sends them to the data output through the first asynchronous control interface. The second asynchronous control interface of the controller, the second asynchronous control interface sends the working mode information in the received working order to the synchronous control circuit, and the synchronous control circuit converts the working mode information into a working mode control signal and sends it to the real-time imaging processor , the real-time imaging processor automatically sets the working mode;

Relevant working parameters in test data generally include pulse repetition frequency (PRF), data length per pulse, and number of pulses per frame, and relevant working instructions in test data generally include working mode, frame start, and pulse start;

After the second asynchronous control interface of the data output controller receives the work parameters and work instructions, it sends them to the decoder of the data output controller, and the decoder controls the counter of the data output controller to start counting, and outputs the count value to the data output The synchronous control circuit of the controller, the synchronous control circuit generates the flow control signal to the data flow controller according to the count, the test control signal to the real-time imaging processor of the synthetic aperture radar under test, and the front data switch and rear data switch to the data output controller. Channel control signals of the data switch, cache circuit A, and cache circuit B;

The flow control signal to the data flow controller mainly includes a pulse trigger signal and a frame trigger signal, which are used to control the data output by the data flow controller in a manner synchronized with the pulse trigger signal and the frame trigger signal;

The test control signals to the real-time imaging processor of the synthetic aperture radar under test mainly include working mode control signals, pulse trigger signals and frame trigger signals;

After the data flow controller receives the flow control signal, the flow control signal triggers the output of test data. The test data enters the front data switch and outputs to buffer circuit A or buffer circuit B according to the channel control signal. Synchronously, according to the channel control signal, the buffer The test data buffered in circuit B or buffer circuit A is output to the rear data switch, and the rear data switch is controlled by the channel control signal, synchronizes the data with the test control signal, and outputs the test data to the real-time imaging processor of the synthetic aperture radar under test .

It should also be noted that the directional terms mentioned in the embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only referring to the directions of the drawings, not Used to limit the protection scope of this disclosure. Throughout the drawings, the same elements are indicated by the same or similar reference numerals. Conventional structures or constructions are omitted when they may obscure the understanding of the present disclosure.

And the shape and size of each component in the figure do not reflect the actual size and proportion, but only illustrate the content of the embodiment of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

Unless known to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that can vary depending upon the desired properties obtained from the teachings of the present disclosure. Specifically, all numbers used in the specification and claims to represent the content of components, reaction conditions, etc. should be understood to be modified by the term "about" in all cases. In general, the expressed meaning is meant to include a variation of ±10% in some embodiments, a variation of ±5% in some embodiments, a variation of ±1% in some embodiments, a variation of ±1% in some embodiments, and a variation of ±1% in some embodiments ±0.5% variation in the example.

Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

Words such as "first", "second", "third" and the like used in the description and claims to modify the corresponding elements do not in themselves mean that the elements have any ordinal numbers, nor The use of these ordinal numbers to represent the sequence of an element with respect to another element, or the order of manufacturing methods, is only used to clearly distinguish one element with a certain designation from another element with the same designation.

In addition, unless specifically described or steps that must occur sequentially, the order of the above steps is not limited to that listed above and may be changed or rearranged according to the desired design. Moreover, the above-mentioned embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, technical features in different embodiments can be freely combined to form more embodiments.

Those skilled in the art can understand that the modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment. Modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore may be divided into a plurality of sub-modules or sub-units or sub-assemblies. All features disclosed in this specification (including accompanying claims, abstract and drawings) and any method or method so disclosed may be used in any combination, except that at least some of such features and/or processes or units are mutually exclusive. All processes or units of equipment are combined. Each feature disclosed in this specification (including accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Moreover, in a unit claim enumerating several means, several of these means may be embodied by the same item of hardware.

Similarly, it should be appreciated that in the above description of exemplary embodiments of the disclosure, in order to streamline the disclosure and to facilitate an understanding of one or more of the various disclosed aspects, various features of the disclosure are sometimes grouped together into a single embodiment, figure, or its description. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this disclosure.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present disclosure in detail. It should be understood that the above descriptions are only specific embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims (10)

1. A test signal source for a synthetic aperture radar real-time imaging processor, comprising: A control computer is used for storing, reading, and analyzing radar echo data, and issuing work parameters, work instructions and data, and the control computer includes a data flow controller; and The data output controller is connected with the control computer, receives the working parameters and work instructions sent by the control computer and generates a flow control signal accordingly; the data flow controller sends data to the said flow control signal according to the flow control signal A data output controller, the data output controller sends test data and test control signals to the real-time imaging processor of the synthetic aperture radar under test according to test requirements. 2. the test signal source of synthetic aperture radar real-time imaging processor according to claim 1, described control computer also comprises CPU, bus controller, memory, nonvolatile memory, the first asynchronous control interface. 3. The test signal source of the synthetic aperture radar real-time imaging processor according to claim 1, the frame trigger and the pulse trigger determined by the described data flow controller according to the flow control signal, control data with the pulse trigger signal and the pulse trigger signal The frame trigger signal is sent to the data output controller in a synchronous manner. 4. the test signal source of synthetic aperture radar real-time imaging processor according to claim 1, described data output controller comprises: the second asynchronous control interface, decoder, counter, system clock circuit, synchronous control circuit, preceding data switch, post-data switch, buffer circuit A and buffer circuit B. 5. the test signal source of synthetic aperture radar real-time imaging processor according to claim 4, described second asynchronous control interface is used for receiving the operating parameter and the work instruction that the first asynchronous control interface sends in the control computer, and sends to decoder and synchronization control circuits. 6. the test signal source of synthetic aperture radar real-time imaging processor according to claim 4, described decoder, is used for receiving the operating parameter and the operating instruction that the second asynchronous control interface sends, carries out respectively to operating parameter and operating instruction Decoding to form a control code, where the control code includes frequency code or period code. 7. the test signal source of synthetic aperture radar real-time imaging processor according to claim 4, described counter, is used for according to the frequency code in the control code or cycle code, control produces control pulse signal, and counter can adopt digital circuit to realize . 8. the test signal source of synthetic aperture radar real-time imaging processor according to claim 4, described synchronous control circuit, is used for according to control pulse signal and control coding, produces the flow control signal that acts on data flow controller; Produces A test control signal acting on the real-time imaging processor of the synthetic aperture radar under test; generating channel control signals acting on the front data switch, rear data switch, buffer circuit A, and buffer circuit B. 9. according to the test signal source of synthetic aperture radar real-time imaging processor according to claim 1, when synthetic aperture radar real-time imaging processor is tested, first select the corresponding test data of an imaging mode, that is, the corresponding test data of this imaging mode actual flight data or simulated simulation data. 10. the test signal source of synthetic aperture radar real-time imaging processor according to claim 1, described working parameter comprises: pulse repetition frequency, every pulse data length, every frame pulse quantity; Described off work order comprises: working pattern , frame start, and pulse start; the test control signal includes: a pulse trigger signal and a frame trigger signal.

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