CN110632568A - Test signal source of real-time imaging processor of synthetic aperture radar - Google Patents
Test signal source of real-time imaging processor of synthetic aperture radar Download PDFInfo
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Abstract
The present disclosure provides a test signal source for a real-time imaging processor of a synthetic aperture radar, comprising: the control computer is used for storing, reading and analyzing radar echo data and sending working parameters, working instructions and data, and comprises a data flow controller; the data output controller is connected with the control computer, receives the working parameters and the working instructions sent by the control computer and generates flow control signals according to the working parameters and the working instructions; the data flow controller sends data to the data output controller according to the flow control signal, and the data output controller sends test data and a test control signal to the real-time imaging processor of the synthetic aperture radar to be tested according to the test requirement; the method can realize comprehensive test of the real-time imaging processor of the synthetic aperture radar on the ground.
Description
Technical Field
The disclosure relates to the technical field of synthetic aperture radars, in particular to a test signal source of a real-time imaging processor of a synthetic aperture radar.
Background
The synthetic aperture radar is a remote sensing device with the capability of imaging the earth surface with high resolution all day long and all weather, the synthetic aperture radar realizes the high resolution in the distance direction by using pulse compression, and the high resolution in the direction is realized by the synthetic aperture.
And in the flight process of the synthetic aperture radar, radar echo data are acquired in real time, and a synthetic aperture radar image is obtained through real-time or off-line imaging processing. Because the two-dimensional image is processed, the motion compensation processing is required to be synchronously performed in the processing process, and compared with the signal processing of other radars, the imaging algorithm of the synthetic aperture radar is very complex, the calculated amount is huge, and the data rate is also very high, so that the real-time imaging processor of the synthetic aperture radar needs to be realized by adopting a special signal processor.
The real-time imaging processor is an important component of the airborne synthetic aperture radar, the missile-borne synthetic aperture radar and the like and is used for imaging radar echo data to obtain radar images. For the test of the real-time imaging processor of the synthetic aperture radar, the best method is to input radar echo data acquired in actual flight, and under special conditions, simulation radar echo data can also be input, no matter which data, two-dimensional test data of two azimuth processing apertures are provided in one measurement process, for the common airborne synthetic aperture radar, the data volume of the test data is in the GB magnitude, and the test data is input to the real-time imaging processor according to the data format, time interval and data rate under the actual flight condition; however, the imaging processor testing technology has the problems that the parameter control is complex, the frame synchronization and the pulse synchronization cannot be synchronized with the actual flight or the simulated flight, and the like, and in order to meet the testing requirements of the real-time imaging processor of the synthetic aperture radar, a special testing signal source is generally adopted, and suitable two-dimensional testing data and control signals are output to the real-time imaging processor of the synthetic aperture radar according to different imaging modes and radar system parameters.
Therefore, there is a need in the art for a dedicated test signal source that enables flexible and comprehensive testing of a synthetic aperture radar real-time imaging processor.
BRIEF SUMMARY OF THE PRESENT DISCLOSURE
Technical problem to be solved
Based on the above requirements, the present disclosure provides a test signal source for a real-time imaging processor of a synthetic aperture radar, so as to alleviate technical problems in the existing test technology for a real-time imaging processor of a synthetic aperture radar, such as complicated parameter control, frame synchronization and pulse synchronization, and incapability of synchronizing with actual flight or simulated flight.
(II) technical scheme
The present disclosure provides a test signal source for a real-time imaging processor of a synthetic aperture radar, comprising: the control computer is used for storing, reading and analyzing radar echo data and sending working parameters, working instructions and data, and comprises a data flow controller; the data output controller is connected with the control computer, receives the working parameters and the working instructions sent by the control computer and generates flow control signals according to the working parameters and the working instructions; and the data flow controller sends data to the data output controller according to the flow control signal, and the data output controller sends test data and a test control signal to the real-time imaging processor of the synthetic aperture radar to be tested according to the test requirement.
In the embodiment of the present disclosure, the control computer further includes a CPU, a bus controller, a memory, a nonvolatile memory, and a first asynchronous control interface.
In the disclosed embodiment, the data flow controller controls the data to be sent to the data output controller in a manner synchronized with the burst trigger signal and the frame trigger signal according to the frame trigger and the burst trigger determined by the flow control signal.
In an embodiment of the present disclosure, the data output controller includes: the device comprises a second asynchronous control interface, a decoder, a counter, a system clock circuit, a synchronous control circuit, a front data switch, a rear data switch, a cache circuit A and a cache circuit B.
In the embodiment of the disclosure, the second asynchronous control interface is used for receiving the working parameters and the working instructions sent by the first asynchronous control interface in the control computer and sending the working parameters and the working instructions to the decoder and the synchronous control circuit.
In the embodiment of the present disclosure, the decoder is configured to receive the working parameter and the working instruction sent by the second asynchronous control interface, and decode the working parameter and the working instruction respectively to form a control code, where the control code includes a frequency code or a periodic code.
In the embodiment of the present disclosure, the counter is used for controlling and generating the control pulse signal according to the frequency coding or the period coding in the control coding, and the counter may be implemented by a digital circuit.
In the disclosed embodiment, the synchronous control circuit is used for generating a flow control signal acting on the data flow controller according to the control pulse signal and the control code; generating a test control signal acting on a real-time imaging processor of the synthetic aperture radar to be tested; and generating channel control signals acting on the front data switch, the rear data switch, the cache circuit A and the cache circuit B.
In the embodiment of the disclosure, when testing the synthetic aperture radar real-time imaging processor, firstly, test data corresponding to one imaging mode, that is, actual flight data or analog simulation data corresponding to the imaging mode is selected.
In an embodiment of the present disclosure, the operating parameters include: pulse repetition frequency, data length per pulse, number of pulses per frame; the shutdown operation instruction comprises: working mode, frame start, pulse start; the test control signal includes: pulse trigger signal, frame trigger signal.
(III) advantageous effects
According to the technical scheme, the test signal source of the real-time imaging processor of the synthetic aperture radar of the disclosure has at least one or part of the following beneficial effects:
(1) the method can automatically extract the working parameters and working instructions of the synthetic aperture radar contained in the test data by using the original echo data of the synthetic aperture radar obtained by actual flight or using the original echo data of the simulated synthetic aperture radar as the test data, automatically control the working mode of real-time imaging processing, control the output of the test data to be close to the data output of a data flight state or a simulated flight state, and provide the test data and test signals which are close to the actual flight conditions for the real-time imaging processor of the synthetic aperture radar.
(2) The real-time imaging processor of the synthetic aperture radar can be comprehensively tested on the ground;
(3) compared with the actual flight test, the risk of technical verification is greatly reduced;
(4) compared with the actual flight test, the cost is greatly reduced.
Drawings
FIG. 1 is a schematic diagram of the components of a test signal source for a synthetic aperture radar real-time imaging processor of the present disclosure;
FIG. 2 is a schematic diagram of the composition of a computer with a data flow controller for a test signal source for a synthetic aperture radar real-time imaging processor of the present disclosure;
FIG. 3 is a schematic diagram of the composition of the data output controller of the test signal source of the real-time imaging processor of the synthetic aperture radar of the present disclosure;
fig. 4 is an operational schematic diagram of a test signal source of the synthetic aperture radar real-time imaging processor of the present disclosure.
Detailed Description
The test signal source can provide test data and test signals close to actual flight conditions for testing the real-time imaging processor of the synthetic aperture radar, and flexibly and comprehensively test the real-time imaging processor of the synthetic aperture radar on the ground.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
In an embodiment of the present disclosure, a test signal source of a real-time imaging processor of a synthetic aperture radar is provided, as shown in fig. 1, the test signal source of the real-time imaging processor of the synthetic aperture radar includes:
the control computer is used for storing, reading and analyzing radar echo data and sending working parameters, working instructions and data;
the data output controller is connected with the control computer, receives the working parameters and the working instructions sent by the control computer and generates flow control signals according to the working parameters and the working instructions;
the control computer includes a data flow controller in which the data flow controller transmits control data to the data output controller in synchronization with the burst trigger signal and the frame trigger signal according to the frame trigger signal and the burst trigger signal determined by the flow control signal. And the data output controller sends test data and test control signals to the real-time imaging processor of the synthetic aperture radar to be tested according to the test requirements.
The control computer reads radar echo data stored in the nonvolatile memory, analyzes a synthetic aperture radar working mode and working parameters corresponding to the radar echo data, sends the radar echo data to the data output controller, receives a flow control signal fed back by the data output controller, controls the data flow controller to send test data to the data output controller according to the flow control signal, and sends the test data and the test control signal to the real-time imaging processor of the synthetic aperture radar to be tested according to the test requirement.
In the embodiment of the present disclosure, as shown in fig. 2, the control computer includes a data flow controller, and may further include a CPU (central processing unit), a bus controller, a memory, a nonvolatile memory, and a first asynchronous control interface; the method is mainly used for storing test data, analyzing the test data, receiving synchronous control of a data flow controller, sending the test data to the data flow controller, and directly sending working parameters and working instructions to a data output controller.
The control computer can be realized by a general server, a general workstation, a high-configuration compatible computer or a high-configuration industrial control computer and a high-configuration ruggedized computer.
The control computer and the data flow controller are connected by a system bus, which may be in the form of a PCI bus, a PCI-E bus, a VPX bus, a PXI-E bus, etc., depending on the selected control computer.
The data flow controller is a high-speed data exchange circuit depending on a system bus and is used for generating a bus control signal, triggering the control computer to send test data stored in an internal memory or a nonvolatile memory and receiving the test data output by the control computer; control data is sent to the data output controller in synchronization with the burst trigger signal and the frame trigger signal in accordance with the frame trigger and the burst trigger determined by the flow control signal.
In the embodiment of the present disclosure, as shown in fig. 3, the data output controller includes: a second asynchronous control interface, a decoder, a counter, a system clock circuit, a synchronous control circuit, a front data switch, a rear data switch, a buffer circuit A and a buffer circuit B,
the second asynchronous control interface is used for receiving and controlling the working parameters and the working instructions sent by the first asynchronous control interface in the computer and sending the working parameters and the working instructions to the decoder and the synchronous control circuit, and the second asynchronous control interface can be realized by adopting a digital circuit;
the decoder is used for receiving the working parameters and the working instructions sent by the second asynchronous control interface, respectively decoding the working parameters and the working instructions to form control codes, wherein the control codes comprise frequency codes or periodic codes, a control counter and a synchronous control circuit, and the decoder can be realized by adopting a digital circuit;
the counter is used for controlling and generating a control pulse signal according to frequency coding or period coding in the control coding, and the counter can be realized by adopting a digital circuit;
the system clock circuit is used for generating a synchronous clock for system work, and can be realized by combining a crystal oscillator with a special clock chip;
the synchronous control circuit is used for generating a flow control signal acting on the data flow controller according to the control pulse signal and the control code, generating a test control signal acting on the real-time imaging processor of the detected synthetic aperture radar, and generating channel control signals acting on the front data switch, the rear data switch, the cache circuit A and the cache circuit B, and can be realized by adopting a digital circuit;
the front data switch is used for controlling the data output by the data flow controller to be output to the cache circuit A or the cache circuit B, and the front data switch can be realized by adopting a digital circuit;
the rear data switch is used for controlling the data output by the cache circuit A or the data output by the output cache circuit B to be output to the real-time imaging processor of the synthetic aperture radar to be detected, and the rear data switch can be realized by adopting a digital circuit;
the buffer circuit A is used for buffering the test data and can be realized by adopting a digital circuit;
and the buffer circuit B is used for buffering the test data, and the buffer circuit B can be realized by adopting a digital circuit.
In addition to the system clock circuit and part of the interface driver chip, the digital circuit implementation of the other components of the data flow controller can be integrated into the programmable logic device.
Fig. 4 is an operational schematic diagram of a test signal source of the synthetic aperture radar real-time imaging processor of the present disclosure.
When testing a real-time imaging processor of the synthetic aperture radar, firstly selecting test data corresponding to an imaging mode, namely actual flight data or analog simulation data corresponding to the imaging mode;
the test data are stored in a nonvolatile memory of the control computer and then are called into a memory of the control computer, a CPU of the control computer extracts relevant working parameters and working instructions in the test data and sends the relevant working parameters and working instructions to a second asynchronous control interface of the data output controller through a first asynchronous control interface, the second asynchronous control interface sends working mode information in the received working instructions to a synchronous control circuit, the synchronous control circuit converts the working mode information into working mode control signals and sends the working mode control signals to a real-time imaging processor, and the real-time imaging processor automatically sets a working mode;
the related working parameters in the test data generally include Pulse Repetition Frequency (PRF), data length per pulse and pulse number per frame, and the related working instructions in the test data generally include working mode, frame start and pulse start;
a second asynchronous control interface of the data output controller sends working parameters and working instructions to a decoder of the data output controller after receiving the working parameters and the working instructions, the decoder controls a counter of the data output controller to start counting, and outputs a counting value to a synchronous control circuit of the data output controller, the synchronous control circuit generates a flow control signal for the data flow controller, a test control signal for a tested synthetic aperture radar real-time imaging processor according to the counting, and channel control signals for a front data switch, a rear data switch, a cache circuit A and a cache circuit B of the data output controller;
the flow control signal for the data flow controller mainly comprises a pulse trigger signal and a frame trigger signal and is used for controlling data output by the data flow controller to be synchronous with the pulse trigger signal and the frame trigger signal;
the test control signal for the real-time imaging processor of the synthetic aperture radar to be tested mainly comprises a working mode control signal, a pulse trigger signal and a frame trigger signal;
after the data flow controller receives the flow control signal, the flow control signal triggers and outputs test data, the test data enters a front data switch and is output to a cache circuit A or a cache circuit B according to a channel control signal, the test data cached in the cache circuit B or the cache circuit A is output to a rear data switch synchronously according to the channel control signal, and the rear data switch is controlled by the channel control signal to synchronize the data with the test control signal and output the test data to a real-time imaging processor of the synthetic aperture radar to be tested.
It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.
And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Unless otherwise indicated, the numerical parameters set forth in the specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the present disclosure. In particular, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Generally, the expression is meant to encompass variations of ± 10% in some embodiments, 5% in some embodiments, 1% in some embodiments, 0.5% in some embodiments by the specified amount.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.
In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. A test signal source for a real-time imaging processor for synthetic aperture radar, comprising:
the control computer is used for storing, reading and analyzing radar echo data and sending working parameters, working instructions and data, and comprises a data flow controller; and
the data output controller is connected with the control computer, receives the working parameters and the working instructions sent by the control computer and generates flow control signals according to the working parameters and the working instructions; and the data flow controller sends data to the data output controller according to the flow control signal, and the data output controller sends test data and a test control signal to the real-time imaging processor of the synthetic aperture radar to be tested according to the test requirement.
2. The synthetic aperture radar real time imaging processor test signal source of claim 1, said control computer further comprising a CPU, a bus controller, a memory, a non-volatile memory, a first asynchronous control interface.
3. The SAR real-time imaging processor test signal source of claim 1, the data flow controller sends control data to the data output controller in synchronization with the burst trigger signal and the frame trigger signal depending on the frame trigger and the burst trigger determined by the flow control signal.
4. A test signal source for a synthetic aperture radar real-time imaging processor according to claim 1, said data output controller comprising: the device comprises a second asynchronous control interface, a decoder, a counter, a system clock circuit, a synchronous control circuit, a front data switch, a rear data switch, a cache circuit A and a cache circuit B.
5. The test signal source of the SAR real-time imaging processor according to claim 4, wherein the second asynchronous control interface is used for receiving the working parameters and working instructions sent by the first asynchronous control interface in the control computer and sending the working parameters and working instructions to the decoder and the synchronous control circuit.
6. The SAR real-time imaging processor test signal source according to claim 4, wherein the decoder is configured to receive the working parameters and the working commands from the second asynchronous control interface, and decode the working parameters and the working commands to form control codes, and the control codes include frequency codes or periodic codes.
7. The SAR real-time imaging processor test signal source according to claim 4, the counter for controlling the generation of the control pulse signal according to the frequency coding or period coding in the control coding, the counter can be implemented by digital circuit.
8. The SAR real-time imaging processor test signal source of claim 4, the synchronization control circuit for generating a flow control signal to the data flow controller according to the control pulse signal and the control code; generating a test control signal acting on a real-time imaging processor of the synthetic aperture radar to be tested; and generating channel control signals acting on the front data switch, the rear data switch, the cache circuit A and the cache circuit B.
9. The testing signal source of the SAR real-time imaging processor according to claim 1, when testing the SAR real-time imaging processor, firstly selecting a testing data corresponding to an imaging mode, i.e. an actual flight data or an analog simulation data corresponding to the imaging mode.
10. A source of test signals for a synthetic aperture radar real-time imaging processor according to claim 1, said operating parameters comprising: pulse repetition frequency, data length per pulse, number of pulses per frame; the shutdown operation instruction comprises: working mode, frame start, pulse start; the test control signal includes: pulse trigger signal, frame trigger signal.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111562552A (en) * | 2020-04-30 | 2020-08-21 | 北京无线电测量研究所 | Ground radar synchronous network master control device and control method |
| CN112305511A (en) * | 2020-09-27 | 2021-02-02 | 北京无线电测量研究所 | Radar receiver digital baseband signal recording and analyzing system and method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1428707A (en) * | 2001-12-27 | 2003-07-09 | 中国科学院计算技术研究所 | Mass high-speed digital signal source based on microcomputer PCI bus |
| CN102882624A (en) * | 2012-08-10 | 2013-01-16 | 上海卫星工程研究所 | PXI/PCI bus-based remote synchronization device of test signal source devices and method thereof |
| US8843343B2 (en) * | 2011-10-31 | 2014-09-23 | Aptina Imaging Corporation | Failsafe image sensor with real time integrity checking of pixel analog paths and digital data paths |
| CN106546963A (en) * | 2016-11-03 | 2017-03-29 | 中国科学院电子学研究所 | A kind of satellite-borne synthetic aperture radar simulation testing device |
| CN106597397A (en) * | 2016-12-20 | 2017-04-26 | 中国科学院电子学研究所 | Synthetic aperture radar real-time imaging processor fault rapid positioning method |
| CN108563144A (en) * | 2018-03-30 | 2018-09-21 | 西安电子科技大学 | A kind of missile-borne radar signal processing semi-hardware type simulation test system |
-
2019
- 2019-11-05 CN CN201911074500.9A patent/CN110632568B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1428707A (en) * | 2001-12-27 | 2003-07-09 | 中国科学院计算技术研究所 | Mass high-speed digital signal source based on microcomputer PCI bus |
| US8843343B2 (en) * | 2011-10-31 | 2014-09-23 | Aptina Imaging Corporation | Failsafe image sensor with real time integrity checking of pixel analog paths and digital data paths |
| CN102882624A (en) * | 2012-08-10 | 2013-01-16 | 上海卫星工程研究所 | PXI/PCI bus-based remote synchronization device of test signal source devices and method thereof |
| CN106546963A (en) * | 2016-11-03 | 2017-03-29 | 中国科学院电子学研究所 | A kind of satellite-borne synthetic aperture radar simulation testing device |
| CN106597397A (en) * | 2016-12-20 | 2017-04-26 | 中国科学院电子学研究所 | Synthetic aperture radar real-time imaging processor fault rapid positioning method |
| CN108563144A (en) * | 2018-03-30 | 2018-09-21 | 西安电子科技大学 | A kind of missile-borne radar signal processing semi-hardware type simulation test system |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111562552A (en) * | 2020-04-30 | 2020-08-21 | 北京无线电测量研究所 | Ground radar synchronous network master control device and control method |
| CN112305511A (en) * | 2020-09-27 | 2021-02-02 | 北京无线电测量研究所 | Radar receiver digital baseband signal recording and analyzing system and method |
| CN112305511B (en) * | 2020-09-27 | 2024-05-07 | 北京无线电测量研究所 | System and method for recording and analyzing digital baseband signals of radar receiver |
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