CN102435968A

CN102435968A - Pulse sequence generator having independent channel delay function

Info

Publication number: CN102435968A
Application number: CN201110328348XA
Authority: CN
Inventors: 宁瑞鹏; 昝国锋; 杨光; 李鲠颖
Original assignee: KALEFU MAGNETIC RESONANCE TECH Co Ltd SHANGHAI; East China Normal University
Current assignee: KALEFU MAGNETIC RESONANCE TECH Co Ltd SHANGHAI; East China Normal University
Priority date: 2011-10-26
Filing date: 2011-10-26
Publication date: 2012-05-02

Abstract

The invention discloses a pulse sequence generator having an independent channel delay function. The pulse sequence generator consists of a programmable logic device, an internal memory, a delay circuit and an interface chip, wherein the quantity of channels of the delay circuit is equal to that of output channels of the pulse sequence generator. When the pulse sequence generator is reset, parameters of the delay circuit are set by a spectrometer computer, and the parameters of each channel of the delay circuit can be independently set, so that the delay amount of each output channel of the pulse sequence generator can be independently programmed. The pulse sequence generator has a simple structure and high universality; during asynchronous triggering, additional occupation of resources of a central processing unit (CPU) and the internal memory of the spectrometer computer is not required; and requirements for an operating environment are reduced.

Description

A kind of pulse-series generator with autonomous channel delay function

Technical field

The present invention relates to NMR spectrum and magnetic resonance imaging instrument technology, be specifically related to a kind of pulse-series generator with autonomous channel delay function.

Background technology

In nuclear magnetic resonance spectrometer and magnetic resonance imaging spectrometer, pulse-series generator is one of core component, is used to produce required pulse train, the miscellaneous part of control instrument and the unit collaborative work of nuclear magnetic resonance experiment scanning.Because each hardware component is different to the response time of trigger pip, therefore in practical application, has relative time delay between each parts.This relative time delay will produce considerable influence to experimental result and picture quality, need correct.One of solution to this problem is to design the influence of eliminating relative time delay through optimizing pulse train.Yet relative time delay is different to the influence that different sequences produce, and the kind of pulse train is a lot, need be optimized one by one each pulse train.In addition, for some pulse train, any magnetic resonance imaging sequence of tomography for example, this method is difficult to eliminate fully the relative time delay effect of three tunnel space encoding gradients.Therefore, adopt this method to proofread and correct and increased the workload and the difficulty of pulse train design.Second method is to utilize pulse-series generator that each parts are carried out asynchronous triggering.Promptly trigger the long parts of those relative time delaies in advance, thereby the relative time delay between the parts is proofreaied and correct.Second method utilizes hardware to eliminate relative time delay, and needn't be optimized and revise to each sequence, so this method is more direct, effective and practical than first method.Yet, adopt second method to eliminate relative time delay, just need pulse-series generator to have the function of asynchronous triggering.Generally speaking, the pulse train data download in the pulse-series generator with the form of " incident-time " tabulation, upgrade the foundation of output state as pulse-series generator.In the prior art, adopt asynchronous trigger method to proofread and correct relative time delay, just need before pulse train is carried out, carry out reconstruction calculations " incident-time " tabulation.Find that in practical application the shared time of reconstruction calculations process can not ignore, can produce certain influence experimentation and picture contrast.In addition, in order to realize asynchronous triggering, " time " in the former tabulation will be divided into a plurality of fragments.This temporal resolution that will cause pulse-series generator to provide might can't satisfy actual requirement, and consequently the pulse-series generator trigger pip that can't export expection is controlled miscellaneous part work.

Summary of the invention

A kind of pulse-series generator that the objective of the invention is to be directed against the deficiency of prior art and provide with autonomous channel delay function.

The objective of the invention is to realize like this:

A kind of pulse-series generator with autonomous channel delay function, this pulse-series generator mainly is made up of PLD, internal memory, delay circuit and interface chip.PLD is responsible for logic control on the plate of pulse-series generator, and it is connected with interface chip, internal memory and delay circuit respectively.Before pulse train was carried out, the pulse train data were through input end, interface chip and PLD, in the write memory.The term of execution of pulse train, the pulse train data are read from internal memory, through PLD and delay circuit, arrive output terminal.Delay circuit is made up of the programmable first in first out of several degree of depth (FIFO) chip, and the port number of delay circuit equates with pulse-series generator output channel number.When pulse-series generator " resetted ", the parameter of delay circuit was by the spectrometer computer settings, and the parameter of each passage of delay circuit can independently set, thereby made the amount of delay of each output channel of pulse-series generator independently to programme.

The invention has the beneficial effects as follows: adopt delay circuit to realize the autonomous channel delay function of pulse-series generator, simple in structure, highly versatile.When adopting the present invention to carry out asynchronous triggerings, not extra CPU and the memory source that takies the spectrometer computing machine need not the reconstruction calculations that " incident-time " tabulate, and reduced the requirement to working environment.

Description of drawings

Fig. 1 is a structural representation of the present invention;

Fig. 2 and Fig. 3 are the structural representation of the embodiment of the invention;

Fig. 4 is the workflow diagram of the embodiment of the invention.

Embodiment

Characteristic of the present invention and other correlated characteristic are done further to set forth through embodiment below in conjunction with accompanying drawing.

Consult Fig. 1, the present invention mainly is made up of PLD, internal memory, delay circuit and interface chip.PLD is responsible for logic control on the plate of pulse-series generator, and it is connected with interface chip, internal memory and delay circuit respectively.Before pulse train was carried out, the pulse train data were through input end, interface chip and PLD, in the write memory.The term of execution of pulse train, the pulse train data are read from internal memory, through PLD and delay circuit, arrive output terminal.The port number of delay circuit equates with pulse-series generator output channel number.When pulse-series generator " resetted ", the parameter of delay circuit was by the spectrometer computer settings, and the parameter of each passage of delay circuit can independently set, thereby made the amount of delay of each output channel of pulse-series generator independently to programme.

Consult Fig. 2 and Fig. 3, delay circuit can adopt the programmable fifo chip of the degree of depth (hereinafter to be referred as FIFO), also can adopt the PLD in the pulse-series generator to make up FIFO.If pulse-series generator has N output channel, then need N FIFO.Each FIFO is corresponding with an output channel of pulse-series generator.The degree of depth of FIFO when pulse-series generator " resets " by the spectrometer computer settings, the depth D of each FIFO _j(j=1,2 ... N) can independently set.

When pulse-series generator " resetted ", " incident-time " tabulation was downloaded in the internal memory through interface chip, and pulse-series generator is in " awaiting orders " state then.If comprise M group data in the tabulation, then each group data is E _i-T _i(i=1,2 ... M).Wherein, E _iBe a N bit, be used to represent the state of N output channel.If S _IjExpression E _iThe j position, E then _i=(S _I1S _I2S _IN).T _iExpression E _iRetention time.

Consult Fig. 4, workflow of the present invention is following:

⑴, pulse-series generator reset; The setting data number M is set the depth D of each FIFO _j(j=1,2 ... N); The counter C of each passage _j=0 (j=1,2 ... N); Internal memory pointer i=0.Pulse-series generator is in " awaiting orders " state;

, if the pulse-series generator that is in " awaiting orders " state receives that " startups " that the spectrometer computing machine sends order execution in step ⑶; Otherwise execution in step ⑵;

, under the control of PLD, from internal memory, read " incident-time " tabulation in data E _i-T _i, internal memory pointer i+1;

, for output channel j, with data S _Ij-T _iWrite among the FIFO, as C _jIndividual data, counter C _j+ 1;

, if C _j=D _j, the FIFO of expression passage j has write full, execution in step ⑹; Otherwise execution in step ⑺;

⑹ first data among, the FIFO are used for the more output state of new tunnel j, and keep the corresponding time.Execution in step ⑺;

⑺ and all data among the FIFO shift forward, promptly second data is placed on the position of original first data, and the 3rd data are placed on the position of original second data, by that analogy, counter C _j-1, execution in step ⑻;

, if i=M, promptly the data in the internal memory all are read, and then finish; Otherwise execution in step ⑶.

In the above-mentioned steps, step ⑷～⑺ has only provided the situation to some passages.For hyperchannel, same steps as is to carry out synchronously.That is, the step ⑷ of all passages carries out synchronously, and step ⑸, ⑹ and ⑺ all so carry out.

Claims

1. pulse-series generator with autonomous channel delay function; It is characterized in that this pulse-series generator comprises PLD, internal memory, delay circuit and interface chip, PLD is connected with interface chip, internal memory and delay circuit respectively; The port number of delay circuit equates with the output channel number.

2. pulse-series generator according to claim 1 is characterized in that said delay circuit is made up of the programmable first in first out chip of several degree of depth, and each first in first out chip is corresponding with an output channel; The degree of depth of each first in first out chip is independently set, and the amount of delay of each corresponding output channel can be programmed.