KR101681862B1 - Method and apparatus for scan cell partition-based x-filling and scan cell reordering method for low power scan test - Google Patents

Abstract

The present invention relates to X-filling and low power scan cell rearrangement. According to an aspect, a low power scan test device comprises: a scan cell arrangement information obtaining unit configured to obtain scan cell arrangement information of a test target integrated circuit (IC); a partitioning unit configured to divide the test target IC into a plurality of partitions based on the scan cell arrangement information and configured to adjust the number of scan cells included in each partition; and a control unit configured to rearrange the scan cells per the divided partition and generate scan cell rearrangement information.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an X-FILLING and low power scan cell rearrangement apparatus and method based on a scan cell partition,

X-filling and low-power scan cell rearrangement, which prevents the excessive routing overhead from being suppressed, filling the unspecified bits of the test pattern of the same partition with the same value, And to a technical idea which can expect effective pattern generation and low-power scan rearrangement effect.

As the integration and complexity of the chip increases, the complexity of the test continues to increase proportionately. As an alternative to this, a scan test technique is widely used. As the number of scan cells increases, it is difficult to increase a scan test speed due to a power issue occurring during a scan shifting operation. This causes problems such as increasing test time and cost, or degrading test reliability.

To do this, a low-power scan test technique is introduced and divided into two major directions. ATPG-based and DFT-based techniques have been introduced to reduce the power by effectively filling the X-bit of the ATPG test pattern, respectively, or by inserting an additional DFT circuit. The insertion of the DFT circuit leads to a greater power reduction, but it has the disadvantage of increasing the hardware overhead and causing a clock skew problem especially for clock gating, which is known to give the best results.

Accordingly, a solution is being developed in which the ATPG-based technique is used in an appropriate overhead in parallel with the two methods. This has the advantage of efficiently reducing the power without burdening the hardware.

Nevertheless, in the existing routing-aware scan rearrangement scheme, there are a lot of limitations for low-power scan test and excessive switching activity occurs in the scan test consuming a lot of power compared to the conventional functional mode, IR-drop occurs. As a result, the high frequency offered by the tester does not allow scan shifting, which slows down the most heavily shifting operation in scan testing, resulting in increased test time, which ultimately leads to increased test costs.

Korean Patent No. 10-1539712 (Semiconductor device capable of low power scan test and method of testing the same) U.S. Patent No. 7,779,320 (Low power scan shifting with random-like test patterns) U.S. Patent No. 7,937,677 (Design-for-test-aware hierarchical design planning)

Low Power Test Method using Scan Cell Rearrangement for 3D ICs, Proceedings of the 2007 Spring Conference of the Institute of Electronics, Information and Communication Engineers, Vol.2015 No.1 [2015], pp. 457-458

After partitioning based on actual physical information, the pattern of the scan cells in each partition is analyzed to determine the X-filling value, and the scan rearrangement is performed to reduce the scanning overhead while minimizing the routing overhead. will be.

A low-power scan test apparatus according to one aspect includes a scan cell arrangement information acquisition unit for acquiring scan cell arrangement information of an IC (Integrated Circuit) to be tested, a plurality of A partitioning unit for dividing the plurality of scan cells into a plurality of partitions and adjusting the number of scan cells included in each partition, and a control unit for rearranging the scan cells according to the divided partitions and generating scan cell rearrangement information.

The partitioning unit adjusts the number of scan cells included in each partition by moving a partition boundary based on a specific scan cell among the scan cells in the partitioned partition.

The partitioning unit according to an embodiment determines a scan cell located at a nearest distance from a boundary of the divided partition as the specific scan cell.

The controller determines an X-filling value and rearranges the scan cell based on the determined X-filling value.

The control unit may generate a simulation pattern, obtain a response value through a simulation according to the generated simulation pattern, and use the obtained response value to calculate a transition probability ), And determines the X-filling value based on the calculated transition probability.

The controller calculates a weighted hamming distance (WHD) for a scan cell for each partitioned partition, and calculates a weighted hamming distance (WHD) And stitches are successively rearranged with respect to the scan cells corresponding to the scan cells.

According to one aspect of the present invention, there is provided a low power scan test method comprising: acquiring scan cell placement information of an integrated circuit (IC) to be tested; dividing the integrated circuit under test into a plurality of partitions based on the scan cell placement information; Adjusting the number of scan cells included in each partition, and rearranging the scan cells according to the divided partitions and generating scan cell rearrangement information.

The step of adjusting the number of the scan cells according to an exemplary embodiment of the present invention may include determining a scan cell located at a nearest distance from a boundary of the partitioned partition and moving the partition boundary based on the determined scan cell, Adjust the number of scan cells included in the partition.

The step of rearranging the scan cells according to an embodiment may include generating a simulation pattern, acquiring a response value through simulation according to the generated simulation pattern, Calculating a transition probability using the determined transition probability, determining the X-filling value based on the calculated transition probability, and determining the X-filling value based on the determined X- And rearranging.

The step of rearranging the scan cells according to an exemplary embodiment may include calculating a weighted hamming distance (WHD) for a scan cell for each divided partition, calculating a weighted hamming distance and rearranging and stitching successively the scan cells corresponding to the weighted hamming distance (WHD).

A method for testing a low power scan according to one aspect includes the steps of partitioning using scan cell placement information, generating a simulation pattern for X-filling a partitioned partition and a PI in each partition to 0 or 1, Performing a pattern simulation using the generated simulation pattern and calculating a transition probability from the result of the pattern simulation, filling the X-bit of each partition and PI in each partition with 0 or 1 Calculating a weighted hamming distance using the intra-partition scan cell pattern information, and rearranging the scan cells using the calculated weighted hamming distance.

The calculating of the transition probability according to an exemplary embodiment may include shifting a boundary of a partition of a scan cell using a perpendicular distance, temporarily rearranging each of the scan cells to which the boundary is shifted, And calculating the transition probability based on the rearranged scan cells.

According to one embodiment, low power shifting is possible while maintaining compatibility with EDA tools by adding a little work to the existing design flow.

According to one embodiment, a low power scan test is effectively possible without large routing overhead and additional circuitry.

According to one embodiment, increasing the scan shifting operating frequency may reduce test time and ultimately reduce overall test cost.

According to one embodiment, the suppression of excessive routing overhead is prevented, and the unspecified bits of the test pattern of the same partition are filled with the same value and then rearranged by scanning. Thus, effective pattern generation and low power scanning The effect of rearrangement can be brought at the same time.

According to an exemplary embodiment of the present invention, since partitioning is performed using actual cell location information after the actual layout, routing suppression according to the number of partitions can be controlled, and it is useful for low power scan shifting And the shifting speed can be remarkably improved.

According to one embodiment, there is no influence on the gate count that greatly affects the circuit size, and there is no factor that affects the existing functional operation since it can be implemented with only a small routing overhead without additional DFT circuit. It is compatible with design and easy to use.

1 is a view for explaining a low power scan test apparatus according to an embodiment.
2 is a view for explaining partitioning and scan rearrangement according to scan cell position information.
FIG. 3 is a view for explaining an embodiment of adjusting the partition size in consideration of the linear distance.
4 is a diagram illustrating a low power scan test method according to one embodiment.
5 is a diagram showing an example of compression for test data.
6 is a diagram for explaining an embodiment of applying test data for a scan test.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the rights is not limited or limited by these embodiments. Like reference symbols in the drawings denote like elements.

The terms used in the following description are chosen to be generic and universal in the art to which they are related, but other terms may exist depending on the development and / or change in technology, customs, preferences of the technician, and the like. Accordingly, the terminology used in the following description should not be construed as limiting the technical thought, but should be understood in the exemplary language used to describe the embodiments.

Also, in certain cases, there may be a term chosen arbitrarily by the applicant, in which case the meaning of the detailed description in the corresponding description section. Therefore, the term used in the following description should be understood based on the meaning of the term, not the name of a simple term, and the contents throughout the specification.

1 is a diagram illustrating a low power scan test apparatus 100 according to an embodiment.

In order to improve the speed of scan shifting, it is possible to improve the shifting speed sufficiently by using the speed within the range of the timing of the scan chain. However, this may result in a switching activity of about 0.2-0.3 Since the power rail is designed on the basis of the function operation of shifting the operation speed to the operating speed due to the power shortage in the scan shifting operation having the switching activity of 0.5, ). Since no additional logic is added between the scan chains, it is possible to solve problems such as PI (primary input) to FF, SI (scan input) to FF and power issue, ), Which can significantly reduce the test time. Since the setup time of PI and SI to FF can be sufficiently analyzed by the STA, it is necessary to solve the power issue in order to improve the scan shifting speed.

For this purpose, the low power scan test apparatus 100 may include a scan cell layout information obtaining unit 110, a partitioning unit 120, and a control unit 130. The low power scan test apparatus 100 may be implemented at least temporarily by the computing terminal. The computing terminal includes any type of electronic device such as a personal computer, a medical device, a smart phone, a tablet computer, and a wearable device. The scan cell layout information obtaining unit 110, the partitioning unit 120, and the control unit 130 may be physical and / or logical elements included in such electronic devices, respectively. For example, the scan cell placement information obtaining unit 110, the partitioning unit 120, and the control unit 130 may be implemented by dedicated hardware or general purpose computing resources controlled by software or an operating system. In addition, the scan cell placement information obtaining unit 110, the partitioning unit 120, and the control unit 130 may be implemented together on one chip, and thus may not be physically separated. Or by design changes. Accordingly, it is understood that the functions, operations and structures of the scan cell layout information obtaining unit 110, the partitioning unit 120, and the control unit 130 are distinguished from each other, but there may be cases where such a distinction is interpreted differently according to the embodiment .

Specifically, the scan cell layout information obtaining unit 110 obtains scan cell layout information of an IC (integrated circuit) to be tested.

Next, the partitioning unit 120 divides the test object integrated circuit into a plurality of partitions based on the scan cell placement information, and adjusts the number of scan cells included in each partition. According to one embodiment, the partitioning unit 120 may adjust the number of scan cells included in each partition by moving a partition boundary line based on a specific scan cell among the scan cells in the partitioned partition. More specifically, the partitioning unit 120 may determine the number of scan cells to be a specific scan cell by determining a scan cell located closest to the boundary of the divided partition.

The controller 130 rearranges the scan cells according to the partitioned partition and generates scan cell rearrangement information.

To this end, the controller 130 may determine the X-fill value and rearrange the scan cells based on the determined X-fill value. In a specific embodiment, the controller 130 may generate a simulation pattern and utilize it to determine the X-fill value. The controller 130 may obtain a response value through a simulation according to the generated simulation pattern and calculate a transition probability using the obtained response value. In addition, the controller 130 may determine the X-filling value based on the calculated transition probability.

Meanwhile, the controller 130 may rearrange the scan cells in the partition using a weighted hamming distance (WHD). Specifically, the controller 130 calculates a weighted hamming distance (WHD) for the scan cells for each divided partition, and calculates a weighted hamming distance (WHD) corresponding to the smallest weighted hamming distance Rearrangement and stitching can be performed continuously on the scan cells.

2 is a view for explaining partitioning and scan rearrangement according to scan cell position information.

The low power scan test apparatus can obtain the scan cell information by using the scan def file generated during the placement process belonging to the back-end operation, and can divide the entire design into the same size as shown at reference numeral 200 have. Then, the low power scan test apparatus selects the shortest scan cell with a straight line distance from the partition boundary, adjusts the size of the partition boundary line by moving the partition boundary line relative to the cell, adjusts the boundary line in an arbitrary direction, You can adjust the size of the partitions to be similar.

FIG. 3 is a view for explaining an embodiment of adjusting the partition size in consideration of the linear distance.

The low power scan test apparatus can select a scan cell having the shortest straight line distance at a partition boundary line, such as a reference numeral 310, and adjust the size while moving a partition boundary line with respect to the cell. At this time, the low power scan test apparatus can adjust the partition size so that the number of scan cells in each partition may be the same or similar while moving the boundary line in the arrow direction of FIG. At this time, the straight line distance can be calculated by Equation (1).

[Equation 1]

Here, (x ₁ , y ₁ ) is the x and y coordinates of each scan cell, and ax + by + c = 0 is each partition boundary line.

The low-power scan test apparatus then generates a simulation pattern, and the number of simulation patterns required therefor can be calculated by Equation (2).

&Quot; (2) "

는 시뮬레이션 패턴의 개수이고,

는 파티션 개수를 나타낸다.

Is the number of simulation patterns,

Represents the number of partitions.

The simulation pattern can be generated as follows.

The first pattern is generated in which the entire PI (primary input) is 0-filled and the remaining scan cell values are left as X-bits. In the second case, the entire PI is applied with 1-fill, This creates a pattern that leaves a bit, so '+2' is followed by the last term in the above expression. Next, from the first partition, a pattern is generated in which 0-fill and 1-fill only the values of the scan cells in the partition are left, and the remaining cells and the PI are left as X-bits, so that [Expression 2] can be generated.

Then, the low-power scan test apparatus calculates a transition probability by obtaining a response value through a simulation and calculates an X-fill value when each X-bit is extracted as a pattern in each partition and PI Can be calculated through Equation (3).

&Quot; (3) "

는 각 패턴에서의 전이 확률(transition probability)을 나타낸다.

Represents a transition probability in each pattern.

는 입출력 되는 전이 확률(transition probability)의 합을 나타낸다.

Represents the sum of the transition probabilities of input and output.

와

는 i 번째 셀 값과 (i+1) 번째 셀 값 사이의 입출력 되는 전이 확률(transition probability)의 합을 나타낸다.

Wow

Represents a sum of transition probabilities of input and output between the ith cell value and the (i + 1) th cell value.

은 [수학식 4]로 산출될 수 있다.Meanwhile,

Can be calculated by the following equation (4).

&Quot; (4) "

은 는 i 번째 셀 값과 (i+1) 번째 셀 값 사이의 스위칭 활동을 나타낸다. 일례로,

또는

가 X인 경우,

는 0.5이다.

Represents the switching activity between the ith cell value and the (i + 1) th cell value. For example,

or

Is X,

Is 0.5.

4 is a diagram illustrating a low power scan test method according to one embodiment.

The low power scan test method according to an exemplary embodiment of the present invention as shown in FIG. 4 includes the steps of determining characteristic configurations of the present invention, that is, a configuration for determining an X-filling value for each partition, a configuration for rearranging scan cells in a partition, Can be implemented.

In particular, the low power scan test method according to an exemplary embodiment acquires scan cell placement information (step 401).

A low power scan test method according to one embodiment performs scan cell partitioning (step 402).

The low power scan test method uses the scan def file generated during the batch process belonging to the backend process to fetch scan cell information and partition the entire design with the same size. Then, the low power scan test method selects the shortest scan cell with a straight line distance from the partition boundary, and adjusts the size by moving the partition boundary with respect to the cell. At this time, it is possible to adjust the partition size so that the number of scan cells in each partition is the same or similar by adjusting the boundary line in a specific arrow direction.

Next, a low power scan test method according to one embodiment estimates pattern simulation and transition probability (step 403).

At this time, the low power scan test method generates a simulation pattern considering the number of simulation patterns. Specifically, a first pattern is generated in which the entire PI is 0-filled and the remaining scan cell values are left as X-bits. In the second case, 1-fill is applied to the entire PI, and the remaining scan cell values are X- Create a leaving pattern.

Next, the low-power scan test method can generate a pattern in which only 0-fill, 1-fill after the first partition, and the remaining cells and PI are left as X-bits.

The low-power scan test method can calculate the transition probability after acquiring the response value through simulation and calculate the X-filling value when the X-bit is extracted as a pattern in each partition and PI.

A low power scan test method according to one embodiment performs scan rendering-aware X-fill (step 404).

The low power scan test method can perform simple scan cell rearrangement before TP estimation after pattern simulation. This is a process to consider the rearrangement to be performed later. Since the rearrangement of the scan to be performed later will be rearranged to minimize the transition, the TP operation can be performed after the rearrangement so as to minimize the transition.

Next, a low power scan test method according to one embodiment transmits low power scan rearrangement and rearrangement information (step 405).

5 is a diagram showing an example of compression for test data.

5 shows a pattern simulation and transition probability, i.e., TP calculation example, by a low power scan test apparatus. As shown in the figure, a simple scan cell rearrangement is performed before TP estimation after pattern simulation. This is a process to consider the rearrangement to be performed later. Since the rearrangement of the scan to be performed later will be rearranged so as to minimize the transition, the TP operation is virtually rearranged so that the transition is minimized.

As shown in FIG. 5, since the TP value (14.5) of case 2 is a value smaller than the TP value (18.0) of case 1, in this example, partition 1 can be applied to all patterns have. In the present specification, such X-filling can be defined as scan rearrangement-aware X-filling.

Next, the low power scan test apparatus calculates a weighted hamming distance (WHD), and successively rearranges and stitches cells having the smallest distance value in the partition. WHD is calculated by the following equation (5).

&Quot; (5) "

,

는 입력 데이터와 출력 응답에 상응하는 거리를 나타낸다.In Equation (5)

,

Represents the distance corresponding to the input data and the output response.

는 i 번째와 j 번째 엘리먼트에 대하 가중치를 나타낸다.

Represents a weight for the i-th and j-th elements.

는 n번째 테스트 패턴에 있어 i 번째와 j 번째 입력 테스트 데이터에 대한 비트를 나타낸다.

Represents the bits for the i-th and j-th input test data in the n-th test pattern.

는 n번째 테스트 패턴에 있어 i 번째와 j 번째 출력 테스트 데이터에 대한 비트를 나타낸다.

Represents the bits for the i-th and j-th output test data in the n-th test pattern.

6 is a diagram for explaining an embodiment of applying test data for a scan test.

6 shows an example of calculation and rearrangement of a weighted hamming distance (WHD). 6 is an example of assuming that there are six scan cells in a partition, three test patterns in total, and a case where a scan chain is stitched (610). The weighted hamming distance (WHD) is calculated for all possible scan cells when the first scan cell connected to SI is determined to be x1 and the scan cell to be stitched to be determined, It is the same as the value shown in the last row of table 620. At this time, the smallest value is a scan cell in which x6 is connected to x1, and the operation is repeated until all the cells are rearranged.

The low-power scan test processes the scan cell rearrangement information to be used for routing.

As a result, by using the present invention, it is possible to prevent the excessive routing overhead from being suppressed, and the unspecified bits of the test pattern of the same partition are filled with the same value, Low-power scan re-arrangement effect simultaneously.

Particularly, since the present invention uses the actual cell location information after the actual layout to partition, it is possible to control the routing restraint according to the number of partitions, and it is useful for low power scan shifting Which can lead to a significant shifting speed improvement.

In addition, it can be implemented with few routing overheads without additional DFT circuitry, it does not affect the gate count, which greatly affects the circuit size, and it does not affect the existing functional behavior. It is easy to use.

The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the apparatus and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA) A programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (12)

A scan cell layout information acquisition unit for acquiring scan cell layout information of an integrated circuit (IC) to be tested;
A partitioning unit that divides the test object integrated circuit into a plurality of partitions based on the scan cell placement information and adjusts the number of scan cells included in each partition; And
A controller for rearranging the scan cells according to the partitioned partition and generating scan cell rearrangement information,
And a scan cell array. The method according to claim 1,
The partitioning unit,
And adjusting the number of scan cells included in each partition while moving a partition boundary line based on a specific scan cell among the scan cells in the partitioned partition. 3. The method of claim 2,
The partitioning unit,
And determines a scan cell located at a nearest distance from a boundary of the divided partition as the specific scan cell. The method according to claim 1,
Wherein,
Determining an X-filling value, and rearranging the scan cells based on the determined X-filling value. 5. The method of claim 4,
Wherein,
Generating a simulation pattern, acquiring a response value through a simulation according to the generated simulation pattern, calculating a transition probability using the obtained response value, Wherein the X-peeling value is determined based on a transition probability. The method according to claim 1,
Wherein,
Calculating a weighted hamming distance (WHD) for a scan cell for each divided partition, and calculating a weighted hamming distance (WHD) for a scan cell corresponding to the smallest weighted hamming distance (WHD) Arrangement of scan cells for rearrangement and stitching. Acquiring scan cell arrangement information of an integrated circuit (IC) to be tested;
Dividing the test object integrated circuit into a plurality of partitions based on the scan cell placement information, and adjusting the number of scan cells included in each partition; And
A step of rearranging scan cells according to the divided partitions and generating scan cell rearrangement information
Wherein the scan cells are arranged in rows and columns. 8. The method of claim 7,
Wherein the adjusting the number of the scan cells comprises:
A scan cell rearrangement method of determining a scan cell located at a nearest distance from a boundary of the divided partition and adjusting a number of scan cells included in each partition while moving a partition boundary based on the determined scan cell . 8. The method of claim 7,
The step of rearranging the scan cells comprises:
Generating a simulation pattern;
Obtaining a response value through simulation according to the generated simulation pattern;
Calculating a transition probability using the obtained response value;
Determining an X-filling value based on the calculated transition probability; And
And rearranging the scan cells based on the determined X-
Wherein the scan cells are arranged in rows and columns. 8. The method of claim 7,
The step of rearranging the scan cells comprises:
Calculating a weighted hamming distance (WHD) for a scan cell for each partitioned partition; And
And successively rearranging and stitching the scan cells corresponding to the smallest weighted hamming distance (WHD) in the calculation result
Wherein the scan cells are arranged in rows and columns. Partitioning using scan cell placement information;
Generating a simulation pattern for X-filling each partitioned partition and a scan cell in each partition with 0 or 1;
Performing a pattern simulation using the generated simulation pattern, and calculating a transition probability as a result of the pattern simulation;
Filling the X-bit of each partition and each of the intra-partition scan cells with 0 or 1;
Calculating a weighted hamming distance using the intra-partition scan cell pattern information; And
And rearranging the scan cells using the calculated weighted hamming distance
Wherein the scan cells are arranged in rows and columns. 12. The method of claim 11,
The step of calculating the transition probability comprises:
The boundary of the partitions of the scan cells is shifted by using the perpendicular distance, the respective scan cells to which the boundary is moved are temporarily rearranged, and the transition probability is calculated based on the temporarily rearranged scan cells step
Wherein the scan cells are arranged in rows and columns.

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