JP2019020822A - Programmable controller - Google Patents

Abstract

To enable fast response to external inputs by exchanging data at high speed between a CPU module and an IO module.SOLUTION: A programmable controller includes a CPU module 1, one or more IO modules 2, and an IO bus 3 connecting the CPU module 1 and the IO modules 2. A first IO module of the IO module 2 has a bus capture unit for capturing data of the IO module 2 flowing through the IO bus. Based on the signal related to the read access from the CPU module 1, the bus capture unit fetches the data of second IO modules 202, 203.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an IO access method between a CPU module and an input / output (IO) module of a programmable controller that controls operations of equipment and a mechanical system by a sequence program.

  A programmable controller (hereinafter referred to as “PLC”) is a control device that cyclically executes a ladder program created by a user, and is used to control various machine facilities and plant facilities installed in factories and the like. Widely used as a general-purpose control device.

  The PLC captures the operating status of the mechanical equipment as ON / OFF information as an external input from a device such as a sensor or switch as a digital signal via an input module, or analogizes plant equipment pressure information or temperature information. It takes in as a signal and performs calculations using a sequence program created by the user.

  Then, the calculation result is transmitted as a digital signal or an analog signal to the power source of the machine facility, the valve of the plant facility, or the like via the output module, thereby realizing advanced control of the entire facility. Taking input data from the input module and outputting the operation result to the output module is called “IO refresh”. One means for performing control by PLC at high speed is to perform this IO refresh at high speed.

  As a technique for speeding up the control by the PLC, for example, in Patent Document 1, “the update cycle of each module can be set in the input / output module allocation information, and the update cycle is set when the refresh process is executed for each scan”. Technology that reduces the number of bus accesses between the CPU module and the IO module and speeds up the scan time by refreshing only the modules that are equal to or longer than the updated update cycle. " Has been.

Japanese Patent Laying-Open No. 2015-60377

  In Patent Document 1 described above, the number of bus accesses is reduced, but it is not disclosed that the internal operation of the module is controlled using external input ON / OFF information as a trigger. In addition, no consideration is given to a method for transferring data between the IO module and the CPU module at high speed.

  Therefore, an object of the present invention is to enable a high-speed response from an external input by transferring data at high speed between a CPU module and an IO module.

  As a preferred example of the present invention, a CPU module, one or more IO modules, and an IO bus connecting the CPU module and the IO module are provided, and the first IO module of the IO modules has an IO flowing through the IO bus. The bus capture unit is a programmable controller that has a bus capture unit that captures module data, and that captures data of the second IO module based on a signal related to read access from the CPU module.

  According to the present invention, a high-speed response from an external input is possible.

It is a block diagram of the programmable controller which concerns on an Example. It is a time chart of read / write access of IO bus. It is a time chart which shows the relationship of the calculation of IO refresh on IO bus. It is a figure explaining the function of the BUS controller of a module with a bus capture function. FIG. 5 is a relationship diagram of external input capture timing and refresh. It is a block diagram of the programmable controller which concerns on a 2nd Example. It is an image figure of the synchronization in a 2nd Example. It is a time chart of the write access on the CPU module side in the second embodiment.

  Hereinafter, embodiments of a PLC with a bus capture function according to the present invention will be described with reference to the drawings.

  FIG. 1 is a configuration diagram of a PLC according to an embodiment of the present invention.

  The CPU module 1 of the PLC includes an MPU 11a for calculating sequence programs, a communication port 12 for communicating with peripheral devices such as personal computers, a ROM 13a for storing sequence programs and system programs, and data used for calculating sequence programs. BUS controller M16 (M is a “master”) having a RAM 14a for storing data, a DMAC 15a for transferring data between the RAM 14a and an IO module connected to the IO bus 3, an address output unit serving as an interface with the IO bus 3, and a data input / output unit. ”).

  The CPU module 1 needs to know in advance which IO module is mounted in the IO slot 0, IO slot 1,... IO slot n. Normally, information such as an input / output type and data size can be recognized from the CPU module 1 as status information on the IO module side.

The IO module 2 includes a module 201 with a bus capture function in addition to the IO modules (input module 202 and output module 203) for digital signals and analog signals.
Reference numeral 3 denotes an IO bus through which an address / data signal 21 flows. Reference numeral 22 denotes a slot n selection signal for selecting an arbitrary n from the slot 0, and the slot n selection signal is configured to send a signal only to the IO module mounted in the IO slot n. Reference numeral 23 denotes a read strobe signal. Reference numeral 24 denotes a write strobe signal.

  The CPU module 1 accesses each IO slot via the IO bus 3. In addition to the address and data of the IO bus 3, a slot selection signal 22, a read strobe signal 23, and a write strobe signal 24 for selecting a slot are required. The slot selection signal 22 is output from the CPU module 1 for each individual slot, but the CPU module 1 outputs the slot selection signal 22 by decoding the address.

  The module 201 with bus capture function is an MPU 11b that performs sequence program operations, a ROM 13b that stores sequence programs and system programs, a RAM 14b that stores data used for sequence program operations, and an address that is an interface with the IO bus 3. BUS controller S17 (S represents “slave”) having an output unit and a data input / output unit.

  FIG. 2 is a time chart showing read access and write access of the CPU module 1 on the IO bus 3. At the time of read access, the address / data signal 21 flows to the IO bus 3 at the timing when the slot n selection signal 22 for selecting the input module of the IO slot n changes from the high level to the low level. At the timing when the read strobe signal 23 changes from the high level to the low level, read data flows from the input module of the IO slot n to the IO bus 3.

  During write access, the address / data signal 21 flows to the IO bus 3 at the timing when the slot n selection signal 22 for selecting the output module of the IO slot n changes from the high level to the low level. Write data from the output module of the IO slot n flows to the IO bus 3 at the timing when the write strobe signal 24 changes from the high level to the low level.

  The CPU module 1 performs this read / write access to the IO module mounted in the IO slot. As shown in FIG. 3, first, input refresh for fetching data from the input module is performed, and after executing the user program with the data, output refresh for the output module is performed. This is called scanning, and is performed cyclically to control the PLC.

  Here, an operation when the module 201 with a bus capture function is mounted in the IO slot 0 when performing the IO refresh with the configuration shown in FIG. 1 will be described. When the CPU module 1 performs the input refresh for the input module of the IO slot 1, the slot selection signal is asserted only for the slot 1 and the slot selection signals for the other slots are not asserted.

  This is because the CPU module 1 can assert only a plurality of slot selection signals or uniquely determined slot selection signals by decoding the slot address included in the address. Therefore, input modules in other slots do not output data.

  FIG. 4 is a diagram illustrating the function of the BUS controller S17 of the module 201 with a bus capture function. The bus capture unit 42 always looks at the address / data signal 21 flowing through the IO bus 3, and when the CPU module 1 access to the address of the IO slot 1 is recognized, the slot 1 of the data transfer target slot table 41 is “ It is possible to recognize that it is “necessary” and to acquire data at the time of the read access.

  The data transfer target slot table 41 is stored in the memory of the BUS controller S17.

  When the read access to the IO slot 1 is executed, the bus capture unit 42 can decode the slot address included in the address / data signal 21 on the IO bus 3 and recognize that the access is to another slot. . For example, when a normal IO module is mounted in Slot0, the IO module 2 cannot see the slot selection signal of Slot1. On the other hand, the module 201 with a bus capture function decodes the slot address included in the address signal and determines that the access is to Slot1.

  Therefore, when there is an access to a preset data transfer target slot table 41, the read data can be directly fetched.

  The information in the data transfer target slot table specifies the presence / absence of input modules and slot positions used by the module 201 with bus capture function when assigning IO modules from a programming tool on a PC, After transferring to 1, the CPU module 1 can obtain the necessary information by transferring to the module 201 with bus capture function.

  In the first embodiment, it is possible to acquire data at the time of read access from the IO bus 3 based on the setting of the data transfer target slot table 41 indicating slots that can be read or written by the module 201 with a bus capture function.

  Therefore, it is not necessary for the CPU module 1 to take in the input data in the slot 1 and then transfer the input data to the module 201 with the bus capture function in the slot 0, and the input data can be taken in at a higher speed.

  The bidirectional buffer 43 shown in FIG. 4 outputs data from the internal bus 45 of the BUS controller S17 to the IO bus 3 based on the enable signal from the bus capture unit 42 or the normal access bus control unit 44. Further, the bidirectional buffer 43 can input data from the IO bus 3 to the BUS controller S17 based on an enable signal from the bus capture unit 42 or the normal access bus control unit 44.

  The normal access bus control unit 44 captures data and outputs an enable signal for output to the bidirectional buffer 43 for the selection signal of slot 0 which is its own selection signal. For example, when the module 201 with a bus capture function is mounted in the slot 0, the bus capture unit 42 cannot see the slot selection signal of the slot 1, but decodes the slot address included in the address signal, It turns out that the access is to slot 1, and an enable signal is output to bidirectional buffer 43 so that data in slot 1 can be exchanged.

  In general, in a high-function module that is an IO module, the internal operation of the module is controlled using ON / OFF information of an external input signal as a trigger. Therefore, in order to speed up the response from the input signal, the module itself can also have a function of capturing the input signal.

  In that case, there are restrictions on the number of points that can be physically input. Therefore, a high function module that takes in an external input signal and performs control based on the input needs to receive the input data from the CPU module.

  FIG. 5 is a time chart showing the relationship between external input capture timing and refresh when the high function module receives the input data from the CPU module. Assuming that the actual change in the input signal is point A, the subsequent input refresh of the CPU module is performed at point B, and that data is passed to the high-function module at point C where the CPU module has performed output refresh. become.

  In FIG. 5, ON / OFF (point A) of the external input signal can be recognized by the CPU module when the CPU module executes input refresh (point B). This input refresh is performed cyclically as shown in FIG.

  According to the first embodiment, since data is taken into the module 201 with a bus capture function at point B, a high-speed response from an external input can be made.

  In the first embodiment, the embodiment in which data is captured from the input module to the module 201 with the bus capture function has been described. In the second embodiment, the case where the computation load is distributed in the module 201 with a bus capture function will be described with reference to FIG.

  Here, the CPU module 1 performs an operation on the input module 202 in the slot 1 and the output module 203 in the slot 2, and the module 201 with a bus capture function in the slot 0 has the input module 204 in the slot 3 and the slot 4 in the module 4. Assume that the calculation is performed on the output module 205.

  The user sets the information in the data transfer target slot table 41 in advance for the module 201 with a bus capture function in slot 0, so that the module 201 with a bus capture function is an input / output module corresponding to the slot “necessary”. It is possible to recognize the timing of input refresh and output refresh.

  As shown in FIG. 7, the CPU module 1 performs IO refresh for the input module 202 in the slot 1 and the output module 203 in the slot 2. On the other hand, the bus capture function module (high function module) 201 can recognize the read access from the slot 3 and the write access to the slot 4 by the bus capture unit 42, capture the read data from the slot 3, and the user user. It is possible to execute a program and output a calculation result to slot 4.

  FIG. 8 shows a time chart at the time of write access to the slot 4 on the CPU module 1 side.

  At the time of write access, the address / data signal 21 flows to the IO bus 3 at the timing when the slot n selection signal 22 for selecting the IO slot n changes from the high level to the low level. At the timing when the write strobe signal 24 changes from the high level to the low level, the data obtained as a result of the calculation by the module 201 with the bus capture function flows as write data to the output module of the IO slot n via the IO bus 3. .

  Since the slot 4 is not subject to calculation by the user program on the CPU module 1, only the address is output and the data is in a high impedance (Hi-Z) state. Thus, the module 201 with a bus capture function can output the calculation result to the slot 4 at this timing.

  The timing of the IO refresh is triggered by the CPU module 1 that is a bus master, and the module 201 with a bus capture function that is a bus slave follows the timing.

According to the second embodiment, in synchronization with the IO refresh of the CPU module 1, the module 201 with a bus capture function shares the control using the input / output data of a part of the IO modules 2 with the CPU module 1. It is also possible to distribute the load.
Therefore, it is possible to easily distribute the load while synchronizing with the CPU module.

DESCRIPTION OF SYMBOLS 1 ... CPU module, 2 ... IO module, 3 ... IO bus, 16 ... BUS controller M, 17 ... BUS controller S, 41 ... Data transfer object slot table, 42 ... Bus capture part, 201 ... Module with bus capture function

Claims (5)

A CPU module, one or more IO modules, and an IO bus connecting the CPU modules and the IO modules;
The first IO module among the IO modules has a bus capture unit that captures data of the IO module flowing in the IO bus,
The programmable controller, wherein the bus capture unit captures data of the second IO module based on a signal related to read access from the CPU module. 2. The programmable controller according to claim 1, wherein data exchange target slot information is set in the first IO module, and the first IO module is set for the slot set in the data transfer target slot information. A programmable controller characterized by performing arithmetic processing. 3. The programmable controller according to claim 2, wherein the bus capture unit determines a slot to be accessed by decoding a slot address included in an address signal flowing through the IO bus. 4. The programmable controller according to claim 3, wherein the first IO module performs write access to the calculated data to the third IO module mounted in the determined slot. 5. The programmable controller according to claim 4, wherein a data signal for write access to the third IO module is in a high impedance state.

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