JP6971668B2 - Programmable controller - Google Patents

Description

The present invention relates to an IO access method between a CPU module and an input / output (IO) module of a programmable controller that controls the operation of equipment or a mechanical system by a sequence program.

A programmable controller (hereinafter referred to as "PLC") is a control device that cyclically executes a ladder program created by a user, and is used to control various mechanical equipment and plant equipment installed in factories and the like. Widely used as a general-purpose control device.

The PLC either captures the operating status of the mechanical equipment from equipment such as sensors and switches as ON / OFF information as an external input via the input module as a digital signal, or captures the pressure information and temperature information of the plant equipment as analog. It is captured as a signal and calculated by a sequence program created by the user.

Then, the calculation result is transmitted as a digital signal or an analog signal to the power source of the mechanical equipment or the valve of the plant equipment via the output module, and advanced control of the entire equipment is realized. Taking in input data from this input module and outputting the calculation result to the output module is called "IO refresh". One of the means for performing control by PLC at high speed is to perform this IO refresh at high speed.

As a technique for speeding up the control by this PLC, for example, in Patent Document 1, "the update cycle of each module can be set in the input / output module allocation information, and the update cycle is set when the refresh process of each scan is executed. By refreshing only modules that are equal to or longer than the updated cycle, the number of bus accesses between the CPU module and IO module is reduced, and the scan time is increased. " Has been done.

Japanese Unexamined Patent Publication No. 2015-60377

Although the above-mentioned Patent Document 1 reduces the number of bus accesses, it does not disclose that the operation inside the module is controlled by the ON / OFF information of the external input as a trigger. Further, the method of high-speed data transfer between the IO module and the CPU module is not considered.

Therefore, an object of the present invention is to enable a high-speed response from an external input by passing data between the CPU module and the IO module at high speed.

As a preferable example of the present invention, a CPU module, one or more IO modules, and an IO bus connecting the CPU module and the IO module are provided, and the first IO module of the IO modules is an IO flowing through the IO bus. It has a bus capture unit that captures the data of the module, and the bus capture unit is a programmable controller that captures the data of the second IO module based on the signal related to the read access from the CPU module.

According to the present invention, a high-speed response from an external input is possible.

It is a block diagram of the programmable controller which concerns on embodiment. It is a time chart of read / write access of IO bus. It is a time chart which shows the relationship of the operation of IO refresh on the IO bus. It is a figure explaining the function of the BUS controller of the module with a bus capture function. It is a relationship diagram of the capture timing of the external input and the refresh. It is a block diagram of the programmable controller which concerns on 2nd Embodiment. It is an image diagram of synchronization in the 2nd Example. It is a time chart of the write access on the CPU module side in the 2nd embodiment.

Hereinafter, an embodiment of the PLC with a bus capture function according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a PLC according to an embodiment of the present invention.

The PLC CPU module 1 includes an MPU 11a that performs sequence program calculations, a communication port 12 for communicating with peripheral devices such as a personal computer, a ROM 13a for storing sequence programs and system programs, and data used for sequence program calculations. A BUS controller M16 (M is a "master") having a RAM 14a for storing data, a DMAC15a for transferring data between the RAM 14a and an IO module connected to the IO bus 3, an address output unit and a data input / output unit which are interfaces with the IO bus 3. ”), Consists of.

The CPU module 1 needs to know in advance what kind of IO module is mounted in the IO slot 0, the IO slot 1, ... The IO slot n. Normally, on the IO module side, information such as input / output type and data size can be recognized from the CPU module 1 as status information.

The IO module 2 includes a module 201 with a bus capture function in addition to an IO module (input module 202 and output module 203) for digital signals and analog signals.
Reference numeral 3 indicates an IO bus, through which the address / data signal 21 flows. Reference numeral 22 denotes a slot n selection signal for selecting an arbitrary n from the slot 0, and the slot n selection signal is configured to send a signal only to the IO module mounted in the IO slot n. Reference numeral 23 indicates a lead strobe signal. Reference numeral 24 indicates a light strobe signal.

The CPU module 1 accesses each IO slot via the IO bus 3. In addition to the address and data of the IO bus 3, a slot selection signal 22, a read strobe signal 23, and a write strobe signal 24 for selecting a slot are required. The slot selection signal 22 is output from the CPU module 1 for each slot, and the CPU module 1 outputs the slot selection signal 22 by decoding the address.

The module 201 with a bus capture function is an interface with an MPU 11b for performing sequence program calculations, a ROM 13b for storing sequence programs and system programs, a RAM 14b for storing data used for sequence program calculations, and an IO bus 3. It is composed of a BUS controller S17 (S represents a "slave") having an output unit and a data input / output unit.

FIG. 2 is a time chart showing read access and write access of the CPU module 1 on the IO bus 3. At the time of read access, the address flows to the IO bus 3 in the address / data signal 21 at the timing when the slot n selection signal 22 that selects the input module of the IO slot n changes from the high level to the low level. Read data flows from the input module of the IO slot n to the IO bus 3 at the timing when the read strobe signal 23 changes from the high level to the low level.

At the time of write access, the address flows to the IO bus 3 in the address / data signal 21 at the timing when the slot n selection signal 22 that selects the output module of the IO slot n changes from the high level to the low level. At the timing when the light strobe signal 24 changes from the high level to the low level, the write data from the output module of the IO slot n flows to the IO bus 3.

The CPU module 1 performs this read / write access to the IO module mounted in the IO slot. As shown in FIG. 3, first, input refresh for fetching data from the input module is performed, user program is executed with the data, and then output refresh for the output module is performed. This is called scanning, and it is cyclically controlled as a PLC.

Here, in the configuration shown in FIG. 1, the operation when the module 201 with the bus capture function is mounted in the IO slot 0 when performing the IO refresh will be described. When the CPU module 1 refreshes the input module of the IO slot 1, only the signal for slot 1 is asserted as the slot selection signal, and the slot selection signal for other slots is not asserted.

In this method, the CPU module 1 can assert only a plurality of slot selection signals or a uniquely determined slot selection signal by decoding the slot address included in the address. Therefore, the input modules of other slots do not output data.

FIG. 4 is a diagram illustrating the function of the BUS controller S17 of the module 201 with a bus capture function. The bus capture unit 42 always looks at the address / data signal 21 flowing through the IO bus 3, and when it recognizes the access of the CPU module 1 to the address of the IO slot 1, the slot 1 of the data transfer target slot table 41 becomes ". It is possible to recognize that it is "required", and it is possible to acquire the data at the time of the read access.

The data transfer target slot table 41 is stored in the memory of the BUS controller S17 or the like.

When the read access to the IO slot 1 is executed, the bus capture unit 42 decodes the slot address included in the address of the address / data signal 21 on the IO bus 3 and can recognize that the access is to another slot. .. For example, if a normal IO module is implemented in Slot 0, IO module 2 cannot see the slot selection signal of Slot 1. On the other hand, the module 201 with the bus capture function decodes the slot address included in the address signal and determines that the access is to Slot1.

Therefore, when there is an access to the preset data transfer target slot table 41, the read data can be directly taken in.

The information of this data transfer target slot table specifies the presence / absence of the input module used by the module 201 with the bus capture function and the slot position when allocating the IO module from the programming tool on the PC, and the program can be programmed into the CPU module. After transferring to 1, it can be obtained by transferring necessary information from the CPU module 1 to the module 201 with a bus capture function.

In the first embodiment, it is possible to acquire the data at the time of read access from the IO bus 3 based on the setting of the data transfer target slot table 41 indicating the slots that the module 201 with the bus capture function can read or write.

Therefore, it is not necessary for the CPU module 1 to take in the input data of the slot 1 and then pass the input data to the module 201 with the bus capture function of the slot 0, and it is possible to take in the input data at a higher speed.

The bidirectional buffer 43 shown in FIG. 4 outputs data from the internal bus 45 of the BUS controller S17 to the IO bus 3 based on the enable signal from the bus capture unit 42 or the normal access bus control unit 44. Further, the bidirectional buffer 43 can input data from the IO bus 3 to the BUS controller S17 based on the enable signal from the bus capture unit 42 or the normal access bus control unit 44.

The normal access bus control unit 44 captures data for the selection signal of slot 0, which is its own selection signal, and outputs an enable signal for output to the bidirectional buffer 43. For example, when the module 201 with a bus capture function is mounted in slot 0, the bus capture unit 42 decodes the slot address included in the address signal, although the slot selection signal of slot 1 cannot be seen. It is found that the access is to slot 1, and an enable signal is output to the bidirectional buffer 43 so that the data in slot 1 can be exchanged.

Generally, in a high-performance module which is an IO module, the operation inside the module is controlled by using ON / OFF information of an external input signal as a trigger. Therefore, in order to speed up the response from the input signal, the module itself can also have a function of capturing the input signal.

In that case, there will be restrictions on the points that can be physically input. Therefore, a high-performance module that takes in an external input signal and controls based on the input needs to have the input data passed from the CPU module.

FIG. 5 is a time chart showing the relationship between the acquisition timing of the external input and the refresh when the high-performance module has the input data passed from the CPU module. If the actual change in the input signal is at point A, the subsequent input refresh of the CPU module is performed at point B, and the data is passed to the high-performance module at point C where the CPU module has performed output refresh. become.

In FIG. 5, ON / OFF (point A) of the external input signal can be recognized by the CPU module when the CPU module executes input refresh (point B). This input refresh is cyclical, as shown in FIG.

According to the first embodiment, since the data is taken into the module 201 with the bus capture function at the point B, a high-speed response from the external input can be made.

In the first embodiment, an embodiment in which data is taken from the input module to the module 201 with a bus capture function has been described. In the second embodiment, the case where the calculation load is distributed by the module 201 with the bus capture function will be described with reference to FIG.

Here, the CPU module 1 performs an operation targeting the input module 202 of the slot 1 and the output module 203 of the slot 2, and the module 201 with the bus capture function of the slot 0 has the input module 204 of the slot 3 and the slot 4 It is assumed that the calculation is performed for the output module 205.

These are input / output modules corresponding to Slot "necessary" by the user by setting the information of the data transfer target slot table 41 to the module 201 with the bus capture function in slot 0 in advance. The timing of input refresh and output refresh can be recognized.

As shown in FIG. 7, the CPU module 1 performs IO refresh for the input module 202 in slot 1 and the output module 203 in slot 2. On the other hand, the module with a bus capture function (high-performance module) 201 can recognize the read access from the slot 3 and the write access to the slot 4 by the bus capture unit 42, and takes in the read data from the slot 3 to be a user user. It is possible to execute the program and output the calculation result to slot 4.

FIG. 8 shows a time chart at the time of write access on the CPU module 1 side to the slot 4.

At the time of write access, the address flows to the IO bus 3 in the address / data signal 21 at the timing when the slot n selection signal 22 for selecting the IO slot n changes from the high level to the low level. At the timing when the light strobe signal 24 changes from the high level to the low level, the data of the result calculated by the module 201 with the bus capture function flows as write data to the output module of the IO slot n via the IO bus 3. ..

Since the slot 4 is not subject to calculation by the user program on the CPU module 1 side, only the address is output and the data is in the high impedance (Hi-Z) state. Now, at this timing, the module 201 with the bus capture function can output the calculation result to the slot 4.

The timing of IO refresh is triggered by the CPU module 1 which is the bus master, and the module 201 with the bus capture function which is the bus slave follows the timing.

According to the second embodiment, the module 201 with the bus capture function shares the control using the input / output data of a part of the IO modules 2 with the CPU module 1 in synchronization with the IO refresh of the CPU module 1 for calculation. It is also possible to distribute the load.
Therefore, it is possible to easily perform load balancing while synchronizing with the CPU module.

1 ... CPU module, 2 ... IO module, 3 ... IO bus, 16 ... BUS controller M, 17 ... BUS controller S, 41 ... Data transfer target slot table, 42 ... Bus capture unit, 201 ... Module with bus capture function

Claims (4)

CPU module and
A bus capture unit that includes one or more IO modules and an IO bus that connects the CPU module and the IO module, and the first IO module among the IO modules captures data of the IO module flowing through the IO bus. When,
The first IO module has a data transfer target slot table indicating slots that can be read or written.
The bus capture unit
The slot address included in the address / data signal address on the IO bus is decoded, it is determined that the access is to a second IO module different from its own slot, and the second of the data transfer target slot table. slot essential der the IO module is, to indicate a slot that can read or write the programmable controller, characterized in that capturing the read data. In the programmable controller according to claim 1,
The first IO module is
Has a bidirectional buffer,
The bus capture unit
Ri slot main der of the second IO module of the data exchange target slot table, to indicate a slot that can read or write, the two-way so that it can exchange data of the second IO module in slot A programmable controller characterized by outputting an enable signal to a buffer. In the programmable controller according to claim 1,
The first IO module is
Recognizing read access to a third slot different from the slot calculated by the CPU module, reading read data from the third slot, and writing to a fourth slot different from the slot calculated by the CPU module. A programmable controller characterized in that it recognizes an access and outputs a calculation result to the fourth slot. In the programmable controller according to claim 3,
The first IO module is
A programmable controller characterized in that an operation result is output to the fourth slot when the data is in a high impedance state.

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