CN117795494A

CN117795494A - Processor and byte order conversion method

Info

Publication number: CN117795494A
Application number: CN202280053523.5A
Authority: CN
Inventors: 岛村光太郎; 酒田辉昭; 田中勇气
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 2021-09-21
Filing date: 2022-07-06
Publication date: 2024-03-29
Also published as: JP2023044909A; WO2023047762A1; GB202401725D0

Abstract

The following means are provided: in a processor provided with a CPU, a plurality of peripheral circuits, and a byte order conversion circuit provided between the CPU and the plurality of peripheral circuits, when the peripheral circuits interpret a written value as a multi-byte value, the peripheral circuits are prevented from being interpreted as a value different from a value intended by a creator of software, and creation of the software is made easier. The byte order conversion circuit has a table indicating a relationship between an address and a connection destination type, and controls the data conversion circuit and the byte enable conversion circuit in the byte order conversion circuit, respectively, by using type information extracted from the table using the address of the access destination.

Description

Processor and byte order conversion method

Technical Field

The present disclosure relates to a processor having a endian conversion circuit provided between a CPU and a peripheral circuit, and a endian conversion method.

Background

As background art in the art, JP h 8-202646 a (patent document 1) exists. This publication describes a byte order conversion circuit (converter) for facilitating connection between a CPU (main processor) and a peripheral circuit (I/O device) when the byte order is different.

Prior Art

Literature patent literature

Patent document 1: JP Japanese patent laid-open No. 8-202646

Disclosure of Invention

The byte order conversion circuit of patent document 1 performs ordering of data when the byte order is different between the CPU and the peripheral circuit. For example, in the case where a 4-byte numerical value 00000001 is written in 16 by the slave CPU to the peripheral circuit, it is converted into 01000000. This corresponds to the fact that the allocation method of addresses with respect to a value of 4 bytes is different in the small-end endian from the large-end endian. Specifically, addresses are allocated in order from low-order bytes to high-order bytes in the small-order endian, while addresses are allocated in order from high-order bytes to low-order bytes in the large-order endian. Therefore, in order to store the same data at the same address when the data is interpreted in 1 byte unit, it is necessary to replace the arrangement order of the data. However, in the case of explanation as a 4-byte value, a different value is written. If the peripheral circuit interprets the written value as a 4-byte value, it is interpreted as a value different from the value intended by the creator of the software. This is not limited to the case of 4 bytes, but in the case where the written value is interpreted in units generally larger than 1 byte, it is interpreted as a value different from the value intended by the creator of the software.

An object of the present disclosure is to provide, in a processor having a CPU and a plurality of peripheral circuits, and a byte order conversion circuit provided between the CPU and the plurality of peripheral circuits, the following means: in the case where the written value is interpreted as a multi-byte value, the peripheral circuit prevents the written value from being interpreted as a value different from a value intended by a creator of the software, making creation of the software easier.

Other objects and novel features will become apparent from the description and drawings of this specification.

A representative summary of the present disclosure is described below.

In order to solve the above-described problem, a processor according to an embodiment includes a table in which a byte order conversion circuit indicates a relationship between an address and a connection destination type, and controls a data conversion circuit and a byte enable conversion circuit in the byte order conversion circuit by using type information extracted from the table by using an address of an access destination.

Effects of the invention

According to the processor of the above embodiment, in the case where the CPU is different from the peripheral circuit in terms of the byte order, the byte enable conversion circuit converts the byte enable according to the difference in the allocation method of the addresses to the data of the plurality of bytes, and the peripheral circuit converts the data by the data conversion circuit taking into consideration how many byte unit interpretation values, whereby the peripheral circuit can accurately interpret the value intended by the creator of the software.

The problems, configurations, and effects other than those described above will be apparent from the following description of the embodiments.

Drawings

Fig. 1 is a first example of a configuration diagram of a processor to which the present invention is applied.

Fig. 2 is an example of a timing diagram for bus 111 and bus 114 of fig. 1.

Fig. 3A is an example of byte-enabled actions of the little-endian of bus 111, and bus 114 of fig. 1.

FIG. 3B is an example of byte-enabled actions of the bus 111, and the big-end endian of the bus 114 of FIG. 1.

Fig. 4A is a diagram showing a first example of the attribute information table of the control circuit 102 of fig. 1.

Fig. 4B is a diagram showing a first example of the control signal generation rule of the control circuit 102 of fig. 1.

Fig. 5 is a first example of the control circuit 102 of fig. 1.

Fig. 6 is an example of byte enable conversion circuit 104 of fig. 1.

Fig. 7 is an example of the operation of byte enable conversion circuit 104 of fig. 1.

Fig. 8 is an example of the data conversion circuit 103 of fig. 1.

Fig. 9 is an example of the operation of the data conversion circuit 103 of fig. 1.

Fig. 10 shows a first example of the operation of the bus 111 and the bus 114 in fig. 1.

Fig. 11A is a diagram showing a second example of the attribute information table of the control circuit 102 of fig. 1.

Fig. 11B is a diagram showing a second example of the control signal generation rule of the control circuit 102 of fig. 1.

Fig. 12 is a second example of the operation of the bus 111 and the bus 114 in fig. 1.

Fig. 13 is a second example of the control circuit 102 of fig. 1.

Fig. 14 is a second example of a configuration diagram of a processor to which the present invention is applied.

Fig. 15A is a diagram showing an attribute information table of the control circuit 1402 of fig. 14.

Fig. 15B is a diagram showing a control signal generation rule of the control circuit 1402 of fig. 14.

Fig. 16 is a third example of a configuration diagram of a processor to which the present invention is applied.

Fig. 17 is an example of the delay circuit 1601 of fig. 16.

Fig. 18 is an example of a timing chart of the bus 111 and the bus 114 of fig. 16.

Detailed Description

Hereinafter, embodiments and examples will be described with reference to the drawings. In the following description, the same reference numerals are given to the same components, and the repetitive description thereof may be omitted. In order to make the description clearer, the drawings are schematically shown in comparison with the actual embodiments, but the present invention is not limited to the explanation by way of example.

The processor of the embodiment adopts the following configuration.

Specifically, the processor (100) is provided with a CPU (101), a plurality of peripheral circuits (105-108), and a byte order conversion circuit (109) provided between the CPU (101) and the plurality of peripheral circuits (105-108). The byte order conversion circuit (109) further includes a table (AIT) that stores class information (byte order attribute, type attribute) indicating the relationship between the address and the class of the connection destination, a byte enable conversion circuit (104), and a data conversion circuit (103). A byte order conversion circuit (109) controls a byte enable conversion circuit (104) and a data conversion circuit (103) respectively, by using class information (byte order attribute, type attribute) fetched from a table (AIT) using an output address of an access destination outputted from a CPU (101).

The byte order conversion method of the embodiment adopts the following configuration.

A processor (100) is provided with a CPU (101), a plurality of peripheral circuits (105-108), and a byte order conversion circuit (109) provided between the CPU (101) and the plurality of peripheral circuits (105-108), the byte order conversion circuit (109) being provided with a table (AIT) for storing class information (byte order attribute, type attribute) indicating the relation between the address and the class of the connection destination, a byte enable conversion circuit (104), and a data conversion circuit (103), and the byte order conversion method of the processor (100) comprises:

a) A step of extracting category information (byte order attribute, type attribute) from a table (AIT) using an output address of an access destination outputted from a CPU (101); and

b) And a step of controlling the byte enable conversion circuit (104) and the data conversion circuit (103) based on the extracted class information (byte order attribute, type attribute).

According to the processor and the byte order conversion method of the above-described embodiment, when the CPU and the peripheral circuit differ in byte order, the byte enable conversion circuit converts byte enable according to the difference in allocation method of addresses to the data of a plurality of bytes, and the peripheral circuit converts the data by the data conversion circuit taking into consideration how many byte unit interpretation values, whereby the peripheral circuit can accurately interpret a value intended by the creator of the software.

Hereinafter, embodiments will be described in detail with reference to the drawings.

Example 1

The processor 100 of the present embodiment has a CPU101, a byte order conversion circuit 109, a first peripheral circuit (ROM) 105, a second peripheral circuit (RAM) 106, a third peripheral circuit (first IO circuit) 107, a fourth peripheral circuit (second IO circuit) 108, a 1 st bus (hereinafter referred to as bus) 111, and a 2 nd bus (hereinafter referred to as bus) 114. The CPU101 is connected to a bus 111, and a first peripheral circuit (ROM) 105, a second peripheral circuit (RAM) 106, a third peripheral circuit (first IO circuit) 107, and a fourth peripheral circuit (second IO circuit) 108 are connected to a bus 114. The byte order conversion circuit 109 is connected between the bus 111 and the bus 114. The ROM is a nonvolatile memory such as a read only memory, and the RAM is a volatile memory such as a random access memory.

The byte order conversion circuit 109 has a control circuit 102, a data conversion circuit 103, and a byte enable conversion circuit 104.

The CPU101 executes the following processing in accordance with a program stored in the first peripheral circuit (ROM) 105. The CPU101 first acquires input information from the third peripheral circuit (first IO circuit: IO 1) 107 and the fourth peripheral circuit (second IO circuit: IO 2) 108 via the buses 114 and 111, performs predetermined processing, and then writes output information to the third peripheral circuit (first IO circuit) 107 and the fourth peripheral circuit (second IO circuit) 108 via the buses 111 and 114. The second peripheral circuit (RAM) 106 is used for saving progress in the process.

When receiving a reception request of input information from the CPU101 via the buses 111, 114, the third peripheral circuit (first IO circuit) 107 outputs the input information received from the signal line 115 to the CPU101 via the buses 114, 111. When the third peripheral circuit (first IO circuit) 107 also receives a write request for output information from the CPU101 via the buses 111 and 114, the write value is held inside and output to the signal line 115.

The operation of the fourth peripheral circuit (second IO circuit) 108 is also the same as that of the third peripheral circuit (first IO circuit) 107.

The control circuit 102 receives information of an access address and an access size from the CPU101 via the bus 111, generates control signals of the byte enable converting circuit 104 and the data converting circuit 103, and outputs the control signals to the signal lines 112, 113.

The byte enable conversion circuit 104 converts the byte enable of the bus 111 into a predetermined value based on the control signal (1 st signal) received from the signal line 112, and outputs the converted value to the bus 114.

The data conversion circuit 103 converts the write data of the bus 111 into predetermined data based on the control signal (the 2 nd signal) received from the signal line 113, and outputs the data to the bus 114. The data conversion circuit 103 also converts the read data of the bus 114 into predetermined data based on the control signal received from the signal line 113, and outputs the data to the bus 111.

Fig. 2 is an example of a timing diagram for bus 111 and bus 114 of fig. 1. Since the operation of the bus 111 and the operation of the bus 114 are the same, the description of the two are not separately provided.

clk is clock signal (1 bit), req is request signal (1 bit), wr is write signal (1 bit), size [2:0] is a size signal (size information) (3 bits), be [3:0] is a byte enable signal (4 bits), adr [31:2] is an address signal (30 bits), wd [31:0] is write data (32 bits), rdv is read data valid signal (1 bit), rd [31:0 is read data (32 bits). size [2:0 represents a signal of 3 bits, i.e., size [2], size [1], size [0], where size [2] is the most significant bit and size [0] is the least significant bit. Likewise, be [3:0 is composed of 4-bit signals of be [3] to be [0], adr [31 ]: 2 is composed of signals of 30 bits of adr [31] to adr [2], wd [31 ]: 0 consists of 32-bit signals wd [31] to wd [0], rd [31: the 0 is composed of 32-bit signals of rd 31-rd 0, and the larger the value in [ ] is, the higher the value is. req, wr, size [2:0], be [3:0], adr [31:2], wd [31:0 is a signal in a direction from the CPU101 toward the peripheral circuits 105 to 108, rdv, rd [31:0 is a signal in a direction from the peripheral circuits 105 to 108 toward the CPU 101. The address space is 32 bits, but the write data and the read data are 4 bytes, so the lowest 2 bits of the address are not transferred, and instead, it is indicated with byte enables which byte of the 4 bytes of data is valid. The byte-enabled actions are described later. The size signal indicates transmission (data transmission size) of 1 byte, 2 bytes, or 4 bytes, respectively, with one of three types of 2-bit numbers of 001, 010, and 100.

Bus 111 and bus 114 can each be considered as including, for example, a bus comprising a bus for transmitting wd [31:0] and rd [31: a data bus including 32 data signal lines for transmitting data such as 0], and includes a data bus for transmitting adr [31: an address bus including 30 address signal lines for address signals of 2], and a control bus including 9 control signal lines for transmitting a request signal (req: 1 bit), a write signal (wr: 1 bit), a size signal (size [2:0]:3 bits), and a byte enable signal (be [3:0]:4 bits).

Cycle 1 (cycle=1) is the transfer of the written data. Req and wr are 1 at write, going to size [2:0], be [3:0], adr [31:2], wd [31:0] outputs valid values (sz 1, be1, a1, d 1), respectively.

Cycles 3-6 are read data transfers. Req becomes 1 and wr becomes 0 at the time of reading. In the first cycle (3 rd cycle), the sequence goes to size [2:0], be [3:0], adr [31:2] outputs valid values (sz 2, be2, a 2). The number of cycles read is not fixed and the cycle transfer with rdv being 1 ends. For rd [31 ] in the period when rdv becomes 1:0] outputs a valid value (d 2). In addition, in fig. 1 and 2, rdv, rd [31 ] are omitted: the value of 0 is output from each of the peripheral circuits 105 to 108. With respect to rdv, OR (OR operations) of the outputs of the four peripheral circuits are performed on bus 114. Fig. 2 shows the state after OR. In addition, regarding rd [31:0], selects the output value of the peripheral circuit that outputs a1 to rdv on bus 114. The selected state is illustrated in fig. 2. In the absence of peripheral circuitry for rdv output 1, rd [31 ] is ignored: 0.

Fig. 3A and 3B are examples of byte-enabled operations of the bus 111 and the bus 114 of fig. 1. Fig. 3A is an example of byte-enabled actions of bus 111, and Little Endian (Little Endian) of bus 114 of fig. 1. FIG. 3B is an example of byte-enabled actions of bus 111, and Big Endian (Big Endian) of bus 114 of FIG. 1. Small Endian (Little Endian) and Big Endian (Big Endian) are described separately. The small end endian can be referred to as the 1 st endian, and the large end endian can be referred to as the 2 nd endian that is different from the 1 st endian.

As described above, there are three cases where the size of the data to be transferred is 1 byte, 2 bytes, or 4 bytes.

In the case of transfer of 1 byte (8 bits) (size signal: case of size [2:0] 001), there are four cases depending on which byte of data of 4 bytes is output to (fig. 3a: be [3:0]:0001, 0010, 0100, 1000; fig. 3b: be [3:0]:1000, 0100, 0010, 0001) (that is, in the case where the bus 111 and the bus 114 include 32 data lines DL31-DL0 as data buses, respectively, there are four cases depending on which data line group of 1 byte is output to the data line groups DL31-DL24, DL23-DL16, DL15-DL8, DL7-DL 0). The byte address of the lower order byte of the little-endian is small, and the byte address of the upper order byte is large. On the other hand, the byte of the lower order of the big-end byte order has a large address, and the byte of the upper order has a small address.

The transfer of 2 bytes (16 bits) (size signal: case of size [2:0] 010) is only allowed if the address is a multiple of 2. Thus, there are two cases (FIG. 3A: be [3:0]:0011, 1100, FIG. 3B:1100, 0011) depending on which of the upper 2 bytes and the lower 2 bytes of the 4 bytes of data has data (that is, there are two cases depending on which of the data line groups DL31-DL16, DL15-DL0 the 2 bytes of data is output to in the case where the bus 111 and the bus 114 each contain 32 data lines DL31-DL0 as data buses). The 2-byte transfer at address 4n corresponds to superimposing the 1-byte transfers of addresses 4n and 4n+1, and the 2-byte transfer at address 4n+2 corresponds to superimposing the 1-byte transfers of addresses 4n+2 and 4n+3.

For a 4 byte (32 bit) transfer (size signal: size [2:0] is 100), all data of 4 bytes is valid, so the byte-enabled full bit is 1 (be [3:0]: 1111), and the byte-enabled values are the same in both the small-end and large-end endian.

Fig. 4A and 4B are a first example of the operation of the control circuit 102 in fig. 1. Fig. 4A is a diagram showing a first example of the attribute information table AIT of the control circuit 102 of fig. 1. Fig. 4B is a diagram showing a first example of the control signal generation rule CSGR of the control circuit 102 in fig. 1.

The operation of the control circuit 102 is described using the attribute information table AIT and the control signal generation rule CSGR. The attribute information table AIT stores address ranges and attribute information of the respective peripheral circuits.

The attribute information table AIT receives as input the address of the bus 111 (0 in which 2 bits are connected to the lower bits of adr [31:2 ]), and outputs the attribute information of the corresponding peripheral circuit. The attribute information can also be referred to as category information of the peripheral circuit. The attribute information exists in both a Endian (Endian) and a type. 0 of the endian is a little-endian and 1 is a big-endian. Type 0 (type 1) represents a set of data that is interpreted as 1 byte independent of the value of the size signal (size [2:0 ]) of bus 111. Data representing 2 bytes or more when the type is 1 (type 2) is interpreted as data of a size represented by the value of the size signal (size [2:0 ]) of the bus 111.

The control signal generation rule CSGR indicates a rule for generating and outputting values to the signal lines 112 and 113, with the byte order, type, and size signal (size [2:0 ]) outputted from the attribute information table AIT as inputs. This table is not explicitly described, but is premised on the fact that the CPU endian is a small-end endian.

The (value of the control signal of) signal line 112 becomes 0 (first value) when the endian attribute is 0, and becomes 1 (second value) when it is 1. This means that byte-enabled conversion is not performed when the CPU and the peripheral circuit are identical in their byte order, and byte-enabled conversion is performed when the CPU and the peripheral circuit are different in their byte order.

The signal line 113 takes three values (the value of the control signal), 00 (first value) indicates no conversion of data, 01 (second value) indicates conversion of data in units of 1 byte, and 10 (third value) indicates conversion of data in units of 2 bytes. The details of the conversion contents are made later. The signal line 113 becomes 00 when the endian attribute is 0. This means that the conversion of data is not performed when the CPU is the same as the byte order of the peripheral circuit. The signal line 113 also always becomes 01 (conversion in 1 byte) when the endian attribute is 1 and the type attribute is 0. On the other hand, when the endian attribute is 1 and the type attribute is 1, the output value is different depending on the value of the size signal (size [2:0 ]) of the bus 111. At size [2:0] is 001 (1 byte), the output value is 01 (conversion in 1 byte), the output value is 10 (conversion in 2 bytes) when the size [2 0] is 010 (2 bytes), and the size [2:0] is 100 (4 bytes), and the output value is 00 (no conversion).

Fig. 5 is a first example of the control circuit 102 of fig. 1.

The control circuit 102 of the present embodiment has fixed value output circuits 501, 502, 505, 506, 507, comparison circuits 503, 504, AND (AND operation) circuits 508, 509, 510, 513, 514, OR (OR operation) circuits 511, 512.

The fixed value output circuit 501 outputs a fixed value F0000000 of 16 to the signal line 521.

The fixed value output circuit 502 outputs a fixed value F8000000 of 16 to the signal line 522.

The comparator circuit 503 compares the address of the bus 111 (0 in which 2 bits are connected to the lower bits of adr [31:2 ]) with the value of the signal line 521, and outputs the result to the signal line 523. The output value is 0 when the address is smaller than the fixed value F0000000 in the 16-ary system, and is 1 when the address is equal to or greater than the fixed value F0000000.

The comparator circuit 504 compares the address of the bus 111 (0 in which 2 bits are connected to the lower bits of adr [31:2 ]) with the value of the signal line 522, and outputs the result to the signal line 524. The output value is 0 when the address is smaller than the fixed value F8000000 of 16, and is 1 when the address is equal to or greater than the fixed value F8000000.

The fixed value output circuit 505 outputs a fixed value 10 of 2 to the signal line 525.

The fixed value output circuit 506 outputs a fixed value 11 of 2 to the signal line 526.

The fixed value output circuit 507 outputs a fixed value 01 of 2 to the signal line 527.

The AND circuit 508 outputs the value of the signal line 525 to the signal line 528 when the value of the signal line 523 is 0. This corresponds to line 1 of the attribute information table AIT of fig. 4A. The AND circuit 508 also outputs 00 to the signal line 528 when the value of the signal line 523 is 1. In this case, the value of the signal line 528 does not affect the output of the OR circuit 511.

The AND circuit 509 outputs the value of the signal line 526 to the signal line 529 when the value of the signal line 523 is 1 AND the value of the signal line 524 is 0. This corresponds to line 2 of the attribute information table AIT of fig. 4A. The AND circuit 509 also outputs 00 to the signal line 529 when the value of the signal line 523 is 0 or the value of the signal line 524 is 1. In this case, the value of the signal line 529 does not affect the output of the OR circuit 511.

The AND circuit 510 outputs the value of the signal line 527 to the signal line 530 when the value of the signal line 524 is 1. This corresponds to line 3 of the attribute information table AIT of fig. 4A. The AND circuit 510 also outputs 00 to the signal line 530 when the value of the signal line 524 is 0. In this case, the value of the signal line 530 does not affect the output of the OR circuit 511.

The OR circuit 511 performs OR (OR operation) of three values of the signal lines 528, 529, 530 and outputs the result to the signal line 531. Since two of the three values of the signal lines 528, 529 and 530 are 00, the operation of the OR circuit 511 substantially selects one of the three values of the signal lines 528, 529 and 530. The value output to the signal line 531 corresponds to the output of the attribute information table AIT of fig. 4A.

The signal line 112 is directly output with the value of the endian attribute of the signal line 531.

The OR circuit 512 outputs 1 to the signal line 532 when the type attribute of the signal line 531 is 0 OR when bit 0 of the size signal (size [2:0 ]) of the bus 111 is 1 (corresponding to 1 byte), and otherwise outputs 0.

The AND circuit 513 outputs 1 to bit 0 of the signal line 113 when both the byte order property of the signal line 531 AND the value of the signal line 532 are 1. This operation corresponds to the case where 01 is output to the signal line 113 in the 2 nd and 3 rd rows of the control signal generation rule CSGR in fig. 4B. The AND circuit 513 also outputs 0 when the value of the endian attribute of the signal line 531 or the signal line 532 is 0.

The AND circuit 514 outputs 1 to bit 1 of the signal line 113 when both the byte order attribute AND the type attribute of the signal line 531 are 1 AND bit 1 of the size signal (size [2:0 ]) of the bus 111 is 1 (equivalent to 2 bytes). This operation corresponds to the case where 10 is output to the 4 th line signal line 113 of the control signal generation rule CSGR in fig. 4B. The AND circuit 514 also outputs 0 to bit 1 of the signal line 113 when bit 1 of the byte order attribute, the type attribute, or the size signal (size [2:0 ]) of the signal line 531 is 0.

Fig. 6 is an example of byte enable conversion circuit 104 of fig. 1.

The byte enable conversion circuit 104 is constituted by selection circuits 601, 602, 603, 604.

The selection circuit 601 selects bit 3 (be [3 ]) of the byte enable signal of the bus 111 when the value of the signal line 112 is 0, and outputs to bit 3 (be [3 ]) of the byte enable signal of the bus 114. The selection circuit 601 also selects bit 0 (be [0 ]) of the byte enable signal of the bus 111 when the value of the signal line 112 is 1, and outputs to bit 3 (be [3 ]) of the byte enable signal of the bus 114 as the byte enable signal after byte order conversion.

Similarly, the selection circuits 602, 603, and 604 operate to select the left input when the value of the signal line 112 is 0, and select the right input when the value of the signal line 112 is 1, and output the selected input as a byte enable signal after byte order conversion.

When the signal line 112 is 0, the byte enable conversion circuit 104 outputs the same value as the input.

When the signal line 112 is 1, the byte enable converting circuit 104 outputs the high order and the low order of the input by switching them to the reverse order.

Fig. 8 is an example of the data conversion circuit 103 of fig. 1. The data conversion is performed with respect to the write data (wd [31:0 ]) and the read data (rd [31:0 ]), but only the conversion circuit of the write data is shown in FIG. 8. The conversion circuit for reading data is also of the same configuration.

The data conversion circuit 103 is constituted by selection circuits 801, 802, 803, 804.

When the value of the signal line 113 is 00, the selection circuit 801 selects bits 31 to 24 (wd [31:24 ]) of the write data of the bus 111 and outputs the selected bits 31 to 24 (wd [31:24 ]) of the write data to the bus 114 without performing byte order conversion. The selection circuit 801 also selects bits 7 to 0 (wd [7:0 ]) of the write data of the bus 111 when the value of the signal line 113 is 01, and outputs the selected bits to bits 31 to 24 (wd [31:24 ]) of the data of the bus 114 as byte order converted data. The selection circuit 801 also selects bits 15 to 8 (wd [15:8 ]) of the write data of the bus 111 when the value of the signal line 113 is 10, and outputs the selected bits 31 to 24 (wd [31:24 ]) of the write data of the bus 114 as byte order converted data.

Similarly, the selection circuits 802, 803, 804 operate to select the left input when the value of the signal line 113 is 00, select the center input when the value of the signal line 113 is 01, and select the right input when the value of the signal line 113 is 10, and output the signals.

When the signal line 113 is 00, the data conversion circuit 103 outputs the same value as the input.

When the signal line 113 is 01, the data conversion circuit 103 outputs the high order and the low order inputted in units of bytes (8 bits) by changing them to the reverse order.

When the signal line 113 is 10, the data conversion circuit 103 outputs the high order 16 bits (bits 31 to 16) and the low order 16 bits (bits 15 to 0) by replacing them.

Fig. 10 shows a first example of the operation of the bus 111 and the bus 114 in fig. 1. In fig. 10, the operation of reading data is not described, but the operation of reading data is the same as the operation of writing data.

The first peripheral circuit (ROM) 105 and the second peripheral circuit (RAM) 106 interpret the write data in units of 1 byte irrespective of the access size. Therefore, byte order conversion is performed in such a manner that data of the same address becomes the same in byte units. For example, when the access size is 4 bytes, the lowest byte(s) of the bus 111 is output to the highest byte of the bus 114. This is because the lowest byte corresponds to address 4n on bus 111, whereas the highest byte corresponds to address 4n on bus 114.

The third peripheral circuit (first IO circuit) 107 interprets the data in units of the same size as the access size. Therefore, the byte order conversion is performed in such a manner that the arrangement order of the data is saved by the unit of the access size. For example, in the case of accessing a data sequence (rs) having a size of 2 bytes and an address of 4n, the data is shifted from the lower order to the higher order.

Thereby, the CPU101 is guaranteed to interpret the data as the same as the third peripheral circuit (first IO circuit) 107.

The byte order of the fourth peripheral circuit (second IO circuit) 108 is the same as that of the CPU101, and therefore, byte order conversion is not performed.

Example 2

Fig. 11A and 11B are second examples of the operation of the control circuit 102 in fig. 1.

Fig. 11A is a diagram showing a second example of the attribute information table of the control circuit 102 of fig. 1. Fig. 11B is a diagram showing a second example of the control signal generation rule of the control circuit 102 of fig. 1.

The operation of the control circuit 102 in fig. 4A and 4B differs from that in fig. 11A and 11B in that the output of the register size is added to the attribute information table AIT in fig. 11A, and the output of the control signal generation rule CSGR in fig. 11B differs depending on the value of the register size attribute. The register size attribute indicates the size of a unit in which the peripheral circuit of the access destination interprets the write value. As described in the description of fig. 10, in the case of the operation of the control circuit 102 in fig. 4A and 4B, when the third peripheral circuit (first IO circuit) 107 is accessed, data is interpreted in units of the same size as the access size. In the case of such an operation, there is a problem that, for example, when the third peripheral circuit (first IO circuit) 107 accesses 2 bytes or 4 bytes to an address where data is interpreted in 1 byte units, it is different from the interpretation of the CPU 101. To cope with such a problem, in the operation of the control circuit 102 in fig. 11A and 11B, the output of the signal line 113 is determined based on the register size attribute (how many bytes of data are interpreted) of the third peripheral circuit (first IO circuit) 107.

In the attribute information table AIT of fig. 11A, the area of the third peripheral circuit (first IO circuit) 107 is divided into three, 1 byte is output to the register size attribute at addresses F0000000 to F1FFFFFF, 2 bytes are output to the register size attribute at addresses F2000000 to F3FFFFFF, and 4 bytes are output to the register size attribute at addresses F40 00000 to F7 FFFFFF. The values of the register size attribute are ignored by the control signal generation rule of fig. 11B in the first peripheral circuit (ROM) 105, the second peripheral circuit (RAM) 106, and the fourth peripheral circuit (second IO circuit) 107, and therefore, the output value of the register size attribute may be any one of 1 byte, 2 bytes, and 4 bytes.

In the control signal generation rule CSGR in fig. 11B, the operation when accessing the third peripheral circuit (first IO circuit) 107 is different from that in fig. 4B. When the register size attribute is 1 byte, the output to the signal line 113 becomes 01 regardless of the value of the size signal (size [2:0 ]) of the bus 111. This is found in size [2:0] is 001 (1 byte) as in fig. 4B, but size [2: the operation at 0] 010 (2 bytes) and 100 (4 bytes) is different from that of fig. 4B. In the case of a register size attribute of 2 bytes, size [2: the operations at 0] of 001 (1 byte) and 010 (2 bytes) are the same as in fig. 4B, but size [2: the operation when 0 is 100 (4 bytes) is different from fig. 4B, and the output to the signal line 113 is 10. The operation when the register size attribute is 4 bytes is the same as fig. 4B.

Fig. 12 is a second example of the operation of the bus 111 and the bus 114 in fig. 1. Fig. 12 corresponds to a second example of the operation of the control circuit 102 in fig. 11A and 11B. Operations at the time of accessing the first peripheral circuit (ROM) 105, the second peripheral circuit (RAM) 106, and the fourth peripheral circuit (second IO circuit) 108 are the same as those of fig. 10, and therefore, only operations at the time of accessing the third peripheral circuit (first IO circuit) 107 are described. In fig. 12, size=1 indicates that the register size attribute is 1 byte, size=2 indicates that the register size attribute is 2 bytes, and size=4 indicates that the register size attribute is 4 bytes.

When the register size attribute is 1 byte, actions are different from those of fig. 10 when the access size is 2 bytes and 4 bytes. The same data is output to the same byte of the address in units of bytes. For example, in the case of an access size of 4 bytes, the lowest order byte(s) of the bus 111 is output to the highest order byte of the bus 114. This is because the lowest byte on the bus 111 corresponds to the address 4n, while the highest byte on the bus 114 corresponds to the address 4 n. When the register size attribute is 1 byte, the third peripheral circuit (first IO circuit) 107 interprets the data in units of 1 byte, and therefore, according to this operation, it is ensured that the CPU101 and the third peripheral circuit (first IO circuit) 107 interpret the data identically.

When the register size attribute is 2 bytes, the operation differs from fig. 10 when the access size is 4 bytes. The lower 2 bytes (rs) of the bus 111 hold the arrangement of data sequentially output to the upper 2 bytes of the bus 114. The lower 2 bytes of the bus 111 correspond to the addresses 4n and 4n+1, and thus, data is shifted to the area of the same address of the bus 114, but the arrangement order of the data is preserved, and thus, the CPU101 and the third peripheral circuit (first IO circuit) 107 are guaranteed to interpret the data identically. Similarly, the upper 2 bytes (p q) of the bus 111 are output to the lower 2 bytes of the bus 114 in a state where the arrangement order of the data is maintained.

Example 3

Fig. 13 is a second example of the control circuit 102 of fig. 1.

The control circuit 102 of fig. 5 is different from the control circuit 102A of fig. 13 in that the fixed value output circuits 501, 502, 505, 506, 507 of fig. 5 are replaced with memory circuits 1301, 1302, 1305, 1306, 1307, and the values can be rewritten from the bus 111.

When the request signal (req) of the bus 111 is 1, the write signal (wr) is 1, the size signal (size [2:0 ]) is 100 (4 bytes), and the address signal (adr [31:2 ]) is a predetermined value, the write control circuit 1311 outputs the write control signal of the memory circuit 1301, 1302, 1305, 1306, 1307 to one of the signal lines 1321, 1322, 1325, 1326, 1327. The write control signal is composed of write enable and write data, and as the write data, a part of the write data (wd [31:0 ]) of the bus 111 is selected and outputted.

By configuring the control circuit 102A of fig. 13, the CPU101 can set the content (stored value) of the attribute information table AIT of fig. 4A. That is, the method has a function of rewriting the saved value of the table AIT according to the request of the CPU101 or a step of rewriting the saved value of the table AIT according to the request from the CPU 101. Thus, even when the configuration of the peripheral circuit is changed, the same control circuit 102A can be used.

Example 4

The processor 100 of fig. 1 is different from the processor 1400 of fig. 14 in that the CPU1401 supports operations of both the small-end and large-end endian, and outputs information of which endian is currently being operated to the control circuit 1402 via the signal line 1411. That is, the CPU1401 has a function of changing the endian to the small-end endian or the large-end endian. The endian conversion circuit 1409 changes the rule of endian conversion according to information on the endian of the CPU1401 received from the signal line 1411. The processor 1400 includes: a step of changing the byte order of the CPU 1401; a step of transferring information on the byte order of the CPU1401 to a signal line 1411 between the CPU1401 and the byte order conversion circuit 1409; and a step of changing the rule of the endian conversion by the endian conversion circuit 1409 based on the information on the endian of the CPU1401 received from the signal line 1411.

The control circuit 1402 generates signals to be output to the signal lines 112 and 113 by adding information on the byte order of the CPU1401 received from the signal line 1411 to the built-in table AIT. Details are described later.

Fig. 15A and 15B are examples of operations of the control circuit 1402 of fig. 14. Fig. 15A is a diagram showing an attribute information table AIT of the control circuit 1402 of fig. 14. Fig. 15B is a diagram showing a control signal generation rule CSG R of the control circuit 1402 of fig. 14.

The attribute information table AIT of fig. 15A is the same as the attribute information table AIT of fig. 4A.

On the other hand, the control signal generation rule CSRG of fig. 15B is different from the control signal generation rule CSRG of fig. 4B in that the value of the signal line 1411 is taken into consideration. The operation when the value of the signal line 1411 is 0 is the same as that of fig. 4B. When the value of the signal line 1411 is 1 and the endian attribute is 0, the CPU1401 is different from the endian of the peripheral circuit, and therefore, byte-enabled endian conversion is required, and the signal line 112 becomes 1. On the other hand, the signal line 113 has a value of 01 when the type attribute is 0, and has a value of 01, 10, 00, or 00 according to the size signal (size [2:0 ]) of the bus 111 when the type attribute is 1. Note that, in the attribute information table AIT of fig. 15A, there is no case where the endian attribute is 0 and the type attribute is 0, and therefore, this case is not described in fig. 15B. When the value of the signal line 1411 is 1 and the endian attribute is also 1, the CPU1401 is identical to the endian of the peripheral circuit, and therefore, no endian conversion is necessary, and outputs 0 to the signal lines 112 and 113.

Example 5

The processor 100 of fig. 1 differs from the processor 1600 of fig. 16 in that the byte order conversion circuit 1609 has a delay circuit 1601. In the processor 100 of fig. 1, the processing of the control circuit 102, the data conversion circuit 103, and the byte enable conversion circuit 104 takes time, and therefore, the transfer time from the CPU101 to the peripheral circuits (105, 106, 107, 108) becomes long, which may cause a drop in the operation frequency. This embodiment corresponds to this problem, and therefore, the delay circuit 1601 divides the transfer from the CPU101 to the peripheral circuits (105, 106, 107, 108) into 2 clock cycles, and shortens the transfer time per 1 clock cycle, thereby preventing the drop in the operation frequency. Further, since transfer of read data from the peripheral circuits (105, 106, 107, 108) to the CPU101 is delayed by 1 clock cycle or more from the start of transfer, the operation of the control circuit 102 is completed at this point in time, and the influence of the decrease in the operation frequency of the byte order conversion circuit is slight, and therefore, in the present embodiment, a configuration is adopted in which transfer of read data is not divided into 2 clock cycles. However, since the transfer time becomes longer due to the processing time of the data conversion circuit 103, the transfer of the read data may be divided into clock cycles in order to eliminate the influence.

The delay circuit 1601 directly outputs the byte enable received from the signal line 1611 and the write data received from the signal line 1612 to the bus 114 when the value received from the signal line 112 is 0. The delay circuit 1601 also delays the byte enable received from the signal line 1611 and the write data received from the signal line 1612 by 1 clock period when the value received from the signal line 112 is 1, and outputs the delayed data to the bus 114. The delay circuit 1601 also directly outputs read data received from the bus 114 to the signal line 1612. The delay circuit 1601 also directly outputs a read data valid signal received from the bus 114 to the bus 111. That is, the byte order conversion circuit 1609 has a function and a process of enabling bytes and delaying data by 1 clock cycle using the delay circuit 1601 in the case where byte order conversion is required.

Fig. 17 is an example of the delay circuit 1601 of fig. 16.

The delay circuit 1601 is configured by memory circuits 1701, 1702, 1703, 1705, AND circuits 1704, 1709, 1710, 1711, selection circuits 1706, 1707, 1708, AND an OR circuit 1712.

The memory circuit 1701 delays the byte enable signal received from the signal line 1611 by 1 clock period and outputs it to the signal line 1721.

The memory circuit 1702 delays the write data (wd [31:0 ]) received from the signal lines 1612 by 1 clock cycle and outputs the delayed write data to the signal lines 1722.

The memory circuit 1703 delays the write signal (wr), the size signal (size [2:0 ]), and the address signal (adr [31:2 ]) received from the bus 111 by 1 clock cycle and outputs the delayed write signal to the signal line 1723.

The AND circuit 1704 performs AND (AND operation) of the byte enable conversion valid signal received from the signal line 112 AND the request signal (req) received from the bus 111, AND outputs to the signal line 1724.

The memory circuit 1705 delays the state of the signal line 1724 by 1 clock cycle and outputs the delayed state to the signal line 1725.

The selection circuit 1706 outputs the value of the signal line 1721 as the byte enable signal (be [3:0 ]) of the bus 114 when the value of the signal line 1725 is 1. The selection circuit 1706 also outputs byte enable signals (be [3:0 ]) of the bus 111 as byte enable signals (be [3:0 ]) of the bus 114 when the value of the signal line 1725 is 0.

The selection circuit 1707 outputs the value of the signal line 1722 as the write data (wd [31:0 ]) of the bus 114 when the value of the signal line 1725 is 1. The selection circuit 1707 also outputs the write data (wd [31:0 ]) of the bus 111 as the write data (wd [31:0 ]) of the bus 114 when the value of the signal line 1725 is 0.

The selection circuit 1708 outputs the value of the signal line 1723 as the write signal (wr), the size signal (size [2:0 ]), and the address signal (adr [31:2 ]) of the bus 114 when the value of the signal line 1725 is 1. The selection circuit 1708 also outputs a write signal (wr), a size signal (size [2:0 ]), and an address signal (adr [31:2 ]) of the bus 111 as a write signal (wr), a size signal (size [2:0 ]), and an address signal (adr [31:2 ]) of the bus 114 when the value of the signal line 1725 is 0.

The AND circuit 1709 performs an AND operation of the write signal (wr) of the signal line 1723 AND the value of the signal line 1725, AND outputs the result to the signal line 1729.

The AND circuit 1710 performs an inversion of the value of the signal line 1725 AND an AND (AND operation) of the value of the signal line 1724, AND outputs the result to the signal line 1730. As a result, the signal line 1730 becomes 1 only for 1 cycle when the signal line 1724 rises.

The AND circuit 1711 AND (AND) the inverted value of the signal line 1730 AND the request signal (req) of the bus 111, AND outputs the result to the signal line 1731. As a result, the signal line 1731 delays the rising of the request signal (req) of the bus 111 by 1 cycle only when the signal line 112 is 1.

The OR circuit 1712 performs an OR operation on the value of the signal line 1729 and the value of the signal line 1731, and outputs the result as a request signal (req) of the bus 114.

The data transfer written in the bus 111 is performed in the 1 st cycle (cycle=1). Since the signal line 112 is 1, data written in the 2 nd cycle is transferred in the bus 114 as well.

Data transfer read in the bus 111 is performed in the 3 rd to 7 th cycles. Since the signal line 112 is 1, the start of data transfer for the same read on the bus 114 is delayed until the 4 th cycle, but the end of data transfer is the 7 th cycle similarly to the bus 111. This is because, in the delay circuit 1601 of fig. 17, there is a circuit delayed by 1 cycle with respect to the request signal (req), the write signal (wr), the size signal (size [2:0 ]), the byte enable signal (be [3:0 ]), the address signal (adr [31:2 ]), but there is no circuit delayed by 1 cycle with respect to the read data valid signal (rdv), the read data (rd [31:0 ]).

The invention proposed by the present inventors has been specifically described above based on examples, but the invention is not limited to the above-described embodiments and examples, and various modifications are naturally possible.

Description of the reference numerals

100: processor, 101: CPU, 103: data conversion circuit, 104: byte enable conversion circuit, 105: first peripheral circuit (ROM), 106: second peripheral circuit (RAM), 107: third peripheral circuits (first IO circuits: IO 1), 108: fourth peripheral circuit (second IO circuit: IO 2), 109: endian conversion circuitry, 501, 502, 505, 506, 507: fixed value output circuits (corresponding to tables indicating the relationship between addresses and types of connection destinations), 1301, 1302, 1305, 1306, 1307: storage circuits (corresponding to tables indicating the relationship between addresses and types of connection destinations), 1311: write control circuit, 1400: processor, 1401: CPU, 1409: byte order conversion circuit, 1411: signal line, 1600 for transferring information of the byte order of the CPU: processor, 1601: delay circuit 1609: a byte order conversion circuit.

Claims

1. A processor, comprising:

CPU；

a plurality of peripheral circuits; and

a byte order conversion circuit provided between the CPU and the plurality of peripheral circuits,

The byte order conversion circuit has a table holding category information indicating a relationship between an address and a category of a connection destination, a byte enable conversion circuit, a data conversion circuit,

the byte order conversion circuit controls the byte enable conversion circuit and the data conversion circuit, respectively, using the category information fetched from the table using the output address of the access destination output from the CPU.

2. The processor of claim 1, wherein the processor further comprises a processor controller,

the table also has size information on the size of the connection destination interpretation data,

the byte order conversion circuit controls the byte enable conversion circuit and the data conversion circuit, respectively, using the category information and the size information fetched from the table.

3. The processor of claim 1, wherein the processor further comprises a processor controller,

the byte order conversion circuit has a function of rewriting a saved value of the table in accordance with a request from the CPU.

4. The processor of claim 1, wherein the processor further comprises a processor controller,

the CPU has the function of altering the endian,

the processor has a signal line between the CPU and the endian conversion circuit that passes information about the endian of the CPU,

The endian conversion circuit changes a rule of endian conversion in accordance with information about the endian of the CPU received from the signal line.

5. The processor of claim 1, wherein the processor further comprises a processor controller,

the byte order conversion circuit has a delay circuit that delays byte enable and data by 1 clock cycle if byte order conversion is required.

6. The processor of claim 1, comprising:

a 1 st bus; and

the 2 nd bus line is provided with a data bus,

the CPU is connected to the 1 st bus, outputs 1-byte or multi-byte data of 1 st byte order, an address signal of an access destination, a size signal indicating the size of the data, and a byte enable signal indicating which byte of the data is valid to the 1 st bus,

the plurality of peripheral circuits are connected to the 2 nd bus,

the byte order conversion circuit is arranged between the 1 st bus and the 2 nd bus,

the plurality of peripheral circuits includes:

a memory that interprets data of a 2 nd endian different from the 1 st endian every 1 st endian;

a first IO circuit that interprets the data of the 2 nd byte order every plural bytes; and

A second IO circuit that interprets the 1 st byte of data every multiple bytes,

the table includes an address range of the memory with respect to the memory, and as the category information of the memory, includes a byte order attribute representing the 2 nd byte order, and a type attribute representing the 1 st type of interpretation data every 1 byte irrespective of the value of the size signal,

the table includes an address range of the first IO circuit with respect to the first IO circuit, and includes, as the class information of the first IO circuit, a endian attribute representing the 2 nd endian, and a type attribute representing the 2 nd type interpreted for data each having a size represented by a value of the size signal,

the table includes an address range of the second IO circuit with respect to the second IO circuit, and includes, as the class information of the second IO circuit, a endian attribute indicating the 1 st endian, and a type attribute indicating the 2 nd type,

the byte order conversion circuit generates a 1 st signal controlling the byte enable conversion circuit and a 2 nd signal controlling the data conversion circuit based on the byte order attribute and the type attribute output from the table using the address signal of the access destination output from the CPU, and the size signal.

7. The processor of claim 6, wherein the processor further comprises,

the 1 st signal is set to a first value in a case where the byte order attribute indicates the 1 st byte order, the byte enable signal is output to the 2 nd bus without byte order conversion using the byte enable conversion circuit,

the 1 st signal is set to a second value if the byte order attribute indicates the 2 nd byte order, byte order conversion of the byte enable signal is implemented using the byte enable conversion circuit, and a converted byte enable signal is output to the 2 nd bus.

8. The processor of claim 6, wherein the processor further comprises,

a) The 2 nd signal is set to a first value in a case where the endian attribute indicates the 1 st endian, the data is output to the 2 nd bus without performing endian conversion using the data conversion circuit,

b) The 2 nd signal is set to a second value in a case where the endian attribute indicates the 2 nd endian and the type attribute is the 1 st type, outputs the data to the 2 nd bus without performing endian conversion using the data conversion circuit,

c) In the case where the endian attribute represents the 2 nd endian and the type attribute is the 2 nd type,

c1 The 2 nd signal is set to the second value when the size signal represents 1 byte, byte order conversion of the data is performed using the data conversion circuit and converted data is output to the 2 nd bus,

c2 The 2 nd signal is set to a third value when the size signal represents 2 bytes, byte order conversion of the data is performed using the data conversion circuit and converted data is output to the 2 nd bus,

c3 The 2 nd signal is set to the first value when the size signal indicates 4 bytes, and the data is output to the 2 nd bus without performing byte order conversion using the data conversion circuit.

9. A byte order conversion method of a processor including a CPU, a plurality of peripheral circuits, and a byte order conversion circuit provided between the CPU and the plurality of peripheral circuits, the byte order conversion circuit having a table storing category information indicating a relationship between an address and a category of a connection destination, a byte enable conversion circuit, and a data conversion circuit, the byte order conversion method comprising:

a) A step of extracting the category information from the table using an output address of an access destination outputted from the CPU; and

b) And controlling the byte enable converting circuit and the data converting circuit based on the extracted class information.

10. The method of claim 9, wherein,

the step a) includes a step of extracting the size information from the table,

in the b), the byte enable converting circuit and the data converting circuit are controlled based on the class information and the size information, respectively.

11. The method of claim 9, wherein,

the method includes the step of rewriting the stored value of the table of the byte order conversion circuit in response to a request from the CPU.

12. The byte order conversion method according to claim 9, comprising:

a step of changing the byte order of the CPU;

a step of transmitting information related to the byte order of the CPU to a signal line between the CPU and the byte order conversion circuit; and

and a step of changing a rule of byte order conversion by the byte order conversion circuit in accordance with information on byte order of the CPU received from the signal line.

13. The method of claim 9, wherein,

the byte order conversion circuit delays byte enabling and data by 1 clock period through a delay circuit when the byte order conversion is needed.