WO2023047762A1

WO2023047762A1 - Processor and endian conversion method

Info

Publication number: WO2023047762A1
Application number: PCT/JP2022/026785
Authority: WO
Inventors: 光太郎島村; 輝昭酒田; 勇気田中
Original assignee: 株式会社日立製作所
Priority date: 2021-09-21
Filing date: 2022-07-06
Publication date: 2023-03-30
Also published as: JP2023044909A; GB202401725D0; CN117795494A

Abstract

Provided is a means of preventing, in a processor having a CPU, a plurality of peripheral circuits, and an endian conversion circuit provided between the CPU and the plurality of peripheral circuits, a written value from being interpreted as a value different from that intended by a software creator when the peripheral circuits interpret the written value as a multi-byte value, to facilitate the creation of software. The endian conversion circuit has a table indicating a relationship between addresses and types of connection destinations, and a data conversion circuit and a byte-enable conversion circuit in the endian conversion circuit are controlled separately by using type information retrieved from the table through use of the address of the access destination.

Description

Processor and endian conversion method

The present disclosure relates to a processor having an endian conversion circuit provided between a CPU and peripheral circuits and an endian conversion method.

As background technology in this technical field, there is Japanese Patent Application Laid-Open No. 8-202646 (Patent Document 1). This publication describes an endian conversion circuit (converter) for facilitating connection between a CPU (main processor) and a peripheral circuit (I/O device) when the endian is different.

Japanese Patent Application Laid-Open No. 8-202646

The endian conversion circuit of Patent Document 1 rearranges data when the endian is different between the CPU and the peripheral circuit. For example, when a 4-byte hexadecimal value 00000001 is written from the CPU to the peripheral function, it is converted to 01000000. This corresponds to the fact that how to assign addresses to 4-byte numbers differs between little endian and big endian. Specifically, in little endian, addresses are assigned in order from lower byte to upper byte, while in big endian, addresses are assigned in order from upper byte to lower byte. Therefore, in order to store the same data at the same address when the data is interpreted in units of one byte, it is necessary to change the order of the data. However, if interpreted as a 4-byte number, a different value would be written. If the peripheral interprets the write value as a 4-byte value, it will interpret it differently than the software author intended. This is not limited to the case of 4 bytes, but in general, when interpreting a written value in units larger than 1 byte, it is interpreted as a value different from the value intended by the creator of the software.

The present disclosure is a processor having a CPU, a plurality of peripheral circuits, and an endian conversion circuit provided between the CPU and the plurality of peripheral circuits. It is an object of the present invention to provide means for facilitating the creation of software by preventing interpretation as values different from those intended by the creator.

Other issues and novel features will become apparent from the description and accompanying drawings of this specification.

A brief outline of representative items of the present disclosure is as follows.

In order to solve the above problem, in a processor according to one embodiment, an endian conversion circuit has a table indicating the relationship between an address and a connection destination type, and uses type information extracted from the table using an access destination address. separately controls the data conversion circuit and the byte enable conversion circuit in the endian conversion circuit.

According to the processor according to the above embodiment, when the endian of the CPU and the peripheral circuit are different, the byte enable is converted by the byte enable conversion circuit according to the difference in how to assign addresses to the data of multiple bytes, and the peripheral By converting the data by the data conversion circuit in consideration of how many bytes the circuit interprets the numerical value, it is possible for the peripheral circuit to correctly interpret the value intended by the creator of the software.

Problems, configurations, and effects other than those described above will be clarified by the following description of the embodiments.

1 is a first example of a configuration diagram of a processor to which the present invention is applied; FIG. It is an example of a timing chart of

buses

111 and 114 in FIG. 2 is an example of the operation of little endian byte enables of

buses

111 and 114 of FIG. It is an example of the big endian byte enable operation of bus 111 and bus 114 of FIG. 4 is a diagram showing a first example of an attribute information table of the control circuit 102 of FIG. 1; FIG. FIG. 2 is a diagram showing a first example of control signal generation rules of the control circuit 102 of FIG. 1; 2 is a first example of the control circuit 102 of FIG. 1; It is an example of the byte enable conversion circuit 104 of FIG. It is an example of the operation of the byte enable conversion circuit 104 of FIG. It is an example of the data conversion circuit 103 of FIG. It is an example of the operation of the data conversion circuit 103 of FIG. 2 is a first example of the operation of

buses

111 and 114 in FIG. 1; 4 is a diagram showing a second example of an attribute information table of the control circuit 102 of FIG. 1; FIG. 3 is a diagram showing a second example of a control signal generation rule for the control circuit 102 of FIG. 1; FIG. 2 is a second example of the operation of

buses

111 and 114 in FIG. 1; 2 is a second example of the control circuit 102 of FIG. 1; FIG. 4 is a second example of a configuration diagram of a processor to which the present invention is applied; 15 is a diagram showing an attribute information table of the control circuit 1402 of FIG. 14; FIG. 15 is a diagram showing a control signal generation rule of a control circuit 1402 of FIG. 14; FIG. FIG. 4 is a third example of a configuration diagram of a processor to which the present invention is applied; It is an example of the delay circuit 1601 of FIG. It is an example of a timing chart of

buses

111 and 114 in FIG.

Hereinafter, embodiments and examples will be described with reference to the drawings. However, in the following description, the same components may be denoted by the same reference numerals, and repeated descriptions may be omitted. In addition, in order to clarify the description, the drawings may be represented schematically as compared with actual embodiments, but they are only examples and do not limit the interpretation of the present invention.

The processor according to the embodiment has the following configuration.

That is, the processor (100) includes a CPU (101), a plurality of peripheral circuits (105-108), and an endian conversion circuit (109) provided between the CPU (101) and the plurality of peripheral circuits (105-108). ) and The endian conversion circuit (109) includes a table (AIT) storing type information (endian attribute, type attribute) indicating the relationship between the address and the type of connection destination, a byte enable conversion circuit (104), and a data conversion circuit. (103) and The endian conversion circuit (109) converts the byte enable conversion circuit (104) using the type information (endian attribute, type attribute) extracted from the table (AIT) using the output address of the access destination output from the CPU (101). and the data conversion circuit (103) are separately controlled.

Also, the endian conversion method according to the embodiment has the following configuration.

a CPU (101), a plurality of peripheral circuits (105 to 108), and an endian conversion circuit (109) provided between the CPU (101) and the plurality of peripheral circuits (105 to 108), wherein the endian conversion The circuit (109) includes a table (AIT) storing type information (endian attribute, type attribute) indicating the relationship between the address and the type of connection destination, a byte enable conversion circuit (104), and a data conversion circuit (103). , an endian conversion method for a processor (100) comprising:
a) a step of extracting type information (endian attribute, type attribute) from the table (AIT) using the output address of the access destination output from the CPU (101);
b) separately controlling the byte enable conversion circuit (104) and the data conversion circuit (103) based on the extracted type information (endian attribute, type attribute);

According to the processor and the endian conversion method according to the above-described embodiment, when the endian of the CPU and the peripheral circuit are different, the byte enable is converted by the byte enable conversion circuit according to the difference in how the addresses are assigned to the data of multiple bytes. In addition, by converting the data by the data conversion circuit in consideration of how many bytes the peripheral circuit interprets the numerical value, the peripheral circuit can correctly interpret the value intended by the creator of the software.

Examples will be described in detail below with reference to the drawings.

FIG. 1 is a first example of a configuration diagram of a processor to which the present invention is applied.

The processor 100 of this embodiment includes a CPU 101, an endian conversion circuit 109, a first peripheral circuit (ROM) 105, a second peripheral circuit (RAM) 106, a third peripheral circuit (first IO circuit) 107, a 4 peripheral circuits (second IO circuits) 108 , a first bus (hereinafter referred to as bus) 111 , and a second bus (hereinafter referred to as bus) 114 . The CPU 101 is connected to a bus 111 and includes a first peripheral circuit (ROM) 105, a second peripheral circuit (RAM) 106, a third peripheral circuit (first IO circuit) 107 and a fourth peripheral circuit (second IO circuit) 108 is connected to bus 114 . Endian conversion circuit 109 is connected between bus 111 and bus 114 . ROM is non-volatile memory such as read only memory, and RAM is volatile memory such as random access memory.

The endian conversion circuit 109 has a control circuit 102, a data conversion circuit 103, and a byte enable conversion circuit 104.

The CPU 101 executes the following processes according to the program stored in the first peripheral circuit (ROM) 105. The CPU 101 first takes in input information from a third peripheral circuit (first IO circuit: IO1) 107 and a fourth peripheral circuit (second IO circuit: IO2) 108 via

buses

114 and 111, After performing prescribed processing, output information is written to the third peripheral circuit (first IO circuit) 107 and fourth peripheral circuit (second IO circuit) 108 via

buses

111 and 114 . A second peripheral circuit (RAM) 106 is used for saving intermediate progress of processing.

When the third peripheral circuit (first IO circuit) 107 receives an input information fetch request from the CPU 101 via the

buses

111 and 114, the input information fetched from the signal line 115 is sent to the CPU 101 via the

buses

114 and 111. Output. When the third peripheral circuit (first IO circuit) 107 receives an output information write request from the CPU 101 via the

buses

111 and 114 , it internally holds the write value and outputs it to the signal line 115 .

The operation of the fourth peripheral circuit (second IO circuit) 108 is similar to the operation of the third peripheral circuit (first IO circuit) 107.

The control circuit 102 receives access address and access size information from the CPU 101 via the bus 111 , generates control signals for the byte enable conversion circuit 104 and the data conversion circuit 103 , and outputs them to

signal lines

112 and 113 .

The byte enable conversion circuit 104 performs predetermined conversion on the byte enable of the bus 111 according to the control signal (first signal) received from the signal line 112 and outputs it to the bus 114 .

The data conversion circuit 103 performs predetermined conversion on the write data on the bus 111 according to the control signal (second signal) received from the signal line 113 and outputs the converted data to the bus 114 . The data conversion circuit 103 also performs predetermined conversion on the read data of the bus 114 according to the control signal received from the signal line 113 and outputs the converted data to the bus 111 .

FIG. 2 is an example of a timing chart of

buses

111 and 114 in FIG. Since the operations of bus 111 and bus 114 are similar, they are described without distinguishing between them.

clk is a clock signal (1 bit), req is a request signal (1 bit), wr is a write signal (1 bit), size[2:0] is a size signal (size information) (3 bits), be[3:0] ] is a byte enable signal (4 bits), adr[31:2] is an address signal (30 bits), wd[31:0] is write data (32 bits), rdv is a read data valid signal (1 bit), rd [31:0] is read data (32 bits). size[2:0] indicates that it consists of a 3-bit signal of size[2], size[1], and size[0], where size[2] is the most significant bit and size[0] is the most significant bit. Lower bits. Similarly, be[3:0] is 4 bits from be[3] to be[0], adr[31:2] is 30 bits from adr[31] to adr[2], wd[31:0] is 32 bits from wd[31] to wd[0], and rd[31:0] consists of 32 bits from rd[31] to rd[0]. is the upper bit. req, wr, size[2:0], be[3:0], adr[31:2], wd[31:0] are signals from the CPU 101 to the peripheral circuits 105 to 108, rdv, rd[31: 0] are signals from the peripheral circuits 105 to 108 to the CPU 101 . Although the address space is 32 bits, since the write data and read data are 4 bytes, the lower 2 bits of the address are not transmitted. Instead, which byte of the 4 bytes of data is valid is indicated by byte enable. Byte enable operation will be described later. The size signal is one of three

binary numbers

001, 010, and 100, indicating that a transfer of 1 byte, 2 bytes, and 4 bytes (data transfer size) is to be performed, respectively.

Buses

111 and 114 each include a data bus including 32 data signal lines for transferring data, eg, wd[31:0] and rd[31:0], and adr[31:2]. is an address bus including 30 address signal lines for transferring address signals, a request signal (req: 1 bit), a write signal (wr: 1 bit), a size signal (size[2:0]: 3 bits ) and a control bus including nine control signal lines for transferring byte enable signals (be[3:0]: 4 bits).

The first cycle (cycle=1) is a write data transfer. When writing, req and wr are 1, and valid values (sz1, be1, a1, d1 ) is output.

The 3rd to 6th cycles are read data transfer. When reading, req is 1 and wr is 0. Effective values (sz2, be2, a2) are output to size[2:0], be[3:0], and adr[31:2] in the first cycle (third cycle). The number of read cycles is not fixed, and the transfer ends in the cycle in which rdv becomes 1. A valid value (d2) is output to rd[31:0] in the cycle in which rdv becomes 1. Although omitted in FIGS. 1 and 2, rdv and rd[31:0] are output by the peripheral circuits 105 to 108, respectively. With respect to rdv, the four peripheral outputs are OR'ed on bus 114 . FIG. 2 shows the state after the OR operation. As for rd[31:0], the output value of the peripheral circuit that outputs 1 to rdv on the bus 114 is selected. FIG. 2 shows the state after selection. If there is no peripheral circuit that outputs 1 to rdv, the value of rd[31:0] is ignored.

3A and 3B are examples of byte-enable operation of

buses

111 and 114 in FIG. FIG. 3A is an example of Little Endian byte enable operation for

buses

111 and 114 of FIG. FIG. 3B is an example of the operation of the Big Endian byte enable of

buses

111 and 114 of FIG. Little Endian Little Endian and Big Endian are described separately because their operations are different. Little endian can be said to be the first endian, and big endian can be said to be the second endian different from the first endian.

As mentioned above, there are three cases for the size of data to be transferred: 1 byte, 2 bytes, and 4 bytes.

In the case of 1-byte (8-bit) transfer (when the size signal: size[2:0] is 001), there are four cases ( 3A: be[3:0]:0001,0010,0100,1000, FIG. 3B: be[3:0]:1000,0100,0010,0001) (i.e., bus 111 and bus 114 each have data When 32 data lines DL31 to DL0 are included as a bus, 1-byte data is output to which data line group among the data line groups DL31 to DL24, DL23 to DL16, DL15 to DL8, and DL7 to DL0. may be). Little endian has a lower byte address and a higher byte address. On the other hand, big endian has a large lower byte address and a smaller upper byte address.

　Transfer of 2 bytes (16 bits) (when the size signal: size[2:0] is 010) is allowed only when the address is a multiple of 2. Therefore, there are two cases (Figure 3A::be[3:0]: 0011, 1100, Figure 3B: 1100, 0011 ) (that is, when each of the

buses

111 and 114 includes 32 data lines DL31 to DL0 as a data bus, 2-byte data can , there are two cases). A 2-byte transfer at address 4n corresponds to a superposition of 1-byte transfers at

addresses

4n and 4n+1, and a 2-byte transfer at address 4n+2 corresponds to a superposition of 1-byte transfers at addresses 4n+2 and 4n+3.

When transferring 4 bytes (32 bits) (when the size signal: size[2:0] is 100), all 4 bytes of data are valid, so all bits of byte enable become 1 (be[3:0]). ]:1111), the value of byte enable is the same for little endian and big endian.

4A and 4B are a first example of the operation of the control circuit 102 of FIG. FIG. 4A is a diagram showing a first example of the attribute information table AIT of the control circuit 102 of FIG. FIG. 4B is a diagram showing a first example of the control signal generation rule CSGR of the control circuit 102 of FIG.

The operation of the control circuit 102 is described by the attribute information table AIT and the control signal generation rule CSGR. The attribute information table AIT stores the address range and attribute information of each peripheral circuit.

The attribute information table AIT receives the address of the bus 111 (adr[31:2] with 0 concatenated to the lower two bits) and outputs the attribute information of the corresponding peripheral circuit. The attribute information can also be called peripheral circuit type information. There are two types of attribute information: endian and type. 0 is little endian and 1 is big endian. When the type is 0 (first type), it indicates that it is interpreted as a set of 1-byte data regardless of the value of the size signal (size[2:0]) of the bus 111 . When the type is 1 (second type), it indicates that data of 2 bytes or more is interpreted as data of the size indicated by the value of the size signal (size[2:0]) of bus 111 .

The control signal generation rule CSGR is a rule for generating values to be output to the

signal lines

112 and 113 with the endian, type, and size signal (size[2:0]) of the bus 111 output from the attribute information table AIT as inputs. is shown. Although not specified in this table, it is assumed that the endian of the CPU is little endian.

The signal line 112 (the value of the control signal) is 0 (first value) when the endian attribute is 0, and 1 (second value) when the endian attribute is 1. This indicates that byte enable conversion is not performed when the endian of the CPU and the peripheral circuit are the same, and byte enable conversion is performed when they are different.

The signal line 113 (the value of the control signal) takes three values: 00 (first value) indicates no data conversion, 01 (second value) indicates conversion of data in 1-byte units, and 10 (second value) indicates conversion of data in 1-byte units. A value of 3) indicates that the data should be converted in 2-byte units. The details of the conversion contents will be described later. The signal line 113 becomes 00 when the endian attribute is 0. This indicates that data conversion is not performed when the endian of the CPU and the peripheral circuit are the same. Signal line 113 is also always 01 (conversion in 1-byte units) when the endian attribute is 1 and the type attribute is 0. On the other hand, when the endian attribute is 1 and the type attribute is 1, the output value differs depending on the value of the size signal (size[2:0]) of bus 111 . When size[2:0] is 001 (1 byte), the output value is 01 (conversion in 1-byte units), and when size[2:0] is 010 (2 bytes), the output value is 10 (conversion in 2-byte units). ) and size[2:0] is 100 (4 bytes), the output value is 00 (no conversion).

FIG. 5 is a first example of the control circuit 102 of FIG.

The control circuit 102 of this embodiment has fixed

value output circuits

501, 502, 505, 506 and 507,

comparison circuits

503 and 504, AND

circuits

508, 509, 510, 513 and 514, and

OR circuits

511 and 512.

The fixed value output circuit 501 outputs the hexadecimal fixed value F0000000 to the signal line 521 .

The fixed value output circuit 502 outputs the hexadecimal fixed value F8000000 to the signal line 522 .

The comparison circuit 503 compares the address of the bus 111 (adr[31:2] with 2 bits of 0 concatenated in the lower order) and the value of the signal line 521 and outputs the result to the signal line 523 . The output value is 0 when the address is smaller than the fixed hexadecimal value F0000000, and 1 when the address is greater than the fixed value F0000000.

The comparison circuit 504 compares the address of the bus 111 (adr[31:2] with 2 bits of 0 concatenated to the lower order) and the value of the signal line 522 and outputs the result to the signal line 524 . The output value is 0 when the address is smaller than the fixed hexadecimal value F8000000, and 1 when the address is greater than the fixed value F8000000.

The fixed value output circuit 505 outputs the binary fixed value 10 to the signal line 525 .
The fixed value output circuit 506 outputs the binary fixed value 11 to the signal line 526 .
The fixed value output circuit 507 outputs the binary fixed value 01 to the signal line 527 .
The AND circuit 508 outputs the value of the signal line 525 to the signal line 528 when the value of the signal line 523 is 0. This corresponds to the first row of the attribute information table AIT in FIG. 4A. The AND circuit 508 also outputs 00 to the signal line 528 when the value of the signal line 523 is 1. In this case, the value of signal line 528 does not affect the output of OR circuit 511 .

The AND circuit 509 outputs the value of the signal line 526 to the signal line 529 when the value of the signal line 523 is 1 and the value of the signal line 524 is 0. This corresponds to the second row of the attribute information table AIT in FIG. 4A. The AND circuit 509 also outputs 00 to the signal line 529 when the value of the signal line 523 is 0 or the value of the signal line 524 is 1. In this case, the value of signal line 529 does not affect the output of OR circuit 511 .

The AND circuit 510 outputs the value of the signal line 527 to the signal line 530 when the value of the signal line 524 is 1. This corresponds to the third row of the attribute information table AIT in FIG. 4A. AND circuit 510 also outputs 00 to signal line 530 when the value of signal line 524 is 0. FIG. In this case, the value of signal line 530 does not affect the output of OR circuit 511 .

The OR circuit 511 ORs the three values of the

signal lines

528 , 529 and 530 and outputs the result to the signal line 531 . Since two of the three values on

signal lines

528, 529 and 530 are 00, the operation of OR circuit 511 effectively selects one of the three values on

signal lines

528, 529 and 530. It will be. The value output to the signal line 531 corresponds to the output of the attribute information table AIT in FIG. 4A.

The value of the endian attribute of the signal line 531 is output to the signal line 112 as it is.

OR circuit 512 outputs 1 to signal line 532 when the type attribute of signal line 531 is 0 or bit 0 of the size signal (size[2:0]) of bus 111 is 1 (equivalent to 1 byte). , otherwise 0 is output.

The AND circuit 513 outputs 1 to bit 0 of the signal line 113 when both the endian attribute of the signal line 531 and the value of the signal line 532 are 1. This operation corresponds to the case of outputting 01 to the signal line 113 in the second and third lines of the control signal generation rule CSGR in FIG. 4B. AND circuit 513 also outputs 0 when the endian attribute of signal line 531 or the value of signal line 532 is 0. FIG.

When the endian attribute and type attribute of the signal line 531 are both 1 and bit 1 of the size signal (size[2:0]) of the bus 111 is 1 (corresponding to 2 bytes), the AND circuit 514 Output 1 to bit 1. This operation corresponds to the case of outputting 10 to the signal line 113 in the fourth line of the control signal generation rule CSGR in FIG. 4B. AND circuit 514 also outputs 0 to bit 1 of signal line 113 when bit 1 of the endian attribute or type attribute of signal line 531 or the size signal (size[2:0]) of bus 111 is 0.

FIG. 6 is an example of the byte enable conversion circuit 104 of FIG.

The byte enable conversion circuit 104 consists of

selection circuits

601, 602, 603, and 604.

Selection circuit 601 selects bit 3 (be[3]) of the byte enable signal of bus 111 when the value of signal line 112 is 0, and selects bit 3 (be[3]) of the byte enable signal of bus 114. Output. Selection circuit 601 also selects bit 0 (be[0]) of the byte enable signal on bus 111 when the value on signal line 112 is 1, and selects bit 3 (be[3]) of the byte enable signal on bus 114. , output as a byte enable signal after endian conversion.

The operation of the

selection circuits

602, 603, and 604 is the same. When the value of the signal line 112 is 0, the left input is selected, and when the signal line 112 is 1, the right input is selected. output as a signal.

FIG. 7 is an example of the operation of the byte enable conversion circuit 104 of FIG.

When the signal line 112 is 0, the byte enable conversion circuit 104 outputs the same value as the input.

When the signal line 112 is 1, the byte enable conversion circuit 104 reverses the upper and lower order of the input and outputs it.

FIG. 8 is an example of the data conversion circuit 103 of FIG. Data conversion is performed on write data (wd[31:0]) and read data (rd[31:0]), but only the write data conversion circuit is shown in FIG. The read data conversion circuit has the same configuration.

The data conversion circuit 103 consists of

selection circuits

801, 802, 803, and 804.

When the value of the signal line 113 is 00, the selection circuit 801 selects bits 31 to 24 (wd[31:24]) of the write data on the bus 111, and selects bits 31 to 24 (wd[31:24]) of the write data on the bus 114. 31:24]) without endian conversion. The selection circuit 801 also selects bits 7 to 0 (wd[7:0]) of the write data on the bus 111 when the value of the signal line 113 is 01, and selects bits 31 to 24 (wd[7:0]) of the data on the bus 114 . 31:24]) as data after endian conversion. Selection circuit 801 also selects bits 15 to 8 (wd[15:8]) of the write data on bus 111 when the value on signal line 113 is 10, and selects bits 31 to 24 (wd[15:8]) of the write data on bus 114. [31:24]) as data after endian conversion.

The operation of the

selection circuits

802, 803, and 804 is similar. When the value of the signal line 113 is 00, the left input is selected. Selects the input on the right to output.

FIG. 9 is an example of the operation of the data conversion circuit 103 of FIG.

When the signal line 113 is 00, the data conversion circuit 103 outputs the same value as the input.

When the signal line 113 is 01, the data conversion circuit 103 reverses the upper and lower order of the input in units of bytes (8 bits) and outputs it.

When the signal line 113 is 10, the data conversion circuit 103 switches the upper 16 bits (bits 31 to 16) and the lower 16 bits (bits 15 to 0) for output.

FIG. 10 is a first example of the operation of

buses

111 and 114 in FIG. Although FIG. 10 does not describe the operation of read data, it is the same as that of write data.

The first peripheral circuit (ROM) 105 and the second peripheral circuit (RAM) 106 interpret the write data in 1-byte units regardless of the access size. Therefore, endian conversion is performed so that data at the same address are the same in byte units. For example, the least significant byte (s) of bus 111 is output to the most significant byte of bus 114 when the access size is 4 bytes. This is because the least significant byte of bus 111 corresponds to address 4n, while the most significant byte of bus 114 corresponds to address 4n.

The third peripheral circuit (first IO circuit) 107 interprets data in units of the same size as the access size. Therefore, endian conversion is performed so that the order of data is preserved in units of access size. For example, when the access size is 2 bytes and the address is 4n, the data is shifted from the lower to the upper while maintaining the data arrangement order (rs).
This ensures that the interpretation of data by the CPU 101 and the interpretation of data by the third peripheral circuit (first IO circuit) 107 are the same.

Since the endian of the fourth peripheral circuit (second IO circuit) 108 is the same as that of the CPU 101, endian conversion is not performed.

11A and 11B are a second example of the operation of the control circuit 102 of FIG. FIG. 11A is a diagram showing a second example of the attribute information table of control circuit 102 of FIG. FIG. 11B is a diagram showing a second example of control signal generation rules for the control circuit 102 of FIG.

The difference between the operation of the control circuit 102 in FIGS. 4A and 4B and FIGS. 11A and 11B is that the output of the register size is added to the attribute information table AIT in FIG. 11A, and the control signal in FIG. The only difference is the output of the rule CSGR. The register size attribute indicates the unit size in which the peripheral circuit to be accessed interprets the write value. As described in the description of FIG. 10, in the case of the operation of the control circuit 102 in FIGS. 4A and 4B, when accessing the third peripheral circuit (first IO circuit) 107, the same size as the access size is used as a unit. Interpret the data as In the case of such an operation, for example, if the third peripheral circuit (first IO circuit) 107 accesses 2 bytes or 4 bytes to an address that interprets data in units of 1 byte, a difference in interpretation with the CPU 101 occurs. There is a problem. In order to deal with such a problem, in the operation of the control circuit 102 in FIGS. 11A and 11B, the register size attribute of the third peripheral circuit (first IO circuit) 107 (in units of bytes to interpret data) The output of the signal line 113 is determined in accordance with .

In the attribute information table AIT of FIG. 11A, the area of the third peripheral circuit (first IO circuit) 107 is divided into three areas. 2 bytes are output for the attribute, and 4 bytes are output for the register size attribute at addresses F4000000 to F7FFFFFF. In the first peripheral circuit (ROM) 105, the second peripheral circuit (RAM) 106, and the fourth peripheral circuit (second IO circuit) 107, the value of the register size attribute is ignored in the control signal generation rule of FIG. 11B. Therefore, the output value of the register size attribute can be 1 byte, 2 bytes, or 4 bytes.

In the control signal generation rule CSGR in FIG. 11B, the operation when accessing the third peripheral circuit (first IO circuit) 107 is different from that in FIG. 4B. When the register size attribute is 1 byte, the output to signal line 113 is 01 regardless of the value of the size signal (size[2:0]) on bus 111 . This is the same as FIG. 4B when size[2:0] is 001 (1 byte), but the operation when size[2:0] is 010 (2 bytes) and 100 (4 bytes) is It is different from FIG. 4B. When the register size attribute is 2 bytes, the operation when size[2:0] is 001 (1 byte) and 010 (2 bytes) is the same as in FIG. 4B, but when size[2:0] is 100 (4 bytes) differs from FIG. 4B in that 10 is output to the signal line 113 . The operation when the register size attribute is 4 bytes is the same as in FIG. 4B.

FIG. 12 is a second example of the operation of

buses

111 and 114 in FIG. FIG. 12 corresponds to a second example of the operation of the control circuit 102 of FIGS. 11A and 11B. Operations for accessing the first peripheral circuit (ROM) 105, the second peripheral circuit (RAM) 106, and the fourth peripheral circuit (second IO circuit) 108 are the same as in FIG. , and the third peripheral circuit (first IO circuit) 107 only. In FIG. 12, size=1 indicates the operation when the register size attribute is 1 byte, size=2 indicates the operation when the register size attribute is 2 bytes, and size=4 indicates the operation when the register size attribute is 4 bytes.

When the register size attribute is 1 byte, the operation differs from that in FIG. 10 when the access size is 2 bytes and 4 bytes. In both cases, the same data is output to bytes with the same address in byte units. For example, if the access size is 4 bytes, the least significant byte (s) of bus 111 is output to the most significant byte of bus 114 . This is because the least significant byte of bus 111 corresponds to address 4n, while the most significant byte of bus 114 corresponds to address 4n. When the register size attribute is 1 byte, the third peripheral circuit (first IO circuit) 107 interprets data in 1-byte units. 107 data interpretation is guaranteed to be the same.

When the register size attribute is 2 bytes, the operation differs from that in FIG. 10 when the access size is 4 bytes. The lower two bytes (rs) of the bus 111 are output to the upper two bytes of the bus 114 while preserving the order of data arrangement. Since the lower two bytes of the bus 111 correspond to the

addresses

4n and 4n+1, the data is shifted to the same address area of the bus 114. It is guaranteed that the interpretation of the data of the first IO circuit) 107 will be the same. Similarly, the upper 2 bytes (pq) of the bus 111 are output to the lower 2 bytes of the bus 114 while preserving the data arrangement order.

FIG. 13 is a second example of the control circuit 102 of FIG.

The difference between control circuit 102 in FIG. 5 and control circuit 102A in FIG. 13 is that fixed

value output circuits

501, 502, 505, 506 and 507 in FIG. , the value can be rewritten from the bus 111 .

The write control circuit 1311 controls the request signal (req) of the bus 111 to be 1, the write signal (wr) to be 1, the size signal (size[2:0]) to be 100 (4 bytes), and the address signal (adr[31 :2]) is a predetermined value, a write control signal for the

memory circuits

1301 , 1302 , 1305 , 1306 and 1307 is output to one of the

signal lines

1321 , 1322 , 1325 , 1326 and 1327 . The write control signal consists of write enable and write data, and the write data is output by selecting part of the write data (wd[31:0]) on the bus 111 .

By adopting the configuration of the control circuit 102A of FIG. 13, it is possible to set the contents (stored values) of the attribute information table AIT of FIG. 4A from the CPU 101. FIG. That is, it has a function of rewriting the stored values of the table AIT according to a request from the CPU 101 or a step of rewriting the stored values of the table AIT according to a request from the CPU 101 . This makes it possible to use the same control circuit 102A even if the configuration of the peripheral circuit is changed.

FIG. 14 is a second example of a configuration diagram of a processor to which the present invention is applied.

The difference between processor 100 in FIG. 1 and processor 1400 in FIG. , to the control circuit 1402 . That is, the CPU 1401 has the function of changing the endian to little endian or big endian. The endian conversion circuit 1409 changes the endian conversion rule according to the information about the endian of the CPU 1401 received from the signal line 1411 . The processor 1400 performs a process of changing the endian of the CPU 1401, a process of transmitting information about the endian of the CPU 1401 to the signal line 1411 between the CPU 1401 and the endian conversion circuit 1409, and a process of transmitting information about the endian of the CPU 1401 received from the signal line 1411. and changing the endian conversion rule of the endian conversion circuit 1409 accordingly.

The control circuit 1402 generates signals to be output to the

signal lines

112 and 113 in consideration of the endian information of the CPU 1401 taken in from the signal line 1411 in addition to the built-in table AIT. Details will be described later.

15A and 15B are examples of the operation of the control circuit 1402 in FIG. 15A shows the attribute information table AIT of the control circuit 1402 of FIG. 14. FIG. FIG. 15B is a diagram showing the control signal generation rule CSGR of the control circuit 1402 of FIG.

The attribute information table AIT in FIG. 15A is the same as the attribute information table AIT in FIG. 4A.

On the other hand, the control signal generation rule CSRG in FIG. 15B differs from the control signal generation rule CSRG in FIG. 4B in that the value of the signal line 1411 is taken into consideration. The operation when the value of the signal line 1411 is 0 is the same as in FIG. 4B. When the value of the signal line 1411 is 1 and the endian attribute is 0, the endian of the CPU 1401 is different from that of the peripheral circuit. On the other hand, the signal line 113 is 01 when the type attribute is 0, and 01, 10, 00, or 00 depending on the value of the size signal (size[2:0]) of the bus 111 when the type attribute is 1. becomes. Since there is no case where the endian attribute is 0 and the type attribute is 0 in the attribute information table AIT of FIG. 15A, that case is not shown in FIG. 15B. If the value of the signal line 1411 is 1 and the endian attribute is also 1, the endian of the CPU 1401 and the peripheral circuit are the same.

FIG. 16 is a third example of a configuration diagram of a processor to which the present invention is applied.

The difference between the processor 100 in FIG. 1 and the processor 1600 in FIG. 16 is that the endian conversion circuit 1609 has a delay circuit 1601 . In the processor 100 of FIG. 1, the processing of the control circuit 102, the data conversion circuit 103, and the byte enable conversion circuit 104 takes time. It may lead to lower operating frequency. In order to deal with this problem, this embodiment divides the transfer from the CPU 101 to the peripheral circuits (105, 106, 107, 108) into two clock cycles by the delay circuit 1601 to shorten the transfer time per clock cycle. to prevent the operating frequency from dropping. The transfer of read data from the peripheral circuits (105, 106, 107, 108) to the CPU 101 is delayed by one clock cycle or more from the start of the transfer. Since the effect of lowering the operating frequency is negligible, the read data transfer is not divided into two clock cycles in this embodiment. However, since the transfer time becomes long due to the processing time of the data conversion circuit 103, the transfer of the read data may also be divided into clock cycles in order to eliminate the effect.

When the value fetched from the signal line 112 is 0, the delay circuit 1601 outputs the byte enable fetched from the signal line 1611 and the write data fetched from the signal line 1612 to the bus 114 as they are. The delay circuit 1601 also delays the byte enable signal received from the signal line 1611 and the write data received from the signal line 1612 by one clock cycle when the value received from the signal line 112 is 1, and outputs the delayed data to the bus 114 . The delay circuit 1601 also outputs the read data fetched from the bus 114 to the signal line 1612 as it is. The delay circuit 1601 also outputs the read data valid signal received from the bus 114 to the bus 111 as it is. In other words, the endian conversion circuit 1609 has a function or process of delaying byte enable and data by one clock cycle with the delay circuit 1601 when endian conversion is required.

FIG. 17 is an example of the delay circuit 1601 in FIG.

The delay circuit 1601 consists of

storage circuits

1701, 1702, 1703, 1705, AND

circuits

1704, 1709, 1710, 1711,

selection circuits

1706, 1707, 1708, and an OR circuit 1712.

The storage circuit 1701 delays the byte enable signal received from the signal line 1611 by one clock cycle and outputs it to the signal line 1721 .

The storage circuit 1702 delays the write data (wd[31:0]) fetched from the signal line 1612 by one clock cycle and outputs it to the signal line 1722 .

The storage circuit 1703 delays the write signal (wr), size signal (size[2:0]), and address signal (adr[31:2]) received from the bus 111 by one clock cycle and outputs them to the signal line 1723 .

The AND circuit 1704 ANDs the byte enable conversion valid signal received from the signal line 112 and the request signal (req) received from the bus 111 and outputs the result to the signal line 1724 .

The storage circuit 1705 delays the state of the signal line 1724 by one clock cycle and outputs it to the signal line 1725 .

The selection circuit 1706 outputs the value of the signal line 1721 as the byte enable signal (be[3:0]) of the bus 114 when the value of the signal line 1725 is 1. Selection circuit 1706 also outputs the byte enable signal (be[3:0]) of bus 111 as the byte enable signal (be[3:0]) of bus 114 when the value of signal line 1725 is 0. FIG.

When the value of the signal line 1725 is 1, the selection circuit 1707 outputs the value of the signal line 1722 as write data (wd[31:0]) of the bus 114 . The selection circuit 1707 also outputs the write data (wd[31:0]) of the bus 111 as the write data (wd[31:0]) of the bus 114 when the value of the signal line 1725 is 0.

When the value of the signal line 1725 is 1, the selection circuit 1708 converts the value of the signal line 1723 to the write signal (wr) of the bus 114, the size signal (size[2:0]), the address signal (adr[31:2] ). The selection circuit 1708 also outputs the write signal (wr), size signal (size[2:0]) and address signal (adr[31:2]) of the bus 111 to the bus 114 when the value of the signal line 1725 is 0. They are output as a write signal (wr), a size signal (size[2:0]), and an address signal (adr[31:2]).

The AND circuit 1709 ANDs the write signal (wr) on the signal line 1723 and the value on the signal line 1725 and outputs the result to the signal line 1729 .

The AND circuit 1710 takes the AND of the inverted value of the signal line 1725 and the value of the signal line 1724 and outputs it to the signal line 1730 . As a result, signal line 1730 is 1 for only one cycle when signal line 1724 rises.

The AND circuit 1711 takes the AND of the inverted value of the signal line 1730 and the request signal (req) of the bus 111 and outputs it to the signal line 1731 . As a result, the signal line 1731 becomes a signal obtained by delaying the rise of the request signal (req) of the bus 111 by one cycle only when the signal line 112 is 1.

The OR circuit 1712 ORs the value of the signal line 1729 and the value of the signal line 1731 and outputs it as a request signal (req) of the bus 114 .

FIG. 18 is an example of a timing chart of

buses

111 and 114 in FIG.

A write data transfer is performed on the bus 111 in the first cycle (cycle=1). Since signal line 112 is 1, the same write data transfer occurs in cycle 2 on bus 114 .

Read data transfer is performed on the bus 111 in the 3rd to 7th cycles. Since the signal line 112 is 1, the start of the same read data transfer on the bus 114 is delayed to the fourth cycle, but the end of the data transfer is the same as the bus 111 on the seventh cycle. This is the request signal (req), write signal (wr), size signal (size[2:0]), byte enable signal (be[3:0]), address signal (adr [31:2]) is delayed by one cycle, but there is no circuit to delay the read data valid signal (rdv) and read data (rd[31:0]) by one cycle.

Although the invention made by the present inventor has been specifically described above based on the examples, it goes without saying that the invention is not limited to the above-described embodiments and examples, and can be variously modified. .

100: Processor, 101: CPU, 103: Data Conversion Circuit, 104: Byte Enable Conversion Circuit, 105: First Peripheral Circuit (ROM), 106: Second Peripheral Circuit (RAM), 107: Third Peripheral Circuit (first IO circuit: IO1), 108: fourth peripheral circuit (second IO circuit: IO2), 109: endian conversion circuit, 501, 502, 505, 506, 507: fixed value output circuit (address and 1301, 1302, 1305, 1306, 1307: storage circuit (corresponding to a table showing the relationship between addresses and types of connection destinations), 1311: write control circuit, 1400: Processor 1401: CPU 1409: Endian conversion circuit 1411: Signal line for transmitting endian information of CPU 1600: Processor 1601: Delay circuit 1609: Endian conversion circuit

Claims

a CPU;
a plurality of peripheral circuits;
an endian conversion circuit provided between the CPU and the plurality of peripheral circuits;
The endian conversion circuit has a table for storing type information indicating the relationship between the types of addresses and connection destinations, a byte enable conversion circuit, and a data conversion circuit,
The endian conversion circuit separately controls the byte enable conversion circuit and the data conversion circuit using the type information extracted from the table using the output address of the access destination output from the CPU.
A processor characterized by:
2. The processor of claim 1, wherein
the table further includes size information about the size at which the destination interprets the data;
The endian conversion circuit separately controls the byte enable conversion circuit and the data conversion circuit using the type information and the size information extracted from the table.
A processor characterized by:
2. The processor of claim 1, wherein
The endian conversion circuit has a function of rewriting the stored values of the table according to a request from the CPU.
A processor characterized by:
2. The processor of claim 1, wherein
The CPU has a function to change the endian,
a signal line for transmitting information about the endian of the CPU between the CPU and the endian conversion circuit;
The endian conversion circuit changes the endian conversion rule according to the information about the endian of the CPU received from the signal line.
A processor characterized by:
2. The processor of claim 1, wherein
The endian conversion circuit has a delay circuit that delays byte enables and data by one clock cycle when endian conversion needs to be performed.
A processor characterized by:
2. The processor of claim 1, wherein
a first bus;
a second bus;
The CPU is connected to the first bus, and transmits to the first bus 1-byte or multiple-byte data of a first endian, an address signal of an access destination, a size signal indicating the size of the data, and the data. outputs a byte enable signal indicating which bytes of
the plurality of peripheral circuits are connected to the second bus;
The endian conversion circuit is provided between the first bus and the second bus,
The plurality of peripheral circuits are
a memory that interprets data in a second endian different from the first endian byte by byte;
a first IO circuit that interprets the second endian data in units of multiple bytes;
a second IO circuit that interprets the first endian data in units of multiple bytes;
The table is
For the memory, an address range of the memory, an endian attribute indicating the second endian as the type information of the memory, and a first type that interprets data byte by byte regardless of the value of the size signal. including type attributes and
With respect to the first IO circuit, the address range of the first IO circuit, the endian attribute indicating the second endian as the type information of the first IO circuit, and the value of the size signal are indicated. a type attribute indicating a second type to interpret for each size data,
With respect to the second IO circuit, an address range of the second IO circuit, and as the type information of the second IO circuit, an endian attribute indicating the first endian and a type attribute indicating the second type. , including
The endian conversion circuit converts the byte enable conversion circuit based on the endian attribute and the type attribute output from the table using the access destination address signal output from the CPU and the size signal. A processor that generates a first signal to control and a second signal to control the data conversion circuit.
7. The processor of claim 6, wherein
The first signal has a first value when the endian attribute indicates the first endian, and outputs the byte enable signal to the second bus without endian conversion using the byte enable conversion circuit. death,
The first signal has a second value when the endian attribute indicates the second endian, and the byte enable conversion circuit converts the endian of the byte enable signal into a converted byte enable signal. A processor that outputs to the second bus.
7. The processor of claim 6, wherein
The second signal is
a) if the endian attribute indicates the first endian, it is set to a first value and the data is output to the second bus without endian conversion using the data conversion circuit;
b) when the endian attribute indicates the second endian and the type attribute is the first type, a second value is given, and the data is converted to the data without endian conversion using the data conversion circuit; output to the second bus,
c) when the endian attribute indicates the second endian and the type attribute is the second type,
c1) when the size signal indicates 1 byte, it is set to the second value, endian conversion is performed on the data using the data conversion circuit, and the converted data is output to the second bus;
c2) when the size signal indicates 2 bytes, it is set to a third value, endian conversion is performed on the data using the data conversion circuit, and the converted data is output to the second bus;
c3) The processor, when the size signal indicates 4 bytes, is set to the first value and outputs the data to the second bus without endian conversion using the data conversion circuit.
A CPU, a plurality of peripheral circuits, and an endian conversion circuit provided between the CPU and the plurality of peripheral circuits, wherein the endian conversion circuit stores type information indicating a relationship between types of addresses and connection destinations. An endian conversion method for a processor having a table that
a) extracting the type information from the table using the output address of the access destination output from the CPU;
b) an endian conversion method including the step of separately controlling the byte enable conversion circuit and the data conversion circuit based on the extracted type information.
The endian conversion method according to claim 9,
The table further has size information about the size at which the connection destination interprets the data,
the step a) includes retrieving the size information from the table;
The endian conversion method, wherein the step b) separately controls the byte enable conversion circuit and the data conversion circuit based on the type information and the size information.
The endian conversion method according to claim 9,
An endian conversion method, comprising the step of rewriting stored values of the table of the endian conversion circuit in accordance with a request from the CPU.
The endian conversion method according to claim 9,
changing the endian of the CPU;
a step of transmitting information regarding the endian of the CPU to a signal line between the CPU and the endian conversion circuit;
and changing the endian conversion rule of the endian conversion circuit in accordance with information about the endian of the CPU received from the signal line.
The endian conversion method according to claim 9,
A method of endian conversion, comprising the step of delaying byte enable and data by one clock cycle with a delay circuit when said endian conversion circuit needs to perform endian conversion.