JPS6048789B2 - Prefix conversion control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a prefix conversion control scheme, in particular a method for converting the real address of a first address register directly into a second address register.
At the same time, the necessity of prefix conversion is checked, and only when the real address of the first address register requires prefix conversion, the real address is set to the first address register again. The present invention relates to a prefix conversion control method that increases the speed of electronic computers by performing prefix conversion after the ``transformation'' is performed.

In a multi-processor system in which multiple central processing units operate in parallel while sharing the main memory, each central processing unit processes error (machine check) information, interrupt information from input/output devices, and programs at interrupts. Information on the contents of the status word (PSW) is stored and used as unique information at a fixed address in the main memory.

Access to the main memory in a large computer with a multi-processor system is performed by converting the logical address on the program of each central processing unit to the real address of the main memory. Because the street address (unique address) is determined,
When accessing by each central processing unit, in order to access each unique address correctly, the above real address is further converted into a physical address (absolute address), and then the main memory is accessed. It has been adopted. That is, as mentioned above, this unique information is stored in a separate location for each central processing unit, that is, at a unique address in the main memory, so the logical address by the program in each central processing unit is different from that of other central processing units. When the unique address corresponds to the real address to be accessed, unless address conversion is performed, the unique address storing the operating system (hereinafter abbreviated as OS) of the other central processing unit mentioned above cannot be accessed. It will be put away. Therefore, in order to avoid such a situation, prefix conversion is performed to convert the real address that would undesirably access the unique address of another central processing unit to access another address in the main memory. That's what I do. In the control method of prefix conversion, which performs address conversion between the real address that specifies the unique address on the program and the absolute address of the main storage device, and creates a correspondence between them, conventionally, the necessity of the prefix conversion is Regardless of the presence or absence of the prefix conversion circuit, a configuration is adopted in which the contents of the first address register in which the real address is set are set in the second address register via the prefix conversion circuit.

Therefore, considering the frequency of occurrence, although there are many real addresses that do not require prefix conversion, it takes a long time to set the contents to the second address register via the prefix conversion circuit. This means that unnecessary processing time is being wasted on large-scale electronic computers, which are required to be faster. The present invention is aimed at solving the above-mentioned problems, and it is possible to directly convert the real address set in the first address register to the second address regardless of whether prefix conversion is necessary or not. The real address is set in the first address register and checked to see if there is a need for prefix conversion, and only when the prefix conversion is necessary, the real address is set in the first address register again and the real address is sent via the prefix conversion circuit. After performing address translation, the second address. It is configured to set the contents of address conversion in a register, and aims to shorten the time required for processing.

Therefore, the prefix conversion control method of the present invention is a multi-processor system in which a plurality of central processing units operate in parallel while sharing the main memory. , whether or not the contents of the real address should be converted when the contents of the real address set in the first address register are set as an absolute address in the second address register via the prefix conversion circuit. is set in the second address register with or without prefix conversion based on the output of the prefix detection circuit that detects the prefix, and the main memory is accessed using the set absolute address. In the multi-processor system, the first address . The content of the real address set in the register is directly set in the second address register, and the content of the real address set in the first address register is configured to be checked to see if there is a need for prefix conversion. When the contents of the address are those for which prefix conversion is to be performed, the contents of the address transferred to the second address register are set in the first address register again, prefix conversion is performed, and the contents of the address are transferred to the second address register. If the configuration is set to
The present invention is characterized in that when prefix conversion is not necessary for the contents of the real address set in the register, it is directly set from the first address register to the second address register. This will be explained below with reference to the drawings. Figure 1 is an example of an address conversion situation in the main memory to explain prefix conversion;
The figure shows the configuration of an example of a conventional prefix conversion control method.
FIG. 3 shows the configuration of an embodiment of the prefix conversion control system according to the present invention.

FIG. 1 is a diagram explaining prefix conversion by two central processing units, where 1 is a real address for central processing unit A, 2 is a real address for central processing unit B,
3 represents the absolute address of the main memory.

The main memory is usually divided into units of 4K bytes, and real address 1 for central processing unit A, real address 2 for central processing unit B, and absolute address 3 of the main memory are provided on each line. A short horizontal line indicates a line for each byte.

Part a of the real address 1 for the central processing unit A is an address part of the OS dedicated to the central processing unit A, and is associated with part c of the absolute address 3 of the main memory by prefix conversion. Therefore, when an access is made with an address in part a of real address 1 for central processing unit A as seen from central processing unit A, for example, address "3303" is prefix-converted and becomes absolute address 3 of the main memory. For example, the address of part c of “3303+M
”, and the main storage device will be accessed at the address “3303+M”. Similarly, part a of real address 2 for central processing unit B is address part 6 dedicated to central processing unit B, and the address is mapped to part c' of absolute address 3 of the main memory by prefix conversion. It will be done. Therefore, when an access is made with an address in part a of real address 2 for central processing unit B as seen from central processing unit B, for example, address "3303" is prefix-converted and becomes absolute address 3 of the main memory. For example, the address of the c' part of "3303+
The address is "33030N".
accesses the main memory. In this way, when accessing the address section of the OS dedicated to each of central processing units A and B, the main memory is shared by prefix converting the absolute address of the main memory to a different address. This enables parallel operation of central processing units A and B. Note that the addresses in part c of real addresses 1 and 2 for central processing units A and B are prefix-converted and converted into addresses in parts A and a' of absolute address 3 in the main memory.

Here, part a of absolute address 3 of the main storage device, that is, a'
The part address is an address that specifies a data area.
One of the conventional control methods for prefix conversion shown in Figure 2
In the example, 4 is the first address. Register (ADRI
), 5 represents a second address register (ADR2), 6 represents a prefix conversion circuit, and 7 represents a prefix detection circuit.

The first address register 4 is a register that sets the real address specified by each central processing unit.
When a real address is set in the first address register 4, the contents of bits 8 to 19 of the real address set in the first address register 4 are prefix-converted regardless of whether or not there is a need for prefix conversion. The data is transferred to the prefix conversion circuit 6 and the prefix detection circuit 7, and after waiting for the prefix detection circuit 7 to check whether or not there is a need for prefix conversion, if there is a need for prefix conversion, the prefix converted contents are transferred to the prefix conversion circuit 6 and the prefix detection circuit 7. If there is no need for conversion, the contents are set as they are in the second address register 5.

Further, the contents of bits 0 to 7 and bits 20 to 31 of the real address set in the first address register 4 are set in the second address register 5 as they are. As explained in FIG. 1, the prefix conversion circuit 6 converts the addresses in the a part of the real addresses 1 and 2 for the central processing unit into the c part and c' part of the absolute address 3 of the main memory, and also Address conversion is performed from the addresses in each part c of real addresses 1 and 2 for the central processing unit to part a, that is, part a', of absolute address 3 in the main memory.

The prefix detection circuit 7 is a circuit for detecting whether or not the content of the real address set in the first address register 4 requires prefix conversion. It is detected whether the address corresponds to the address of section a or the address of section c of Nos. 1 and 2.

That is, when all bits 0 to 19 of the real address set in the first address register 4 are detected as "O", and when the prefix in the prefix detection circuit 7 is detected.
There is a circuit that outputs a signal to the prefix conversion circuit 6 to perform prefix conversion corresponding to each case when it is detected that the contents of the bit match the contents of the register. As explained above, the contents of the real address set in the first address register 4 are transferred to the prefix conversion circuit 6 regardless of whether or not prefix conversion is necessary, and the address conversion from the prefix detection circuit 7 is executed. A conversion process is performed after waiting for a "no" signal and is set in the second address register 5, and the main memory is accessed using the address of the set contents.

As is clear from FIG. 1, the frequency with which real addresses to be prefix-converted are transferred as they are without being prefix-converted is relatively high. It is obvious that the processing time will be longer if the user waits until the end of the process. FIG. 3 shows the configuration of an embodiment of the prefix conversion control method according to the present invention.
corresponds to that in FIG. 2, 8 and 9 represent flip-flop circuits, and 10 and 11 represent selection circuits.

The flip-flop circuit (FFI) 8 receives the output from the flip-flop circuit (FF2) 9 and sets the logic value to "1".
is set to be set, and when the logical value "1" is set, the first address . The bit contents from register 4 are converted into addresses by prefix conversion corresponding to the respective bit contents.

The flip-flop circuit 9 is a prefix detection circuit 7.
is set in response to a signal issued when it is detected that the content of the real address set in the first address register 4 is an address to which prefix conversion is to be performed, and opens the selection circuit 10; This circuit causes the contents set in the second address register 5 to be set again in the first address register 4 via the selection circuit 10. In the prefix conversion control method according to the present invention, the contents set in the first address register 4 are directly transferred to the second address. It is set in the register 5 and also supplied to the prefix detection circuit 7.

Then, according to the detection result by the prefix detection circuit 7, if the detection result does not require prefix conversion, the second address register. The first set for evening 5
The contents transferred directly from the address register are used as is in subsequent circuits. That is, the real address is used as the absolute address of the main memory and becomes the address to be accessed. On the other hand, when the detection result of the prefix detection circuit 7 requires prefix conversion, the logic value "1" is set in the flip-flop circuit 9, and the logic value "1" causes the selection circuit 1 to be set.
0 circuit is opened, and the contents set in the second address register, E5, are set in the first address register 4 again. Also, the logic value of the flip-flop circuit 9 is “1”.
” sets the flip-flop circuit 8 to the logic value “1”.
", and the prefix conversion circuit 6 outputs the logical value "
1" is input. As a result, the contents of bits 8 to 19 of the real address set again in the first address register 4 are transferred to the prefix conversion circuit 6,
A prefix conversion circuit 6 performs prefix conversion. Bits 0 to 7 and 2 of the real address set again in the first address register 4? or 3
The contents of 1 are directly set in the second address register 5, and the prefix-converted address is set in the second address register 5 and becomes the absolute address of the main memory. In the prefix conversion control system according to the present invention, when the logic value "1" is set in the flip-flop circuit 9, the content set in the second address register 5 is transferred to the first address register 5 via the selection circuit 10.
By setting the address register 4 of the address register 4 again, the logical value "1" of the flip-flop circuit 9 causes the central processing unit that is sending out the real address to set the same real address as the first address again. - Having the data transferred to the register 4 and performing prefix conversion is also included as an embodiment of the present invention.

As explained above, according to the present invention, the first address.
The real address set in the register is directly converted to the second address. By setting the address in the register and supplying it to the prefix detection circuit, and creating the absolute address of the main memory device via the prefix conversion circuit only when prefix conversion is necessary, it is possible to - Enables high-speed calculation processing by the processor.

[Brief explanation of the drawing]

FIG. 1 shows an example of an address conversion situation in the main memory to explain prefix conversion. The configuration of one embodiment of such a prefix conversion control method is shown. In the figure, 4 is the first address register, 5 is the second address register. 6 represents a prefix conversion circuit, 7 represents a prefix detection circuit, and 8 and 9 represent flip-flop circuits.

Claims (1)

[Claims] 1 A multi-processor system in which multiple central processing units operate in parallel while sharing the main memory,
When accessing the main memory, when the contents of the real address set in the first address register are set as an absolute address in the second address register via the prefix conversion circuit, the above-mentioned The set absolute address is set in the second address register with or without prefix conversion based on the output of a prefix detection circuit that detects whether or not the contents of the address should be converted. In a multi-processor system in which the main memory is accessed by the first address register, the content of the real address set in the first address register is directly set in the second address register, and The address is configured to check whether there is a need for prefix conversion, and is transferred to the second address register when the content of the real address set in the first address register is an address to which prefix conversion is to be performed. The contents of the first address register are set again to the first address register, prefix conversion is performed, and the contents are set to the second address register.
A prefix conversion control method characterized in that when prefix conversion is not required for the contents of a real address set in a register, the content is directly set from a first address register to a second address register.