CN103095289B - Signal delay control circuit - Google Patents
Signal delay control circuit Download PDFInfo
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- CN103095289B CN103095289B CN201110349001.3A CN201110349001A CN103095289B CN 103095289 B CN103095289 B CN 103095289B CN 201110349001 A CN201110349001 A CN 201110349001A CN 103095289 B CN103095289 B CN 103095289B
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Abstract
The invention provides a signal delay control circuit which at least comprises a first in first out (FIFO) unit, a writing pointer control unit, a read pointer control unit, a latch unit and a drive unit. A programmable delay unit and a semi-stable state unit are arranged between the writing pointer control unit and the read pointer control unit. The programmable delay unit enables the read pointer and the writing pointer to maintain a corresponding phase relation through output delay and enables the operation of the read pointer to be after the operation of the writing pointer. The semi-stable state unit is used for conducting a semi-stable state detection before the operation of the read pointer and does not carry out operation on the read pointer when the semi-stable state is detected. Due to the fact that the semi-stable state unit is reset during the next clock period, the problem that burrs are generated under the circumstance of initialization of inputting of clock frequency changes in the prior art is solved, periodical resetting of the read pointer is achieved when an input clock is stable, and reliability of the circuit is improved.
Description
Technical field
The present invention relates to the Time delay control technical field of signal, particularly relate to a kind of signal delay control circuit.
Background technology
In the integrated circuit (IC) chip in modern times, some system to need between module and module or between chip and chip transfer of data to meet fixing its function of delay relation guarantee normal.Because this type systematic place may under different technique, voltage, temperature, frequency condition, how designing one, to ensure that data delay is fixed with transmitting reliable circuit structure be the problem needing to consider.
In the prior art, commonly adopt the circuit that a FIFO and latch is formed, by the read-write clock of phase-locked loop (i.e. phase-locked loop, PLL) control FIFO, make both meet fixing phase relation, thus the fixed delay realizing input signal export.When circuit working is at stable input clock frequency, this technology is all well positioned to meet the timing requirements of settling time and retention time at different technique, voltage, temperature.But, this circuit structure is when initialization or input clock frequency change, circuit easily produces burr, find by analysis, cause the reason of burr to have 2 points: to be a bit because phase-locked loop is in initialized process, the clock of output also after unstable or clock stable the read-write clock phase of control FIFO do not fix; On the other hand due to input clock frequency change time, FIFO read pointer may adopt metastable state, thus less desirable saltus step occurs, and then is unfavorable for the stable of circuit.
Thus, how a kind of signal delay control technology is provided, the Burr Problem produced when initialization or input clock frequency change in prior art can be overcome, and regularly can reset to read pointer when input clock is stablized, improve the reliability of circuit, become those skilled in the art's problem demanding prompt solution in fact.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of signal delay control circuit, produce burr and FIFO read pointer generation saltus step for solving system in prior art when initialization or input clock frequency change, and then be unfavorable for the stability problem of circuit.
For achieving the above object and other relevant objects, the invention provides a kind of signal delay control circuit, at least comprise: sampling unit, gather address signal according to system clock and also export; Logical block, exports data after described collection address signal being carried out logical process according to system clock; Cell fifo, the data of reception store by sensing according to write pointer successively, and the data that described read pointer points to are exported successively according to the principle of first in first out; Write pointer control unit, according to system clock, controls the data of described write pointers point for write; Read pointer control unit, according to reading clock, controls the data that described read pointer points to wish reading; The data that described cell fifo exports are latched by latch units, and foundation reads transfer of data to driver element that clock will latch; Also comprise and be connected to programmable delay unit between described write pointer control unit and read pointer control unit and metastable state unit, described programmable delay unit by exporting the time delay phase relation that makes described read pointer and write pointer keep corresponding, and makes after the operation of described read pointer is positioned at the operation of described write pointer; Described metastable state unit is used for carrying out metastable state detecting before described read pointer operation, and does not operate read pointer when metastable state being detected, resets in the next clock cycle.
Preferably, in described programmable delay unit, be preset with acquiescence delay value and a question blank, in described question blank, be preset with the corresponding delay value of each this clock frequency of many group clock frequencies and correspondence.Described programmable delay unit exports described acquiescence delay value in system initialisation phase; Described programmable delay unit extracts should the corresponding delay value of clock frequency at system frequency changes phase according to the clock frequency of input in described question blank; Described programmable delay unit keeps fixing delay value in the system frequency stabilization sub stage.
Preferably, described metastable state unit passes through the identical clock of frequency sampled signal and the signal through fixed delay respectively, and adopts this clock respectively through same delay and reverse sampled signal afterwards, and the 4 groups of data obtained are carried out metastable state detection and process.Described metastable state unit is also for regularly resetting to described read pointer when input clock is stablized.
Preferably, described cell fifo is made up of at least two D type flip-flop and a data distributor and a data selector.Described write pointer control unit, according to writing clock, controls the data of described write pointers point for write, so as by the data for write via described data distributor successively stored in described at least two D type flip-flop.Described read pointer control unit, according to reading clock, controls the data that described read pointer points to wish reading, the data for reading to be exported successively via described data selector from described at least two D type flip-flop.
As mentioned above, signal delay control circuit of the present invention carries out FIFO by a programmable delayer and reads and writes pointer check and correction, makes both can be consistent when normal work.Can metastable state detection be carried out before read pointer operation, and read pointer is regularly resetted.Under circumstance of initialization, the value of delayer is a fixing enough large time delay, and can ensure that read pointer is after write pointer, the data of adopting are stable data, no matter whether the clock of latch units is stablized, all there will not be burr.When input clock frequency changes, this delay unit can change accordingly according to different frequencies, and ensures that FIFO reads and writes the consistency of pointer by metastable state unit.Signal delay control circuit of the present invention can overcome the Burr Problem that prior art produces when initialization or input clock frequency change, and regularly can reset to read pointer when input clock is stablized, and improves the reliability of circuit.
Accompanying drawing explanation
Fig. 1 is shown as the theory diagram of signal delay control circuit of the present invention.
Fig. 2 is shown as the sequential chart of signal delay control circuit of the present invention.
Fig. 3 is shown as the theory diagram of cell fifo in signal delay control circuit of the present invention.
Fig. 4 is shown as the theory diagram of the signal delay control circuit Central Asia of the present invention steady state cell.
Fig. 5 is shown as the sequential chart of the signal delay control circuit Central Asia of the present invention steady state cell.
Element numbers explanation
11 sampling units
12 logical blocks
13 cell fifos
131 data distributors
132 data selectors
133,134,135 D type flip-flop
14 latch units
15 driver elements
16 write pointer control units
17 read pointer control units
18 programmable delay unit
19 metastable state unit
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 to Fig. 5.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Refer to Fig. 1, be shown as the theory diagram of signal delay control circuit of the present invention, as shown in the figure, the invention provides a kind of signal delay control circuit, at least comprise: sampling unit 11, logical block 12, cell fifo 13, latch units 14, driver element 15, write pointer control unit 16, read pointer control unit 17, programmable delay unit 18, and metastable state unit 19.
Described sampling unit 11 gathers address signal according to system clock and exports, and described logical block 12 exports data after described collection address signal being carried out logical process according to system clock.
The data of reception store according to the sensing of write pointer by described cell fifo 13 successively, and according to the principle of first in first out, the data that described read pointer points to are exported successively, described write pointer control unit 16 is according to system clock, control the data of described write pointers point for write, described read pointer control unit 17, according to reading clock, controls the data that described read pointer points to wish reading.
The data that described cell fifo 13 exports are latched by described latch units 14, and according to transfer of data to driver element 15 read clock and will latch, described driver element 15 is such as performing the chip of certain function, electronic component or circuit module etc.
The write pointer control unit 16 of signal delay control circuit of the present invention be also connected programmable delay unit 18 and a metastable state unit 19 between read pointer control unit 17.Wherein, described programmable delay unit 18 by exporting the time delay phase relation that makes described read pointer and write pointer keep corresponding, and makes after the operation of described read pointer is positioned at the operation of described write pointer; Described metastable state unit 19 for carrying out metastable state detecting before described read pointer operation, and does not operate read pointer when metastable state being detected, resets in the next clock cycle.In the present embodiment, described programmable delay unit 18 is a delayer (leveling).
Refer to Fig. 1, as shown in the figure, from figure, can be clearly seen that there is steering needle unit bottom described cell fifo 13, be respectively and control write pointer " Wr_ptr " according to system clock " CK_ca " and point to for the write pointer control unit 16 of the data " data " of write with according to reading clock, control read pointer " Rd_ptr " and point to read pointer control unit 17 for the data " data " read.The metastable state unit 19 having a programmable delay unit 18 between two above-mentioned steering needle unit and be connected with described programmable delay unit 18, read-write pointer is made to keep corresponding phase relation by configurating programmable delay unit 18, no matter be under initialization or input clock frequency situation of change, the data that latch exports are all stable data.When described metastable state unit 19 detects metastable state, read pointer " Rd_ptr " value can be kept constant, prevent because metastable state causes read pointer " Rd_ptr " dap and produce burr.
Fig. 1 please be coordinate to consult Fig. 2 more simultaneously, as shown in the figure, write clock " Ck_write " (assumption period is 1.5ns) to meet the sequential (can see from the circuit diagram of Fig. 1) of previous groups combinational logic circuit, and between system clock " Ck_ca " (assumption period also for 1.5ns), have fixing logical delay (1ns).When writing clock " Ck_write " rising edge and arriving, the data " data " of logical block 12 being come successively write in cell fifo 13.Make after read pointer " Rd_ptr " appears at write pointer " Wr_ptr " by programmable programmable delay unit 18 and metastable state unit 19, and keep corresponding phase relation, thus make the numerical value of two pointers keep synchronous (for convenience of reader's understanding, read pointer " Rd_ptr " sequential in diagram is respectively with Rd_ptr<1>, Rd_ptr<2> and Rd_ptr<3> is illustrated, correspondingly, write pointer " Wr_ptr " sequential in diagram is also respectively with Wr_ptr<1>, Wr_ptr<2> and Wr_ptr<3> is illustrated).Read also to have between clock " Ck_read " and system clock " Ck_ca " time delay " Tpdm-Toutput " that fixing as we can see from the figure, the input and output that wherein " Tpdm " fixes for chip postpone, " Toutput " drives time delay to the driver element 15 in Fig. 1 for exporting, when the trailing edge of system clock " Ck_ca " arrives, data " data " are exported from cell fifo 13, and at the rising edge of next clock, data " data " are exported (as Suo Shi " dout " Fig. 2) from driver element 15, ensure that it meets " Tpdm " time of regulation, and sequential can not be caused to break rules and burr, and then improve the reliability and stability of circuit.
Refer to Fig. 3, as shown in the figure, described cell fifo 13 is by least two D type flip-flop, in the present embodiment, such as be described for three D type flip-flop (i.e. diagram in DFF133,134 and 135), described three D type flip-flop 133,134 and 135 and a data distributor (i.e. Demux in diagram) 131 and data selector (i.e. Mux in diagram) 132 compositions.Wherein, described write pointer control unit 16 according to writing clock, control described write pointers point for write data so that by for write data via described data distributor 131 successively stored in described three D type flip-flop 133,134 and 135.Described read pointer control unit 17, according to reading clock, controls the data that described read pointer points to wish reading, the data for reading to be exported successively via described data selector 132 from described three D type flip-flop 133,134 and 135.Namely, by Fig. 3 by known with the contrast of Fig. 1, write pointer " Wr_ptr " and write clock " Ck_write " effect under, by data " data " successively stored in three D type flip-flop, under the effect of read pointer " Rd_ptr ", data " data " are exported successively from three D type flip-flop.
In the present embodiment, in described programmable delay unit 18, be preset with acquiescence delay value and a question blank, in described question blank, be preset with the corresponding delay value of each this clock frequency of many group clock frequencies and correspondence.
Described programmable delay unit 18 exports described acquiescence delay value in system initialisation phase, and particularly, at initial phase, the default value of described programmable delay unit 18 is one to be fixed and enough large time delay.This acquiescence delay value is by drawing after sequential computational analysis, when circuit connect with the mains carry out transfer of data time, can ensure that the read pointer of cell fifo 13 is after write pointer, the data of adopting are stable data, no matter whether the clock of phase-locked loop is stablized, this circuit all there will not be burr.The acquiescence delay value in this stage also can be finely tuned by register after the power-up accordingly simultaneously.
Described programmable delay unit 18 extracts should the corresponding delay value of clock frequency, particularly, in the frequency change stage at system frequency changes phase according to the clock frequency of input in described question blank.Provide a question blank be made up of input clock frequency and various Tpdm value in described programmable delay unit 18, when electric circuit inspection changes to frequency or Tpdm value, corresponding delay value just can adjust according to question blank accordingly.
Described programmable delay unit 18 keeps fixing delay value in the system frequency stabilization sub stage, particularly, in the frequency stabilization stage, the clock that now phase-locked loop produces is stable, delay value is also fixing constant, that is keeps constant with the value of a upper delay cycle.
In the present embodiment, described metastable state unit 19 passes through the identical clock of frequency sampled signal and the signal through fixed delay respectively, and adopt this clock respectively through same delay and reverse sampled signal afterwards, the 4 groups of data obtained are carried out metastable state detection and process.Described metastable state unit 19 is also for regularly resetting to described read pointer when input clock is stablized.Refer to Fig. 4 and Fig. 5, as shown in the figure, in order to make the reading and writing pointer of cell fifo 13 keep corresponding phase relation, and in order to avoid adopting metastable state in the process due to read pointer, cause read pointer that less desirable saltus step occurs, invention increases a metastable state unit 19 based on this.First described metastable state unit 19 passes through the identical clock of frequency sampled signal and the signal through fixed delay respectively by described metastable state unit 19, and adopt this clock through same delay sampled signal, obtain 3 groups of data obtained are respectively: " din_s ", " din_pre_s ", " din_post_s ".When appearance " din_pre_s " signal is low level, and " din_s " and " din_post_s " signal is high level; Or occur that the signal that " din_pre_s " and " din_s " detects is low level, and when the signal that " din_post_s " detects is high level, now metastable state unit 19 preliminary judgement detects metastable state.Then use the trailing edge of " clk " to detect signal, if when the signal detected " din_neg_s " is for high level, what now metastable state unit 19 was just determined to detect above further is metastable state.Based on this, metastable state unit 19, in the appearance metastable cycle, does not reset to the value of read pointer " Rd_ptr "; The non-metastable cycle detected at the next one, just the value of read pointer " Rd_ptr " is resetted, also namely regularly reset.
Refer to Fig. 5, be shown as the sequential chart of metastable state unit.In figure, " Wr_ptr " and " Rd_ptr " is respectively write pointer, read pointer, and show " Rd_ptr " respectively do not having metastable state occur (in as figure shown in Rd_ptr A), metastable state occurs but not process (as shown in Rd_ptr B in figure), and metastable state occurs going forward side by side the numerical value change in row relax (as shown in Rd_ptr C in figure) three kinds of situations.In figure, circled represents and metastable state signal detected this moment.
In sum, signal delay control circuit of the present invention carries out FIFO by a programmable delay unit and reads and writes pointer check and correction, makes both can be consistent when normal work.Can metastable state detection be carried out before read pointer operation, and read pointer is regularly resetted.Under circumstance of initialization, the value of programmable delay unit is a fixing enough large time delay, and can ensure that read pointer is after write pointer, the data of adopting are stable data, no matter whether the clock of latch units is stablized, all there will not be burr.When input clock frequency changes, this programmable delay unit can change accordingly according to different frequencies, and is detected and treatment circuit by metastable state, ensures that FIFO reads and writes the consistency of pointer.Signal delay control circuit of the present invention can overcome the Burr Problem that prior art produces when initialization or input clock frequency change, and regularly can reset to read pointer when input clock is stablized, and improves the reliability of circuit.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (9)
1. a signal delay control circuit, at least comprises:
Cell fifo, the data of reception store by sensing according to write pointer successively, and the data that read pointer points to are exported successively according to the principle of first in first out;
Write pointer control unit, according to system clock, controls the data of described write pointers point for write;
Read pointer control unit, according to reading clock, controls the data that described read pointer points to wish reading;
The data that described cell fifo exports are latched by latch units, and foundation reads transfer of data to driver element that clock will latch;
It is characterized in that, also comprise and be connected to programmable delay unit between described write pointer control unit and read pointer control unit and metastable state unit, described programmable delay unit by exporting the time delay phase relation that makes described read pointer and write pointer keep corresponding, and makes after the operation of described read pointer is positioned at the operation of described write pointer; Described metastable state unit is used for carrying out metastable state detecting before described read pointer operation, and read pointer is not operated when metastable state being detected, reset in the next clock cycle, described metastable state unit is also for regularly resetting to described read pointer when input clock is stablized;
Or, under circumstance of initialization, the value of described programmable delay unit is a fixing enough large time delay, to guarantee that described read pointer is after described write pointer, the data of adopting are stable data, no matter whether the clock of described latch units is stable all there will not be burr;
Or when input clock frequency changes, described delay unit can change accordingly according to different frequencies, and ensure that FIFO reads and writes the consistency of pointer by described metastable state unit.
2. signal delay control circuit according to claim 1, it is characterized in that: in described programmable delay unit, be preset with acquiescence delay value and a question blank, in described question blank, be preset with the corresponding delay value of each this clock frequency of many group clock frequencies and correspondence.
3. signal delay control circuit according to claim 2, is characterized in that: described programmable delay unit exports described acquiescence delay value in system initialisation phase; Described programmable delay unit extracts should the corresponding delay value of clock frequency at system frequency changes phase according to the clock frequency of input in described question blank; Described programmable delay unit keeps fixing delay value in the system frequency stabilization sub stage.
4. signal delay control circuit according to claim 1, it is characterized in that: described metastable state unit passes through the identical clock of frequency sampled signal and the signal through fixed delay respectively, and adopt this clock respectively through same delay and reverse sampled signal afterwards, at least 3 group data obtained are carried out metastable state detection and process.
5. signal delay control circuit according to claim 1, is characterized in that: described cell fifo is made up of at least two D type flip-flop and a data distributor and a data selector.
6. signal delay control circuit according to claim 5, it is characterized in that: described write pointer control unit is according to writing clock, control described write pointers point for write data so that by for write data via described data distributor successively stored in described at least two D type flip-flop.
7. signal delay control circuit according to claim 5, it is characterized in that: described read pointer control unit is according to reading clock, control the data that described read pointer points to wish reading, the data for reading to be exported successively via described data selector from described at least two D type flip-flop.
8. signal delay control circuit according to claim 1, is characterized in that: also comprise sampling unit, gathers address signal and export according to system clock.
9. signal delay control circuit according to claim 8, is characterized in that: also comprise logical block, exports data to described cell fifo after described collection address signal being carried out logical process according to system clock.
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| CN201110349001.3A CN103095289B (en) | 2011-11-08 | 2011-11-08 | Signal delay control circuit |
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| CN201110349001.3A CN103095289B (en) | 2011-11-08 | 2011-11-08 | Signal delay control circuit |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104216462B (en) * | 2014-08-27 | 2017-02-15 | 电子科技大学 | Large-dynamic and high-precision programmable time delay device based on FPGA (field programmable gate array) |
| CN105677593B (en) * | 2016-01-11 | 2018-09-28 | 福州瑞芯微电子股份有限公司 | Chip memory write operation timing path adaptive regulation method and device |
| CN105701041B (en) * | 2016-01-11 | 2018-09-28 | 福州瑞芯微电子股份有限公司 | The method and apparatus that chip automatic adjusument reads timing path |
| CN110618950B (en) * | 2018-06-19 | 2023-02-17 | 中国科学院上海高等研究院 | Asynchronous FIFO read-write control circuit and method, readable storage medium and terminal |
| CN111262583B (en) * | 2019-12-26 | 2021-01-29 | 普源精电科技股份有限公司 | Metastable state detection device and method and ADC circuit |
| CN111211777B (en) * | 2020-01-14 | 2021-12-07 | 中山大学 | System, method and device for preventing chip time sequence violation |
| CN113342717A (en) * | 2021-06-22 | 2021-09-03 | 京微齐力(深圳)科技有限公司 | FIFO read-write control method and control circuit |
| CN115085701A (en) * | 2022-07-09 | 2022-09-20 | 深圳市速腾聚创科技有限公司 | Circuit and method for diagnosing clock burr, clock circuit, chip and radar |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1658596A (en) * | 2004-02-19 | 2005-08-24 | 安捷伦科技有限公司 | FIFO module, deskew circuit and rate matching circuit having the same |
| CN1682476A (en) * | 2002-07-17 | 2005-10-12 | 英特尔公司 | Techniques to reduce transmitted jitter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7292080B2 (en) * | 2005-08-25 | 2007-11-06 | Infineon Technologies Ag | Delay locked loop using a FIFO circuit to synchronize between blender and coarse delay control signals |
-
2011
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1682476A (en) * | 2002-07-17 | 2005-10-12 | 英特尔公司 | Techniques to reduce transmitted jitter |
| CN1658596A (en) * | 2004-02-19 | 2005-08-24 | 安捷伦科技有限公司 | FIFO module, deskew circuit and rate matching circuit having the same |
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Address after: A6, No. 900 Yishan Road, Xuhui District, Shanghai, 2003 Patentee after: Lanqi Technology Co., Ltd. Address before: Room 406A, 4th floor, 32 Guiping Road, Xuhui District, Shanghai, 2003 Patentee before: Acrospeed, Inc. |