CN109155798A

CN109155798A - A kind of asynchronous FIFO circuit and time delay determine method

Info

Publication number: CN109155798A
Application number: CN201680086087.6A
Authority: CN
Inventors: 夏山春; 张志伟; 陈默
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-05-27
Filing date: 2016-05-27
Publication date: 2019-01-04
Anticipated expiration: 2036-05-27
Also published as: CN109155798B; WO2017201727A1

Abstract

The embodiment of the invention provides a kind of asynchronous FIFO circuits and time delay to determine method, is related to wireless communication field.The asynchronous FIFO circuit includes: to write clock generation circuit, read clock generation circuit, write address generation circuit, read address generation circuit, random access storage device, delay line, sync logic, address comparison logic circuit and processor；The second output terminal of write address generation circuit and the first input end of delay line connect, second input terminal of delay line and the first output end of processor connect, the output end of delay line and the first input end of sync logic connect, the output end of sync logic is connect with the first input end of address comparison logic circuit, the output end of read address generation circuit is connect with the third input terminal of address comparison logic circuit, and the first output end of address comparison logic circuit and the input terminal of processor connect.The accurate determination to the time delay of asynchronous FIFO circuit may be implemented in the present invention.

Description

A kind of asynchronous FIFO circuit and time delay determine method

Technical field

The present embodiments relate to wireless communication field, in particular to a kind of asynchronous FIFO (First Input First Output, First Input First Output) circuit and time delay determine method.

Background technique

In a wireless communication system, it often include multiple communication equipments, the clock domain of multiple communication equipment is substantially independent, and the clock domain for multiple modules that same communication equipment includes is also independent substantially, therefore, the transmission of the data between different clock-domains is substantially in the data transmission in multiple communication equipment between any two communication equipment or in the data transmission in multiple modules between any two module.Such as, common public radio interface (the Common Public Radio Interface of any two communication equipment, CPRI the data transmission between) is the data transmission of different clock-domains, Remote Radio Unit (Remote Radio Unit in same communication equipment, RRU) the data transmission on interior digital RF front end (Digital Front End, DFE) between modules is also the data transmission of different clock-domains.In order to guarantee integrality that data are transmitted between different clock-domains, often carried out data transmission using the asynchronous FIFO circuit of communication equipment.In addition, permitted multiple services normal operation in a wireless communication system and requires accurate Timing Synchronization, and often there is certain time delay in asynchronous FIFO circuit, the introducing of the asynchronous FIFO circuit time delay prevent communication equipment from accurately determining transmitting-receiving time of data, the Timing Synchronization precision of communication equipment is impacted, therefore, when being carried out data transmission by asynchronous FIFO circuit, in order to improve the Timing Synchronization precision of communication equipment, it is thus necessary to determine that the time delay of the asynchronous FIFO circuit.

At present, provide a kind of asynchronous FIFO circuit, as shown in Figure 1, the asynchronous FIFO circuit includes: to write clock generation circuit 1, read clock generation circuit 2, write address generation circuit 3, read address generation circuit 4, random access storage device 5, sync logic 6 and address comparison logic circuit 7.Referring to Fig. 1, the output end 1a for writing clock generation circuit 1 is connect with the input terminal 3a of write address generation circuit 3, first output end 3b of write address generation circuit 3 is connect with the first input end 5a of random access storage device 5, the second output terminal 3c of write address generation circuit 3 is connect with the first input end 6a of sync logic 6, the output end 6b of sync logic 6 is connect with the first input end 7a of address comparison logic circuit 7, second input terminal 6c of sync logic 6 and the second input terminal 7b of address comparison logic circuit 7 are connect with the output end 2a for reading clock generation circuit 2 respectively；Read clock generation circuit 2 output end 2a also with read address generation circuit 4 input terminal 4a connection, the output end 4b of read address generation circuit 4 is connect with the third input terminal 7c of the second input terminal 5b of random access storage device 5 and address comparison logic circuit 7 respectively, and the output end 7d of address comparison logic circuit 7 is connect with the set end 4c of read address generation circuit 4.

Wherein, by taking the data transmission in wireless communication process system between the communication equipment of any two different clock-domains as an example, if the first communication equipment needs target data to be transmitted being transferred to the second communication equipment, at this point, the first communication equipment can carry out write operation and read operation to the random access storage device in the fifo circuit that itself includes.When the first communication equipment carries out write operation to random access storage device, write address generation circuit can generate writing address signal in the rising edge for the write clock signal for writing clock generation circuit generation, write address is carried in the writing address signal, the first communication equipment target data can be written in random access storage device on position corresponding to the write address.Simultaneously, when the first communication equipment carries out read operation to random access storage device, read address generation circuit can generate read address signal in the rising edge for reading the read clock signal that clock generation circuit generates, read address is carried in the read address signal, first communication equipment can be from reading the data stored on position corresponding to the read address in random access storage device, and the data of reading are transferred to the second communication equipment.Wherein, during the first communication equipment and the second communication equipment transmission data, specified read/write address difference and the product of clock cycle can also be determined as the time delay of the asynchronous FIFO circuit by the first communication equipment, specified address difference of the read/write address difference between pre-set write address and read address, clock cycle is the period of read clock signal or write clock signal, and read clock signal is equal with the period of write clock signal.

In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:

The true time delay of asynchronous FIFO circuit includes decimal time delay and integer time delay two parts, decimal time delay is introduced by the phase difference between read clock signal and write clock signal, and integer time delay is introduced to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation by synchronization.Decimal time delay is not determined in the prior art, integer time delay has only been determined, and the integer time delay is determined directly as to the time delay of asynchronous FIFO circuit, causes asynchronous FIFO circuit time delay definitive result inaccurate.

Summary of the invention

In order to solve the problems, such as the relevant technologies, the present invention provides a kind of asynchronous FIFO circuits and time delay to determine method.The technical solution is as follows:

First aspect, a kind of fifo circuit is provided, the asynchronous FIFO circuit includes: to write clock generation circuit, read clock generation circuit, write address generation circuit, read address generation circuit, random access storage device, delay line, sync logic, address comparison logic circuit and processor；

The output end for writing clock generation circuit is connect with the input terminal of the write address generation circuit, described First output end of write address generation circuit is connect with the first input end of the random access storage device, the second output terminal of the write address generation circuit is connect with the first input end of the delay line, second input terminal of the delay line is connect with the first output end of the processor, the output end of the delay line is connect with the first input end of the sync logic, the output end of the sync logic is connect with the first input end of the address comparison logic circuit, second input terminal of the second input terminal of the sync logic and the address comparison logic circuit is connect with the output end for reading clock generation circuit respectively；

The output end for reading clock generation circuit is also connect with the input terminal of the read address generation circuit, the output end of the read address generation circuit is connect with the second input terminal of the random access storage device, the output end of the read address generation circuit is also connect with the third input terminal of the address comparison logic circuit, and the first output end of the address comparison logic circuit is connect with the input terminal of the processor.

Wherein, clock generation circuit is write for generating write clock signal；Clock generation circuit is read for generating read clock signal；Write address generation circuit is for generating multiple writing address signals and writing indication signal, write address is carried in each writing address signal, it is that at least two write addresses generated based on write address generation circuit are generated that this, which writes indication signal, and it is the second logic level by the jump of the first logic level that this, which writes indication signal when write address generation circuit generates specified write address, wherein, multiple writing address signals of generation can be sent to random access storage device by the first output end of itself by write address generation circuit, and the indication signal of writing of generation can be sent to by delay line by the second output terminal of itself；Read address generation circuit is for generating multiple read address signals, read address is carried in each read address signal, wherein, multiple read address signals of generation can be sent to random access storage device and address comparison logic circuit by the output end of itself by read address generation circuit；Random access storage device is for storing data；Delay line is used to postpone the indication signal of writing for inputting the delay line, and the indication signal of writing after delay is sent to sync logic；Sync logic is used to write indication signal in the rising edge reception for reading the read clock signal that clock generation circuit generates, and the received indication signal of writing of institute is sent to address comparison logic circuit；Address comparison logic circuit is used to be based on to write indication signal and read address signal, determines that read/write address is poor, which is currently to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation；The read/write address that processor is used to determine based on address comparison logic circuit is poor, it determines decimal time delay, and is based on the decimal time delay, determine the time delay of asynchronous FIFO circuit, wherein, the introduced time delay of phase difference of the decimal time delay between read clock signal and write clock signal.

It should be noted that, writing clock generation circuit, reading clock generation circuit, write address generation circuit, read address generation circuit, random access storage device, delay line and sync logic can realize that address comparison logic circuit and processor in practical applications can be in a software form in the form of hardware in practical applications It realizes, the embodiment of the present invention is not specifically limited in this embodiment.

In embodiments of the present invention, asynchronous FIFO circuit includes writing clock generation circuit, reading clock generation circuit, write address generation circuit, read address generation circuit, random access storage device, delay line, sync logic, address comparison logic circuit and processor.Wherein, multiple read address signals of generation can be sent to address comparison logic circuit by read address generation circuit, the indication signal of writing of generation can be sent to delay line by write address generation circuit, the delay line can will be write and be sent to address comparison logic circuit by sync logic after indication signal postpones, address comparison logic circuit can be based on writing indication signal and read address signal, determine that read/write address is poor, since the read/write address that processor can be determined based on address comparison logic circuit is poor, determine decimal time delay, and it is based on the decimal time delay, determine the time delay of asynchronous FIFO circuit, therefore, the accurate determination to the time delay of asynchronous FIFO circuit may be implemented.

With reference to first aspect, in the first possible implementation of above-mentioned first aspect, the second output terminal of the address comparison logic circuit is connect with the set end of the read address generation circuit.

Wherein, address comparison logic circuit is used for when detecting that writing indication signal jumps to the second logic level by the first logic level, and the read address currently generated to read address generation circuit is reset.

In embodiments of the present invention, address comparison logic circuit can reset the read address that read address currently generates, to guarantee that synchronization is poor to the read/write address that the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation is a certain fixation, guarantee that the integer time delay of asynchronous FIFO circuit is fixed.

With reference to first aspect or the first possible implementation of first aspect, in second of possible implementation of above-mentioned first aspect, the second output terminal of the processor is connect with the reset terminal of the write address generation circuit, and the third output end of the processor is connect with the reset terminal of the read address generation circuit.

Wherein, processor is used for when receiving reset setting instruction, third address is set by write address electrification reset value, the 4th address is set by read address electrification reset value, third address is that specified read/write address is poor with four address address difference, write address electrification reset value is the initial write address that write address generation circuit generates when powering on, and read address electrification reset value is the initial read address that read address generation circuit generates when powering on.

It should be noted that resetting setting instruction for being configured to write address electrification reset value and read address electrification reset value.

In embodiments of the present invention, third address can be set by write address electrification reset value, the 4th address is set by read address electrification reset value, and third address is that specified read/write address is poor with four address address difference, to guarantee asynchronous FIFO circuit when powering on rigid start-up operation, it is that specified read/write address is poor to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation, to protect It is all the same to demonstrate,prove the time delay of the asynchronous FIFO circuit in whole work process.

Any possible implementation into second of possible implementation of first aspect with reference to first aspect, in the third possible implementation of above-mentioned first aspect, the delay line includes: N-1 delay section and N number of tap, and the N is the natural number greater than 1；

The N-1 delay section is connected in series, one end of i-th of delay section is connect with i-th of tap in N number of tap in the N-1 delay section, the other end of i-th of delay section is connect with i+1 tap in N number of tap in the N-1 delay section, and the i is greater than or equal to 1 and is less than or equal to N-1.

It should be noted that each delay in N-1 delay section is saved and is postponed in the indication signal of writing for inputting the delay section.

In addition, since the number of the delay section in N number of tap between each tap and write address generation circuit is fixed, and each delay section can will input the delay of the delay section write indication signal and the time is fixed, so, N number of tap and N number of default time delay correspond.Therefore, for each tap in N number of tap, when delay line, which detects, writes indication signal, indication signal can will be write by the tap postpone to delay when the tap is corresponding default and be sent to sync logic.

Furthermore delay line is delayed when being also used to write indication signal delay second and is sent to sync logic.Wherein, the second time delay is that can eliminate the metastable time delay of sync logic.Delay line will be delayed when will write indication signal delay second and be sent to sync logic, metastable state can occur to avoid sync logic, so that guaranteeing that sync logic can receive stable writes indication signal.

In embodiments of the present invention, N number of tap and N number of default time delay in delay line correspond, delay line can pass sequentially through N number of tap, it will write to delay when indication signal successively postpones N number of default and address comparison logic circuit is sent to by sync logic, so that address comparison logic circuit can successively determine that N number of read/write address is poor correspondingly with N number of pre-set delay, and then guarantee that subsequent processor can be poor based on N number of read/write address, realize the accurate determination to decimal time delay.

Any possible implementation into the third possible implementation of first aspect with reference to first aspect, in the 4th kind of possible implementation of above-mentioned first aspect, the sync logic includes multiple concatenated triggers, and each trigger is used to write indication signal in the rising edge reception of the read clock signal of the reading clock generation circuit generation in the multiple concatenated trigger.

Wherein, the first order trigger in multiple triggers that sync logic includes writes indication signal in the rising edge reception of read clock signal, and this is write into indication signal and is sent to second level trigger, second level trigger receives this in the rising edge of read clock signal and writes indication signal, and this is write into indication signal and is sent to third level trigger, in this way, until this, which is write indication signal, is sent to the m grades of triggers that sync logic includes M grades of triggers receive this in the rising edge of read clock signal and write indication signal, and this is write indication signal and is sent to address comparison logic circuit, and m is natural number, and m is more than or equal to 2.

It should be noted that, first order trigger to m grades of triggers in multiple trigger are obtained according to the series sequence determination of multiple trigger, it that is to say, the trigger connecting with delay line can be determined as first order trigger, the trigger after first order trigger is successively determined as m grades of second level trigger, third level trigger ... triggers.

In embodiments of the present invention, sync logic can will write indication signal by multiple triggers and be sent to sync logic, since each trigger is to write indication signal in the rising edge reception for reading the read clock signal that clock generation circuit generates and sent in multiple concatenated trigger, therefore, it may be implemented to write indication signal synchronous with the signal of read address signal, and then be based on writing indication signal and read address signal convenient for subsequent address CL Compare Logic circuit, determine that read/write address is poor.

The third possible implementation with reference to first aspect, in the 5th kind of possible implementation of above-mentioned first aspect, the read address generation circuit, for the multiple read address signals generated to be sent to the address comparison logic circuit；

The write address generation circuit, indication signal of writing for that will generate is sent to the delay line, the indication signal of writing is that at least two write addresses based on write address generation circuit generation generate, and the indication signal of writing is jumped when the write address generation circuit generates specified write address by the first logic level as the second logic level；

The processor, for passing through the read address generation circuit, the delay line, the sync logic and the address comparison logic circuit, indication signal, the multiple read address signal and the read clock signal reading clock generation circuit and generating are write based on described, obtain that N number of read/write address is poor, N number of default time delay in N number of read/write address difference and the delay line corresponds；

The processor, it is also used to based on N number of read/write address difference and interconnection delay, determine decimal time delay, and it is based on the decimal time delay, determine the time delay of the asynchronous FIFO circuit, the introduced time delay of wiring of the interconnection delay between the write address generation circuit and the sync logic, the decimal time delay are the introduced time delay of the phase difference between the read clock signal and the write clock signal for writing clock generation circuit generation.

In embodiments of the present invention, processor can pass through read address generation circuit, delay line, sync logic and address comparison logic circuit, based on the read clock signal for writing indication signal, multiple read address signals and reading clock generation circuit generation, it is poor to obtain N number of read/write address, and based on N number of read/write address difference and interconnection delay, determine decimal time delay, and then be based on the decimal time delay, determine asynchronous FIFO circuit when Prolong, realizes the accurate determination to the asynchronous FIFO circuit.

The 5th kind of possible implementation with reference to first aspect, in the 6th kind of possible implementation of above-mentioned first aspect, the delay line, for when detect it is described write indication signal when, by it is described write indication signal and postpone to delay when i-th of tap is corresponding default in N number of tap the address comparison logic circuit is sent to by the sync logic, N number of tap and N number of default time delay correspond；

The address comparison logic circuit, for when the rising edge in the read clock signal detect it is described to write indication signal by first logic level jump be second logic level when, obtain the read address carried in the read address signal being currently received, and the read address based on the specified write address and acquisition, it determines that the corresponding read/write address of i-th of tap is poor, the corresponding read/write address difference of i-th of tap is sent to the processor；

The processor, for when receiving the corresponding read/write address difference of i-th of tap, enable the i=i+1, again through the delay line by it is described write indication signal and postpone to delay when i-th of tap is corresponding default in N number of tap the address comparison logic circuit is sent to by the sync logic.

It should be noted that, processor can be configured the currently used tap of delay line, it that is to say, processor can default time delay currently used to delay line be configured, to guarantee that delay line can successively traverse N number of tap, indication signal will be write and successively postpone N number of default time delay.

In the embodiment of the present invention, a circulate operation can be executed by the cooperation of delay line, sync logic, address comparison logic circuit and processor, to guarantee that the corresponding read/write address of available tap each into N number of tap is poor, it that is to say, it is poor each to preset the corresponding read/write address of time delay for Yanzhong when can guarantee to get N number of default, and then can guarantee the accuracy being delayed when subsequent processor determines decimal based on N number of read/write address difference.

Second aspect provides a kind of time delay and determines method, applied in asynchronous FIFO circuit described in any possible implementation in the 6th kind of possible implementation of above-mentioned first aspect to first aspect, which comprises

During carrying out read operation and write operation to the random access storage device, multiple read address signals of generation are sent to the address comparison logic circuit by the read address generation circuit, the indication signal of writing of generation is sent to the delay line by the write address generation circuit, and the indication signal of writing is based on described At least two write addresses of write address generation circuit generation generate, and the indication signal of writing is jumped when the write address generation circuit generates specified write address by the first logic level as the second logic level；

The processor passes through the read address generation circuit, the delay line, the sync logic and the address comparison logic circuit, indication signal, the multiple read address signal and the read clock signal reading clock generation circuit and generating are write based on described, it is poor to obtain N number of read/write address, N number of default time delay in N number of read/write address difference and the delay line corresponds, and the N is the natural number greater than 1；

The processor is based on N number of read/write address difference and interconnection delay, determine decimal time delay, the introduced time delay of wiring of the interconnection delay between the write address generation circuit and the sync logic, the decimal time delay are the introduced time delay of the phase difference between the read clock signal and the write clock signal for writing clock generation circuit generation；

The processor is based on the decimal time delay, determines the time delay of the asynchronous FIFO circuit.

Wherein, during carrying out read operation to random access storage device, when read address generation circuit detects a rising edge of read clock signal, generate a read address signal, read address is carried in the read address signal, it that is to say, read address generation circuit can generate a read address signal within each period of read clock signal.Simultaneously, during carrying out write operation to random access storage device, write address generation circuit, which can produce, writes indication signal and multiple writing address signals, write address is carried in each writing address signal, and when write address generation circuit detects that the write address of generation is specified write address, it is the second logic level that this can be write to indication signal and jumped from the first logic level.

In addition, the state of the state of the first logic level and the second logic level is on the contrary, such as when the first logic level is 0, the second logic level can be 1；When the first logic level is 1, the second logic level can be 0, and the embodiment of the present invention is not specifically limited in this embodiment.

Furthermore write address generation circuit can also be when the write address for detecting generation be any write address except specified write address, and it is the first logic level that this, which is write indication signal from the jump of the second logic level, and the embodiment of the present invention is not specifically limited in this embodiment.

In embodiments of the present invention, processor can pass through read address generation circuit, delay line, sync logic and address comparison logic circuit, based on the read clock signal for writing indication signal, multiple read address signals and reading clock generation circuit generation, it is poor to obtain N number of read/write address, and based on N number of read/write address difference and interconnection delay, decimal time delay is determined, and then be based on the decimal time delay, it determines the time delay of asynchronous FIFO circuit, realizes the accurate determination to the asynchronous FIFO circuit.

In conjunction with second aspect, in the first possible implementation of above-mentioned second aspect, the delay line Circuit includes N-1 delay section and N number of tap, and N number of tap and N number of default time delay correspond；

The processor passes through the read address generation circuit, the delay line, the sync logic and the address comparison logic circuit, indication signal, the multiple read address signal and the read clock signal reading clock generation circuit and generating are write based on described, it is poor to obtain N number of read/write address, comprising:

When the delay line detect it is described write indication signal when, by it is described write indication signal and postpone to delay when i-th of tap is corresponding default in N number of tap the address comparison logic circuit is sent to by the sync logic, the i is greater than or equal to 1 and is less than or equal to N-1；

When the address comparison logic circuit the rising edge of the read clock signal detect it is described to write indication signal by first logic level jump be second logic level when, obtain the read address carried in the read address signal being currently received, read address based on the specified write address and acquisition, it determines that the corresponding read/write address of i-th of tap is poor, and the corresponding read/write address difference of i-th of tap is sent to the processor；

When the processor receives the corresponding read/write address difference of i-th of tap, the i=i+1 is enabled, return is described to be postponed the indication signal of writing to delay the step of being sent to the address comparison logic circuit by the sync logic when i-th of tap is corresponding default in N number of tap.

In addition, since the number of the delay section in N number of tap between each tap and write address generation circuit is fixed, and each delay section can will input the delay of the delay section write indication signal and the time is fixed, so, N number of tap and N number of default time delay correspond.

Furthermore, processor can be configured the currently used tap of delay line, it that is to say, processor can default time delay currently used to delay line be configured, to guarantee that delay line can successively traverse N number of tap, indication signal will be write and successively postpone N number of default time delay.

In conjunction with the first possible implementation of second aspect, in second of possible implementation of above-mentioned second aspect, read address of the address comparison logic circuit based on specified write address and acquisition determines institute It is poor to state the corresponding read/write address of i-th of tap, comprising:

The address comparison logic circuit determines the address difference between the specified write address and the read address of acquisition；

The number for the trigger that the sync logic includes is subtracted 1 by the address comparison logic circuit, obtains the first numerical value；

Determining address difference is added by the address comparison logic circuit with first numerical value, and it is poor to obtain the corresponding read/write address of i-th of tap.

In embodiments of the present invention, it is to be jumped when write address generation circuit generates specified write address by the first logic level as the second logic level due to writing indication signal, and it is to be sent to address comparison logic circuit after being synchronized logic circuit delays the first numerical value clock cycle that this, which writes indication signal, therefore, address comparison logic circuit detect this write indication signal by the first logic level jump be the second logic level when, write address generation circuit produces the first numerical value write address after generating the specified write address again, so currently carrying out the address difference between the write address and specified write address of write operation to random access storage device is the first numerical value.Again since address comparison logic circuit is used to determine synchronization to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation, and the read address signal that address comparison logic circuit is currently received is transmitted directly to address comparison logic circuit, do not postponed, therefore, when address comparison logic circuit specifies based on this read address of write address and acquisition, when determining the corresponding read/write address difference of i-th of tap, determining address difference can be added with the first numerical value, it is poor to obtain the corresponding read/write address of i-th of tap, realize the accurate determination to i-th of tap corresponding read/write address difference.

In conjunction with second aspect to second aspect second of possible implementation in any possible implementation, in the third possible implementation of above-mentioned second aspect, the processor is based on the N number of read/write address difference and interconnection delay, before determining decimal time delay, further includes:

The processor obtains the introduced maximum delay and minimal time delay of wiring between the write address generation circuit and the sync logic from the wiring report of the rear end of storage, and the rear end wiring report is for recording the introduced time delay of all wirings that the asynchronous FIFO circuit includes；

The average value of the maximum delay and the minimal time delay is determined as the interconnection delay by the processor.

In embodiments of the present invention, since the position of write address generation circuit and sync logic can impact interconnection delay, therefore, it can be when carrying out the wiring of the asynchronous FIFO circuit, constrain the position of write address generation circuit and sync logic as close possible to, so that the variation for being routed introduced maximum delay and minimal time delay between write address generation circuit and sync logic is minimum, to be based on the maximum delay The interconnection delay determined with the minimal time delay is small as far as possible and stablize, to guarantee the accuracy being delayed when processor determines decimal based on the interconnection delay.

In conjunction with second aspect to second aspect the third possible implementation in any possible implementation, in the 4th kind of possible implementation of above-mentioned second aspect, the processor is based on N number of read/write address difference and interconnection delay, determines decimal time delay, comprising:

The processor be based on N number of read/write address it is poor, from it is described N number of default when Yanzhong determine the first time delay；

The sum of first time delay and the interconnection delay are determined as the decimal time delay by the processor.

In embodiments of the present invention, processor can be poor based on N number of read/write address, and Yanzhong determines the first time delay when N number of default from this, and the sum of first time delay and interconnection delay are determined as decimal time delay, to realize the accurate determination to decimal time delay.

In conjunction with the 4th kind of possible implementation of second aspect, in the 5th kind of possible implementation of above-mentioned second aspect, the processor be based on N number of read/write address it is poor, from it is described N number of default when Yanzhong determine the first time delay, comprising:

The processor is based on N number of default time delay, is ranked up to N number of read/write address difference, obtains the sequence of N number of read/write address difference；

Sequence of the processor based on N number of read/write address difference, it is poor that the first read/write address is obtained from N number of read/write address difference, the first read/write address difference is to be obtained based on the read/write address difference determination jumped in N number of read/write address difference, and the read/write address difference of the jump is that the read/write address different from previous position read/write address difference is poor；

The corresponding default time delay of the first read/write address difference is determined as first time delay by the processor.

Optionally, processor is based on N number of default time delay, when being ranked up to N number of read/write address difference, sequence that can be ascending according to N number of default time delay, N number of read/write address difference is ranked up, it is of course also possible to the sequence descending according to N number of default time delay, N number of read/write address difference is ranked up, the embodiment of the present invention is not specifically limited in this embodiment.

Optionally, sequence of the processor based on N number of read/write address difference, the operation that the first read/write address difference is obtained from N number of read/write address difference can be with are as follows: when the sequence of N number of read/write address difference is sorts to obtain according to the ascending sequence of N number of default time delay, the read/write address that processor obtains first jump from N number of read/write address difference is poor, and it is poor that the read/write address difference that will acquire is determined as the first read/write address；When the sequence of N number of read/write address difference is to sort to obtain according to the descending sequence of N number of default time delay, the read/write address that processor determines that the last one is jumped from N number of read/write address difference is poor, and the read-write that the last one is jumped by this It is poor that the previous position read/write address difference of address difference is determined as the first read/write address.

In conjunction with the 4th kind of possible implementation of second aspect or the 5th kind of possible implementation of second aspect, in the 6th kind of possible implementation of above-mentioned second aspect, the processor is based on the N number of read/write address difference and interconnection delay, after determining decimal time delay, further includes:

The processor is based on first time delay, determines that the second time delay, second time delay are that can eliminate the metastable time delay of the sync logic；

The processor is based on first time delay and second time delay, is reset by the read address that the address comparison logic circuit generates the read address generation circuit.

In embodiments of the present invention, since the second time delay is that can eliminate the metastable time delay of sync logic, therefore, the first time delay and the second time delay are based in processor, during being reset by the read address that address comparison logic circuit generates read address generation circuit, metastable state can occur to avoid sync logic, stable indication signal is write to guarantee that sync logic can receive, and then guarantee the accuracy for the read/write address difference that address comparison logic circuit determines, guarantee the correct resetting for the read address that address comparison logic circuit generates read address generation circuit.

In conjunction with the 6th kind of possible implementation of second aspect, in the 7th kind of possible implementation of above-mentioned second aspect, the processor is based on first time delay, determines the second time delay, comprising:

When first time delay is less than or equal to signal stabilization time, the sum of first time delay and the first default time delay are determined as second time delay by the processor, the first default time delay is greater than the signal stabilization time and is less than third time delay, the signal stabilization time is the sum of settling time and retention time of first order trigger, the trigger being connect in multiple triggers that the first order trigger includes for the sync logic with the delay line, difference of the third time delay between clock cycle and the signal stabilization time, the clock cycle is the period of the read clock signal or the write clock signal, the read clock signal is equal with the period of the write clock signal, the signal stabilization time is less than the third time delay；Alternatively,

It is delayed when first time delay is greater than the signal stabilization time and is less than the third, first time delay is subtracted the second default time delay by the processor, second time delay is obtained, the second default time delay is greater than the signal stabilization time and is less than or equal to the decimal time delay；Alternatively,

It is delayed when first time delay is greater than or equal to the third, first time delay is subtracted the described first default time delay by the processor, obtains second time delay.

It should be noted that the first default time delay and the second default time delay can be preset, and the first default time delay can be any time delay in the range of being greater than signal stabilization time and being less than third time delay, second Default time delay can be not specifically limited in this embodiment for any time delay in the range of being greater than signal stabilization time and being less than or equal to decimal time delay, the embodiment of the present invention.

In addition, in embodiments of the present invention, the settling time and retention time that first order trigger is obtained in report can be routed from rear end, the sum of the settling time and retention time are determined as signal stabilization time, certainly, in practical application, it can also be otherwise obtained in signal stabilization time, the embodiment of the present invention is not specifically limited in this embodiment.

In embodiments of the present invention, when being sent to sync logic due to delaying when delay line will write indication signal delay first, the rising edge of read clock signal can be placed exactly in the trip point for writing indication signal, therefore, in order to eliminate the metastable state of sync logic, guarantee that sync logic receives to write indication signal more stable, it can be based on the first time delay, determine the second time delay, it is delayed when delay line can will write indication signal delay second in turn and is sent to sync logic, to guarantee the rising edge of read clock signal positioned at the stable point for writing indication signal, and then guarantees that sync logic can receive in the rising edge of read clock signal and stable write indication signal.

In conjunction with the 6th kind of possible implementation of second aspect or the 7th kind of possible implementation of second aspect, in the 8th kind of possible implementation of above-mentioned second aspect, the processor is based on first time delay and second time delay, it is reset by the read address that the address comparison logic circuit generates the read address generation circuit, comprising:

First time delay is sent to the address comparison logic circuit by the processor；

The time delay of the delay line is set second time delay by the processor；

When the delay line detect it is described write indication signal when, write indication signal by described the address comparison logic circuit be sent to by the sync logic；

When the address comparison logic circuit the rising edge of read clock signal detect it is described to write indication signal by first logic level jump be second logic level when, obtain the read address carried in the read address signal being currently received, read address based on the specified write address and acquisition, determine that the second read/write address is poor, the second read/write address difference is that the corresponding read/write address of second time delay is poor；

The delay when the address comparison logic circuit receives described first, poor based on the specified write address, first time delay, second read/write address difference and specified read/write address, the read address currently generated to the read address generation circuit is reset.

It should be noted that delay when Yanzhong does not include second when this is N number of default, does not include at this time that the corresponding read/write address of the second time delay is poor in N number of read/write address difference, it is therefore desirable to be determined to the corresponding read/write address difference of the second time delay；And be delayed when this is N number of default, Yanzhong includes second, in order to guarantee to determine The second read/write address difference accuracy, the corresponding read/write address difference of the second time delay can also be determined again.Therefore, whether Yanzhong includes the second time delay when no matter this is N number of default, it is delayed when processor sets second for the time delay of delay line, address comparison logic circuit can pass through delay line, sync logic and read address generation circuit, determine that the corresponding read/write address of the second time delay is poor, it that is to say, determine that the second read/write address is poor.

In embodiments of the present invention, it is delayed when processor sets second for delay line, when delay line, which detects, writes indication signal, is delayed when this can be write to indication signal delay second and be sent to address comparison logic circuit.Since the second time delay is that can eliminate the metastable time delay of sync logic, therefore, sync logic, which can receive, at this time stable writes indication signal, and this is write into indication signal and is sent to address comparison logic circuit, the accuracy that the second read/write address difference that indication signal determines is write to guarantee address comparison logic circuit based on this, guarantees the correct resetting for the read address that address comparison logic circuit can generate read address generation circuit based on the second read/write address difference.

In conjunction with the 6th kind of possible implementation of second aspect or the 7th kind of possible implementation of second aspect, in the 9th kind of possible implementation of above-mentioned second aspect, the processor is based on first time delay and second time delay, it is reset by the read address that address comparison logic circuit generates the read address generation circuit, comprising:

Delay when Yanzhong includes described second when described N number of default, the processor is from N number of read/write address difference, and the second read/write address of acquisition is poor, and the second read/write address difference is that the corresponding read/write address of second time delay is poor；

First time delay and the second read/write address difference are sent to the address comparison logic circuit by the processor；

The time delay of the delay line is set second time delay by the processor；

When the address comparison logic circuit the rising edge of the read clock signal detect it is described write indication signal and be second logic level and received first time delay and the second read/write address difference by first logic level jump when, poor based on the specified write address, first time delay, second read/write address difference and specified read/write address, the read address currently generated to the read address generation circuit is reset.

In embodiments of the present invention, it is delayed when Yanzhong includes second when this is N number of default, includes at this time that the corresponding read/write address of the second time delay is poor, and therefore, processor can be from N number of reading in N number of read/write address difference It is poor that the corresponding read/write address of the second time delay is directly acquired in write address difference, and the corresponding read/write address difference of second time delay is sent to address comparison logic circuit, address comparison logic circuit is not necessarily to determine the corresponding read/write address difference of the second time delay again by delay line, sync logic and read address generation circuit at this time, to save the process resource in asynchronous FIFO circuit.

In conjunction with the 8th kind of possible implementation of second aspect or the 9th kind of possible implementation of second aspect, in the tenth kind of possible implementation of above-mentioned second aspect, it is poor that the address comparison logic circuit is based on the specified write address, first time delay, second read/write address difference and specified read/write address, the read address currently generated to the read address generation circuit is reset, comprising:

When first time delay is less than or equal to signal stabilization time and the second read/write address difference adds 1 resulting address difference not equal to the specified read/write address difference, the number for the trigger that the address comparison logic circuit includes based on the specified write address and the sync logic, it determines the first address, and sets first address for the read address that the read address generation circuit currently generates；Alternatively,

When first time delay is greater than the signal stabilization time and the second read/write address difference is not equal to the specified read/write address difference, the number for the trigger that the address comparison logic circuit includes based on the specified write address and the sync logic, it determines the second address, and sets second address for the read address that the read address generation circuit currently generates.

In embodiments of the present invention, address comparison logic circuit can the different situations based on the first time delay and the second read/write address difference, determine the first address or the second address, and then it is based on first address or the second address, the read address currently generated to read address generation circuit is reset, to realize the correct resetting of the read address currently generated to read address generation circuit.

In conjunction with second aspect to second aspect the tenth kind of possible implementation in any possible implementation, in a kind of the tenth possible implementation of above-mentioned second aspect, the processor is based on the decimal time delay, determines the time delay of the asynchronous FIFO circuit, comprising:

The processor obtains integer time delay, and the integer time delay is the synchronization time delay introduced to the address difference between the read address that the random access storage device carries out the write address of write operation and carries out read operation；

The sum of the decimal time delay and the integer time delay are determined as the time delay of the asynchronous FIFO circuit by the processor.

Optionally, it is delayed when processor obtains integer, specified read/write address difference and the product of clock cycle can be determined as integer time delay, certainly, in practical application, processor can also obtain integer time delay otherwise, and the embodiment of the present invention is not specifically limited in this embodiment.

In embodiments of the present invention, since the time delay of asynchronous FIFO circuit under normal conditions includes integer time delay The sum of decimal time delay and integer time delay therefore can be determined as to the time delay of asynchronous FIFO circuit with decimal time delay, to realize the accurate determination to the time delay of the asynchronous FIFO circuit.

In conjunction with second aspect to second aspect a kind of the tenth possible implementation in any possible implementation, in the 12nd kind of possible implementation of above-mentioned second aspect, the method also includes:

When the processor receives reset setting instruction, third address is set by write address electrification reset value, the 4th address is set by read address electrification reset value, the third address is that specified read/write address is poor with the four address address difference, the write address electrification reset value is the initial write address that the write address generation circuit generates when powering on, and the read address electrification reset value is the initial read address that the read address generation circuit generates when powering on.

In embodiments of the present invention, third address is set by write address electrification reset value, the 4th address is set by read address electrification reset value, and third address is that specified read/write address is poor with four address address difference, asynchronous FIFO circuit can be guaranteed when powering on rigid start-up operation, it is that specified read/write address is poor to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation, to guarantee that the time delay of the asynchronous FIFO circuit in whole work process is all the same, guarantee the accuracy of the time delay of determining asynchronous FIFO circuit.

The beneficial effect of the technical scheme provided by the present invention is that: in embodiments of the present invention, asynchronous FIFO circuit includes writing clock generation circuit, reading clock generation circuit, write address generation circuit, read address generation circuit, random access storage device, delay line, sync logic, address comparison logic circuit and processor.Wherein, multiple read address signals of generation can be sent to address comparison logic circuit by read address generation circuit, the indication signal of writing of generation can be sent to delay line by write address generation circuit, due to including N number of default time delay in delay line, therefore, the delay line, which can will be write to delay when indication signal successively postpones N number of default, is sent to address comparison logic circuit by sync logic, address comparison logic circuit can be based on writing indication signal and read address signal, determine that N number of read/write address is poor correspondingly with N number of default time delay, and N number of read/write address difference is sent to processor, later, processor can be based on N number of read/write address difference and interconnection delay, determine decimal time delay, and it is based on the decimal time delay, determine the time delay of asynchronous FIFO circuit, to realize to asynchronous FIFO The accurate determination of the time delay of circuit.

It should be understood that above general description and following detailed description be only it is exemplary and explanatory, the present invention can not be limited.

Detailed description of the invention

To describe the technical solutions in the embodiments of the present invention more clearly, the accompanying drawings required for describing the embodiments of the present invention are briefly described below.

Fig. 1 is a kind of structural schematic diagram for asynchronous FIFO circuit that the relevant technologies provide；

Fig. 2 is a kind of structural schematic diagram of asynchronous FIFO circuit provided in an embodiment of the present invention；

Fig. 3 is the structural schematic diagram of another asynchronous FIFO circuit provided in an embodiment of the present invention；

Fig. 4 is the structural schematic diagram of another asynchronous FIFO circuit provided in an embodiment of the present invention；

Fig. 5 is a kind of structural schematic diagram of delay line provided in an embodiment of the present invention；

Fig. 6 is a kind of structural schematic diagram of sync logic provided in an embodiment of the present invention；

Fig. 7 is the flow chart that a kind of time delay provided in an embodiment of the present invention determines method；

Fig. 8 be it is provided in an embodiment of the present invention the first write the schematic diagram of indication signal；

Fig. 9 (a) is the second provided in an embodiment of the present invention schematic diagram for writing indication signal；

Fig. 9 (b) is that provided in an embodiment of the present invention the third writes the schematic diagram of indication signal；

Figure 10 (a) is the 4th kind provided in an embodiment of the present invention schematic diagram for writing indication signal；

Figure 10 (b) is the 5th kind provided in an embodiment of the present invention schematic diagram for writing indication signal；

Figure 10 (c) is the 6th kind provided in an embodiment of the present invention schematic diagram for writing indication signal.

Appended drawing reference:

The relevant technologies:

1: writing clock generation circuit；1a: the output end of clock generation circuit is write；

2: reading clock generation circuit；2a: the output end of clock generation circuit is read；

3: write address generation circuit；3a: the input terminal of write address generation circuit；3b: the first output end of write address generation circuit；3c: the second output terminal of write address generation circuit；

4: read address generation circuit；4a: the input terminal of read address generation circuit；4b: the output end of read address generation circuit；4c: the set end of read address generation circuit；

5: random access storage device；5a: the first input end of random access storage device；5b: the second input terminal of random access storage device；

6: sync logic；6a: the first input end of sync logic；6b: the output end of sync logic；6c: the second input terminal of sync logic；

7: address comparison logic circuit；7a: the first input end of address comparison logic circuit；7b: the second input terminal of address comparison logic circuit, 7c: the third input terminal of address comparison logic circuit；7d: the output end of address comparison logic circuit.

The embodiment of the present invention:

8: writing clock generation circuit；8a: the output end of clock generation circuit is write；

9: reading clock generation circuit；9a: the output end of clock generation circuit is read；

10: write address generation circuit；10a: the input terminal of write address generation circuit；10b: the first output end of write address generation circuit；10c: the second output terminal of write address generation circuit；10d: the reset terminal of write address generation circuit；

11: read address generation circuit；11a: the input terminal of read address generation circuit；11b: the output end of read address generation circuit；11c: the set end of read address generation circuit；11d: the reset terminal of read address generation circuit；

12: random access storage device；12a: the first input end of random access storage device；12b: the second input terminal of random access storage device；

13: delay line；13a: the first input end of delay line；13b: the output end of delay line；13c: the second input terminal of delay line；

14: sync logic；14a: the first input end of sync logic；14b: the output end of sync logic；14c: the second input terminal of sync logic；

15: address comparison logic circuit；15a: the first input end of address comparison logic circuit；15b: the second input terminal of address comparison logic circuit, 15c: the third input terminal of address comparison logic circuit；15d: the first output end of address comparison logic circuit；15e: the second output terminal of address comparison logic circuit；

16: processor；16a: the first output end of processor；16b: the input terminal of processor；16c: the second output terminal of processor；16d: the third output end of processor 16；

D: delay section；T: tap；P: trigger.

Specific embodiment

Below in conjunction with attached drawing, embodiment of the present invention is described further in detail.

Fig. 2 is a kind of structural schematic diagram of asynchronous FIFO circuit provided in an embodiment of the present invention.Referring to fig. 2, which includes: to write clock generation circuit 8, read clock generation circuit 9, write address generation circuit 10, read address generation circuit 11, random access storage device 12, delay line 13, sync logic 14, address comparison logic circuit 15 and processor 16；

The output end 8a for writing clock generation circuit 8 is connect with the input terminal 10a of write address generation circuit 10, the first output end 10b of write address generation circuit 10 and the first input end 12a of random access storage device 12 Connection, the second output terminal 10c of write address generation circuit 10 is connect with the first input end 13a of delay line 13, second input terminal 13c of delay line 13 is connect with the first output end 16a of processor 16, the output end 13b of delay line 13 is connect with the first input end 14a of sync logic 14, the output end 14b of sync logic 14 is connect with the first input end 15a of address comparison logic circuit 15, second input terminal 14c of sync logic 14 and the second input terminal 15b of address comparison logic circuit 15 are connect with the output end 9a for reading clock generation circuit 9 respectively；The output end 9a for reading clock generation circuit 9 is also connect with the input terminal 11a of read address generation circuit 11, the output end 11b of read address generation circuit 11 is connect with the second input terminal 12b of random access storage device 12, the output end 11b of read address generation circuit 11 is also connect with the third input terminal 15c of address comparison logic circuit 15, and the first output end 15d of address comparison logic circuit 15 is connect with the input terminal 16b of processor 16.

Wherein, when carrying out write operation to random access storage device 12 by the asynchronous FIFO circuit, write address generation circuit 10 can be sent to for the write clock signal of generation by writing clock generation circuit 8, write address generation circuit 10 can generate writing address signal in the rising edge of the write clock signal, write address is carried in the writing address signal, the communication equipment where the asynchronous FIFO circuit data to be transmitted can be written in random access storage device 12 on position corresponding to the write address at this time.Simultaneously, when carrying out read operation to random access storage device 12 by the asynchronous FIFO circuit, read address generation circuit 11 can be sent to for the read clock signal of generation by reading clock generation circuit 9, read address generation circuit 11 can generate read address signal in the rising edge of the read clock signal, read address is carried in the read address signal, the communication equipment where the asynchronous FIFO circuit can read the data stored on position corresponding to the read address from random access storage device 12 at this time.

Wherein, clock generation circuit 8 is write for generating write clock signal；Clock generation circuit 9 is read for generating read clock signal；Write address generation circuit 10 is for generating multiple writing address signals and writing indication signal, write address is carried in each writing address signal, it is that at least two write addresses generated based on write address generation circuit 10 are generated that this, which writes indication signal, and it is the second logic level by the jump of the first logic level that this, which writes indication signal when write address generation circuit 10 generates specified write address, wherein, multiple writing address signals of generation can be sent to random access storage device 12 by the first output end 10b by write address generation circuit 10, and the indication signal of writing of generation can be sent to by delay line 13 by second output terminal 10c；Read address generation circuit 11 is for generating multiple read address signals, read address is carried in each read address signal, wherein, multiple read address signals of generation can be sent to random access storage device 12 and address comparison logic circuit 15 by output end 11b by read address generation circuit 11；Random access storage device 12 is for storing data；Delay line 13 will write finger after delay for postponing to the indication signal of writing of input delay line circuit 13 Show that signal is sent to sync logic 14；Sync logic 14 is used to write indication signal in the rising edge reception for reading the read clock signal that clock generation circuit 9 generates, and the received indication signal of writing of institute is sent to address comparison logic circuit 15；Address comparison logic circuit 15 is used to be based on to write indication signal and read address signal, determines that read/write address is poor, which is currently to the address difference between the read address that random access storage device 12 carries out the write address of write operation and carries out read operation；Processor 16 is used to pass through read address generation circuit 11, delay line 13, sync logic 14 and address comparison logic circuit 15, based on writing indication signal, multiple read address signals and read clock signal, it is poor to obtain N number of read/write address, wherein, N number of default time delay in N number of read/write address difference and delay line 13 corresponds, which is the natural number greater than 1；And processor 16 is also used to based on N number of read/write address difference and interconnection delay, determine decimal time delay, and it is based on decimal time delay, determine the time delay of asynchronous FIFO circuit, wherein, the introduced time delay of wiring of the interconnection delay between write address generation circuit and sync logic, the introduced time delay of phase difference of the decimal time delay between read clock signal and write clock signal.

It should be noted that specified write address and N number of default time delay can be preset, the embodiment of the present invention is not specifically limited in this embodiment.

In addition, the state of the state of the first logic level and the second logic level is on the contrary, such as when the first logic level is 0, the second logic level is 1；When the first logic level is 1, the second logic level is 0, and the embodiment of the present invention is not specifically limited in this embodiment.

Furthermore write address generation circuit 10 can also be when the write address for detecting generation be any write address except specified write address, and it is the first logic level that this, which is write indication signal from the jump of the second logic level, and the embodiment of the present invention is not specifically limited in this embodiment.

It should be noted that, write clock generation circuit 8, read clock generation circuit 9, write address generation circuit 10, read address generation circuit 11, random access storage device 12, delay line 13 and sync logic 14 in practical applications can in the form of hardware or software form is realized, such as, it writes clock generation circuit 8 and reads clock generation circuit 9 and realized by oscillator, further, it can also be realized by oscillator combination phaselocked loop, write address generation circuit 10 and read address generation circuit 11 can be by hardware programming devices, such as FPGA (Field Programmable Gate Array, field programmable gate array) Lai Shixian, sync logic 14 can be realized by trigger, address comparison logic circuit 15 and processor 16 Function in practical applications can be with software or formal implementation of hardware, for example by hardware encoding device realizes that the embodiment of the present invention is not specifically limited in this embodiment.Optionally, when the above circuit and processor are by software realization, can integrate in a hardware entities, can also each self-dispersing or part be distributed in multiple hardware entities in combination, herein not limit.For example, the function of address above mentioned CL Compare Logic circuit 15 can also be by the processor 16 realize, realize alternatively, the function of processor 16 is embedded in the address comparison logic circuit 15, alternatively, address comparison logic circuit 15 and processor 16 are not integrated, not limit herein.

Referring to Fig. 3, in the asynchronous FIFO circuit, the second output terminal 15e of address comparison logic circuit 15 is connect with the set end 11c of read address generation circuit 11.

Wherein, address comparison logic circuit 15 is used for when detecting that writing indication signal jumps to the second logic level by the first logic level, and the read address currently generated to read address generation circuit 11 is reset.

Referring to fig. 4, in the asynchronous FIFO circuit, the second output terminal 16c of processor 16 is connect with the reset terminal 10d of write address generation circuit 10, and the third output end 16d of processor 16 is connect with the reset terminal 11d of read address generation circuit 11.

Wherein, processor 16 is used for when receiving reset setting instruction, third address is set by write address electrification reset value, the 4th address is set by read address electrification reset value, third address is that specified read/write address is poor with four address address difference, write address electrification reset value is the initial write address that write address generation circuit 10 generates when powering on, and read address electrification reset value is the initial read address that read address generation circuit 11 generates when powering on.

In addition, specified read/write address difference can be preset, such as this, which specifies read/write address difference, to be 7,8, and the embodiment of the present invention is not specifically limited in this embodiment.

Furthermore, in embodiments of the present invention, third address is set by write address electrification reset value, the 4th address is set by read address electrification reset value, and third address is that specified read/write address is poor with four address address difference, asynchronous FIFO circuit can be guaranteed when powering on rigid start-up operation, it is that specified read/write address is poor to the address difference between the read address that random access storage device 12 carries out the write address of write operation and carries out read operation, to guarantee that the time delay of the asynchronous FIFO circuit in whole work process is all the same.

Referring to Fig. 5, delay line 13 includes: N-1 delay section D and N number of tap T, N are the natural number greater than 1；

N-1 delay section is connected in series, one end of i-th of delay section is connect with i-th of tap in N number of tap in N-1 delay section, the other end of i-th of delay section is connect with i+1 tap in N number of tap in N-1 delay section, and i is greater than or equal to 1 and is less than or equal to N-1.

Wherein, delay line 13 be used for when detect write indication signal when, indication signal will be write postpone to delay when i-th of tap is corresponding default in N number of tap and address comparison logic circuit 15 is sent to by sync logic 14, N number of tap and N number of default time delay correspond；Address comparison logic circuit 15 For when the rising edge in read clock signal detect write indication signal by the first logic level jump be the second logic level when, obtain the read address carried in the read address signal being currently received, and the read address based on specified write address and acquisition, it determines that the corresponding read/write address of i-th of tap is poor, the corresponding read/write address difference of i-th of tap is sent to processor 16；Processor 16 is used for when receiving the corresponding read/write address difference of i-th of tap, i=i+1 is enabled, indication signal will be write again through delay line 13 postpones to delay when i-th of tap is corresponding default in N number of tap address comparison logic circuit 15 is sent to by sync logic 14.

Furthermore, processor 16 can be configured the currently used tap of delay line 13, it that is to say, processor 16 can default time delay currently used to delay line 13 be configured, to guarantee that delay line 13 can successively traverse N number of tap, indication signal will be write and successively postpone N number of default time delay.

It should be noted that, above-mentioned circulate operation can be executed by the cooperation of delay line 13, sync logic 14, address comparison logic circuit 15 and processor 16 in the embodiment of the present invention, to guarantee that the corresponding read/write address of available tap each into N number of tap is poor, it that is to say, it is poor each to preset the corresponding read/write address of time delay for Yanzhong when can guarantee to get N number of default, and then can guarantee the accuracy being delayed when subsequent processor 16 determines decimal based on N number of read/write address difference.

Referring to Fig. 6, sync logic 14 includes multiple concatenated trigger P, and each trigger is used to write indication signal in the rising edge reception for reading the read clock signal that clock generation circuit 9 generates in multiple concatenated trigger P.

Wherein, the first order trigger in multiple triggers that sync logic 14 includes writes indication signal in the rising edge reception of read clock signal, and this is write into indication signal and is sent to second level trigger, second level trigger receives this in the rising edge of read clock signal and writes indication signal, and this is write into indication signal and is sent to third level trigger, so, until this, which is write indication signal, is sent to the m grades of triggers that sync logic 14 includes, m grades of triggers receive this in the rising edge of read clock signal and write indication signal, and this is write into indication signal and is sent to address comparison logic circuit 15, m is natural number, and m is more than or equal to 2.

It should be noted that first order trigger to the m grades of triggers in multiple trigger are according to this The series sequence determination of multiple triggers obtains, it that is to say, the trigger connecting with delay line 13 can be determined as first order trigger, the trigger after first order trigger is successively determined as m grades of second level trigger, third level trigger ... triggers.

In embodiments of the present invention, asynchronous FIFO circuit includes writing clock generation circuit, reading clock generation circuit, write address generation circuit, read address generation circuit, random access storage device, delay line, sync logic, address comparison logic circuit and processor.Wherein, multiple read address signals of generation can be sent to address comparison logic circuit by read address generation circuit, the indication signal of writing of generation can be sent to delay line by write address generation circuit, due to including N number of default time delay in delay line, therefore, the delay line, which can will be write to delay when indication signal successively postpones N number of default, is sent to address comparison logic circuit by sync logic, address comparison logic circuit can be based on writing indication signal and read address signal, determine that N number of read/write address is poor correspondingly with N number of default time delay, and N number of read/write address difference is sent to processor, later, processor can be based on N number of read/write address difference and interconnection delay, determine decimal time delay, and it is based on the decimal time delay, determine the time delay of asynchronous FIFO circuit, to realize to asynchronous FIFO The accurate determination of the time delay of circuit.

Fig. 7 is the flow chart that a kind of time delay provided in an embodiment of the present invention determines method, this method can be applied to above-mentioned Fig. 2-6 it is any shown in asynchronous FIFO circuit, it can be understood that, this method also can be applied to be different from Fig. 2-6 it is any shown in asynchronous FIFO circuit, when the lesser part of key component relevance that asynchronous FIFO circuit shown in Fig. 2-6 is any and this method are realized or connect is changed, this method is still applicable to the circuit after changing, such as, the set function of address comparison logic circuit and connection are by other modules such as processor come when realizing, this method should be still applicable in.Referring to Fig. 7, this method comprises:

Step 701: during carrying out read operation and write operation to random access storage device, multiple read address signals of generation are sent to address comparison logic circuit by read address generation circuit, the indication signal of writing of generation is sent to delay line by write address generation circuit, it is that at least two write addresses generated based on write address generation circuit are generated, and it is the second logic level by the jump of the first logic level that this, which writes indication signal when write address generation circuit generates specified write address, that this, which writes indication signal,.

Wherein, during carrying out read operation to random access storage device, when read address generation circuit detects a rising edge of read clock signal, generate a read address signal, read address is carried in the read address signal, it that is to say, read address generation circuit can generate a read address signal within each period of read clock signal.Meanwhile during carrying out write operation to random access storage device, write address generation circuit, which can produce, writes indication signal and multiple writing address signals, write address is carried in each writing address signal, and work as When write address generation circuit detects that the write address of generation is specified write address, it is the second logic level that this can be write to indication signal and jumped from the first logic level.

It should be noted that specified write address can be preset, such as this, which specifies write address, to be 7,8,9, and the embodiment of the present invention is not specifically limited in this embodiment.

It should be noted that random access storage device is for storing data；Read address generation circuit carries read address in each read address signal for generating multiple read address signals；Write address generation circuit is for generating multiple writing address signals and writing indication signal, write address is carried in each writing address signal, it is that at least two write addresses generated based on write address generation circuit are generated, and it is the second logic level by the jump of the first logic level that this, which writes indication signal when write address generation circuit generates specified write address, that this, which writes indication signal,；Address comparison logic circuit is used to be based on to write indication signal and read address signal, determines that read/write address is poor, which is currently to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation；Delay line is for postponing the indication signal of writing of input delay line circuit.

Step 702: processor passes through read address generation circuit, delay line, sync logic and address comparison logic circuit, indication signal, multiple read address signal and the read clock signal for reading clock generation circuit generation are write based on this, it is poor to obtain N number of read/write address, N number of default time delay in N number of read/write address difference and delay line corresponds, which is the natural number greater than 1.

It should be noted that N number of default time delay can be preset, the embodiment of the present invention is not specifically limited in this embodiment.In addition, preferably, due to the introduced time delay of phase difference of the decimal time delay between read clock signal and write clock signal, and less than one clock cycle of the decimal time delay, therefore, in order to guarantee subsequent to determine decimal time delay based on N number of default time delay, it can be 0 that the minimum of Yanzhong, which presets time delay, when this is N number of default, and the maximum preset time delay of Yanzhong can be greater than or equal to a clock cycle when this is N number of default.Wherein, the clock cycle is the period of read clock signal or write clock signal, and read clock signal is equal with the period of write clock signal.

Specifically, delay line includes N-1 delay section and N number of tap, and N number of tap and N number of default time delay correspond, processor by read address generation circuit, delay line, sync logic and Address comparison logic circuit writes indication signal, multiple read address signal and the read clock signal for reading clock generation circuit generation based on this, and the operation for obtaining N number of read/write address difference may include steps of (1)-(3):

(1), when delay line, which detects, writes indication signal, this is write to delay when i-th of tap is corresponding default in the N number of tap of indication signal delay, address comparison logic circuit is sent to by sync logic, i is greater than or equal to 1 and is less than or equal to N-1.

Wherein, delay line this is write that indication signal postpones to delay when i-th of tap is corresponding default in N number of tap can be with by the operation that sync logic is sent to address comparison logic circuit are as follows: this by i-th of tap in N number of tap is write indication signal and postpones to delay when i-th of tap is corresponding default by delay line is sent to sync logic；When sync logic, which receives this, writes indication signal, this is write after indication signal postponed for the first numerical value clock cycle and is sent to address comparison logic circuit.

It should be noted that the number that the first numerical value is the sync logic trigger that includes subtracts 1 resulting numerical value.

Since the number of the delay section in N number of tap between each tap and write address generation circuit is fixed, and each delay section can will input the delay of the delay section write indication signal and the time is fixed, so N number of tap and N number of default time delay correspond.Therefore, this can be write indication signal by i-th of tap in N number of tap and postpones to delay when i-th of tap is corresponding default by delay line is sent to sync logic.

Wherein, sync logic includes multiple concatenated triggers, when sync logic, which receives this, writes indication signal, this is write the operation of address comparison logic circuit is sent to after indication signal postponed for the first numerical value clock cycle can be with are as follows: the first order trigger in multiple triggers that sync logic includes receives this in the rising edge of read clock signal and writes indication signal, and this is write into indication signal and is sent to second level trigger, second level trigger receives this in the rising edge of read clock signal and writes indication signal, and this is write into indication signal and is sent to third level trigger, so, until this, which is write indication signal, is sent to the m grades of triggers that sync logic includes, m grades of triggers receive this in the rising edge of read clock signal and write indication signal, and this is write into indication signal and is sent to address comparison logic circuit, m is certainly So number, and m is more than or equal to 2.

It should be noted that, first order trigger to m grades of triggers in multiple trigger are obtained according to the series sequence determination of multiple trigger, it that is to say, the trigger connecting in multiple trigger with delay line can be determined as first order trigger, the trigger after first order trigger is successively determined as m grades of second level trigger, third level trigger ... triggers.

In the multiple triggers for including due to sync logic each trigger be read clock signal rising edge reception write indication signal, and this is write into indication signal and is sent to next trigger, therefore, next trigger is sent to by a trigger when this writes indication signal, and when being sent again by next trigger, this is write indication signal and is delayed by a clock cycle, and therefore, this can be write indication signal and postpone for the first numerical value clock cycle by sync logic.

It should be noted that, when sync logic, which receives this, writes indication signal, this is write and is sent to the operation of address comparison logic circuit after indication signal postponed for the first numerical value clock cycle and can also refer to the relevant technologies, this is no longer described in detail in the embodiment of the present invention.

(2), when address comparison logic circuit the rising edge of read clock signal detect this write indication signal by the first logic level jump be the second logic level when, obtain the read address carried in the read address signal being currently received, read address based on specified write address and acquisition, it determines that the corresponding read/write address of i-th of tap is poor, and the corresponding read/write address difference of i-th of tap is sent to processor.

Wherein, read address of the address comparison logic circuit based on specified write address and acquisition determines that the operation of the corresponding read/write address difference of i-th of tap can be with are as follows: address comparison logic circuit determines the address difference between specified write address and the read address of acquisition；The number for the trigger that sync logic includes is subtracted 1 by address comparison logic circuit, obtains the first numerical value；Determining address difference is added by address comparison logic circuit with the first numerical value, and it is poor to obtain the corresponding read/write address of i-th of tap.

It is to be jumped when write address generation circuit generates specified write address by the first logic level as the second logic level due to writing indication signal, and it is to be sent to address comparison logic circuit after being synchronized logic circuit delays the first numerical value clock cycle that this, which writes indication signal, therefore, address comparison logic circuit detect this write indication signal by the first logic level jump be the second logic level when, write address generation circuit produces the first numerical value write address after generating the specified write address again, so currently carrying out the address difference between the write address and specified write address of write operation to random access storage device is the first numerical value.Again since address comparison logic circuit is used to determine synchronization to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation, and the read address signal that address comparison logic circuit is currently received is transmitted directly to address comparison logic circuit, do not postponed, therefore, when address comparison logic circuit specifies based on this read address of write address and acquisition, when determining the corresponding read/write address difference of i-th of tap, need by between the specified write address and the read address of acquisition address difference and the first numerical value be added.

Such as, address comparison logic circuit determines that the address difference between the specified write address and the read address of acquisition is 6, the number for the trigger that sync logic includes is 3, then the number 3 for the trigger that sync logic includes is subtracted 1, obtaining the first numerical value is 2, determining address difference 6 is added with the first numerical value 2 Obtaining the corresponding read/write address difference of i-th of tap is 8.

Wherein, address comparison logic circuit determines that the operation of the address difference between the specified write address and the read address of acquisition can be with are as follows: when this specifies write address to be greater than the read address obtained, the read address for specifying write address to subtract acquisition is obtained into second value, second value is determined as the address difference between the specified write address and the read address of acquisition；When this specifies write address to be less than the read address obtained, the read address that will acquire subtracts the specified write address and obtains third value, the address total number that random access storage device includes is subtracted into third value, the 4th numerical value is obtained, the 4th numerical value is determined as the address difference between the specified write address and the read address of acquisition；When this specifies write address to be equal to the read address obtained, if the specified write address to write number identical as the reading number of the read address of acquisition, then the address difference between write address and the read address of acquisition is specified to be determined as 0 this, if the reading number of the read address for writing number and acquisition of the specified write address is not identical, the address total number that random access storage device includes is determined as the address difference between the specified write address and the read address of acquisition.Wherein, the number of writing of the specified write address is the number that the specified write address is written into data, and the reading number of the read address of acquisition is the read address of acquisition by the number of reading data.

Wherein, the reading number of address can be marked on each address in multiple addresses that random access storage device includes and writes number, it is the number that the address is written into data that this, which writes number, which is the address by the number of reading data, and the embodiment of the present invention is not specifically limited in this embodiment.

For example, the specified write address is 8, the read address of acquisition is 7, since 8 are greater than 7, then specifies write address 8 to subtract the read address 7 of acquisition this, obtaining second value is 1, and second value 1 is determined as the address difference between the specified write address and the read address of acquisition.

Again for example, the specified write address is 2, the read address of acquisition is 7, since 2 less than 7, then the read address that will acquire subtracts the specified write address, and obtaining third value is 5, assuming that the address total number that random access storage device includes is 10, the address total number 10 that random access storage device includes then is subtracted into third value 5, obtaining the 4th numerical value is 5, and the 4th numerical value 5 is determined as the address difference between the specified write address and the read address of acquisition.

In another example, the specified write address is 7, the read address of acquisition is 7, since this specifies write address to be equal to the read address obtained, it can then determine the reading number of the read address for writing number and acquisition of the specified write address, assuming that the number of writing of the specified write address is 2, the reading number of the read address of acquisition is 1, determine that the reading number of the read address for writing number and acquisition of the specified write address is not identical, assuming that the address total number that random access storage device includes is 10, the address difference that the address total number 10 that random access storage device includes can be then determined as between the specified write address and the read address of acquisition.

It should be noted that address comparison logic circuit determines between the specified write address and the read address of acquisition The operation of address difference can also refer to the relevant technologies, this is no longer described in detail in the embodiment of the present invention.

(3), when processor receives the corresponding read/write address difference of i-th of tap, i=i+1 is enabled, this is write into indication signal in return step (1) and postpones to delay the step of being sent to address comparison logic circuit by sync logic when i-th of tap is corresponding default in N number of tap.

It should be noted that, pass through circulate operation in the embodiment of the present invention, it is poor that the corresponding read/write address of each tap in N number of tap can be guaranteed to get, it that is to say, each the default corresponding read/write address of time delay is poor for Yanzhong when can guarantee to get N number of default, thereby may be ensured that the accuracy being delayed when subsequent processor determines decimal based on N number of read/write address difference.

Step 703: processor is based on N number of read/write address difference and interconnection delay, determine decimal time delay, the introduced time delay of wiring of the interconnection delay between write address generation circuit and sync logic, the introduced time delay of phase difference of the decimal time delay between read clock signal and write clock signal.

Further, processor is based on N number of read/write address difference and interconnection delay, before determining decimal time delay, processor can also be routed from the rear end of storage obtains the wiring between write address generation circuit and sync logic introduced maximum delay and minimal time delay in report, and the average value of maximum delay and minimal time delay is determined as interconnection delay, rear end wiring report is for recording the introduced time delay of all wirings that asynchronous FIFO circuit includes.

Such as, the introduced maximum delay of wiring of the processor from the wiring report of rear end between the write address generation circuit obtained and sync logic is 0.6ns (nanosecond), minimal time delay is 0.2ns, then the average value 0.4ns of maximum delay 0.6ns and minimal time delay 0.2ns can be determined as interconnection delay by processor.

It should be noted that, since the position of write address generation circuit and sync logic can impact interconnection delay, therefore, the embodiment of the present invention can be when carrying out the wiring of the asynchronous FIFO circuit, constrain the position of write address generation circuit and sync logic as close possible to, so that the variation for being routed introduced maximum delay and minimal time delay between write address generation circuit and sync logic is minimum, so that the interconnection delay determined based on the maximum delay and the minimal time delay is small as far as possible and stablizes, to guarantee the accuracy being delayed when processor determines decimal based on the interconnection delay.

Specifically, processor is based on N number of read/write address difference and interconnection delay, delay when determining decimal, processor can be poor based on N number of read/write address, and Yanzhong determines the first time delay when N number of default from this, and the sum of the first time delay and interconnection delay are determined as decimal time delay.

Wherein, processor is based on that N number of read/write address is poor, determines that the operation of the first time delay can be in Yanzhong when N number of default from this are as follows: processor is based on N number of default time delay, is ranked up to N number of read/write address difference, obtains the sequence of N number of read/write address difference；Sequence of the processor based on N number of read/write address difference, Obtain that the first read/write address is poor from N number of read/write address difference, the first read/write address difference is to obtain based on the read/write address difference determination jumped in N number of read/write address difference, and the read/write address difference of the jump is that the read/write address different from previous position read/write address difference is poor；The corresponding default time delay of first read/write address difference is determined as the first time delay by processor.

It should be noted that, processor is based on N number of default time delay, when being ranked up to N number of read/write address difference, sequence that can be ascending according to N number of default time delay, N number of read/write address difference is ranked up, it is of course also possible to the sequence descending according to N number of default time delay, N number of read/write address difference is ranked up, the embodiment of the present invention is not specifically limited in this embodiment.

Such as, N number of default time delay is 5ns, 1ns, 2ns, 4ns, 3ns, N number of read/write address difference is 6,7,7,6,7, wherein, the corresponding read/write address difference of 5ns is 6, the corresponding read/write address difference of 1ns is 7, the corresponding read/write address difference of 2ns is 7, the corresponding read/write address difference of 4ns is 6, the corresponding read/write address difference of 3ns is 7, the then sequence that processor can be ascending according to N number of default time delay, N number of read/write address difference is ranked up, the sequence for obtaining N number of read/write address difference is 7,7,7,6,6.

Again for example, N number of default time delay is 5ns, 1ns, 2ns, 4ns, 3ns, N number of read/write address difference is 6,7,7,6,7, wherein, the corresponding read/write address difference of 5ns is 6, the corresponding read/write address difference of 1ns is 7, the corresponding read/write address difference of 2ns is 7, the corresponding read/write address difference of 4ns is 6, the corresponding read/write address difference of 3ns is 7, the then sequence that processor can be descending according to N number of default time delay, N number of read/write address difference is ranked up, the sequence for obtaining N number of read/write address difference is 6,6,7,7,7.

Wherein, sequence of the processor based on N number of read/write address difference, the operation that the first read/write address difference is obtained from N number of read/write address difference can be with are as follows: when the sequence of N number of read/write address difference is sorts to obtain according to the ascending sequence of N number of default time delay, the read/write address that processor obtains first jump from N number of read/write address difference is poor, and it is poor that the read/write address difference that will acquire is determined as the first read/write address；When the sequence of N number of read/write address difference is to sort to obtain according to the descending sequence of N number of default time delay, the read/write address that processor determines that the last one is jumped from N number of read/write address difference is poor, and to be determined as the first read/write address poor for previous position read/write address difference of the last one read/write address difference jumped by this.

Such as, the sequence of N number of read/write address difference is 7,7,7,6,6, and the sequence of N number of read/write address difference is to sort to obtain according to the ascending sequence of N number of default time delay, it is 6 that then processor, which can obtain the read/write address difference of first jump from N number of read/write address difference, and it is poor to be determined as the first read/write address for 6.

Again for example, the sequence of N number of read/write address difference is 6,6,7,7,7, and the sequence of N number of read/write address difference is to sort to obtain according to the descending sequence of N number of default time delay, then processor can determine that the read/write address difference that the last one is jumped is 7 from N number of read/write address difference, and the last one is jumped It is poor that the previous position read/write address poor 6 of read/write address difference is determined as the first read/write address.

Further, in conjunction with specific example, it is poor that N number of read/write address is based on to processor, from it is N number of default when Yanzhong determine the first time delay, and the principle that the sum of the first time delay and interconnection delay are determined as decimal time delay is illustrated:

Fig. 8 is a kind of delay line provided in an embodiment of the present invention to the schematic diagram writing indication signal and being postponed.With reference to Fig. 8, the introduced time delay of phase difference of the decimal time delay between write clock signal and read clock signal；Indication signal is write in the generation of write address generation circuit, and writing indication signal and being jumped in the rising edge a of write clock signal by the first logic level 0 is the second logic level 1；N number of default time delay in delay line is default time delay 1, default time delay 2 ... presets time delay f-1, presets the default time delay n of time delay f ..., and default 1 < of time delay presets 2 < ... < of time delay and presets the default time delay n of the default time delay f < ... < of time delay f-1 <.

As shown in figure 8, the rising edge c of read clock signal is respectively positioned on the second logic level 1 for writing indication signal when being sent to sync logic after postponing default time delay 1 respectively when delay line will write indication signal, presetting the default time delay f-1 of time delay 2 ....And when being sent to sync logic after delay line will write the default time delay f of indication signal delay, the rising edge c of read clock signal, which is placed exactly in, writes the trip point that the first logic level 0 of indication signal is jumped to the second logic level 1.

Since the wiring between write address generation circuit and sync logic can introduce interconnection delay, therefore, when the trip point that the rising edge c of read clock signal is jumped positioned at the first logic level 0 for writing indication signal to the second logic level 1, it writes indication signal and is not only delayed by the default time delay f of line circuit delay, also by the interconnection delay of the wiring delay between write address generation circuit and sync logic.As shown in Figure 8, when writing indication signal and being sent to delay line by write address generation circuit, write the rising edge a that the trip point that the first logic level 0 of indication signal is jumped to the second logic level 1 is in write clock signal, and after writing indication signal and being delayed by default time delay f and interconnection delay, the rising edge c that the trip point that the first logic level 0 of indication signal is jumped to the second logic level 1 is in read clock signal is write.Since decimal time delay is introduced by the phase difference between write clock signal and read clock signal, it that is to say, decimal time delay is therefore the sum of default time delay f and interconnection delay can be determined as decimal time delay by the time delay in Fig. 8 between the rising edge a of write clock signal and the rising edge c of read clock signal.

When due to being sent to sync logic after postponing default time delay 1 when delay line will write indication signal, presetting the default time delay f-1 of time delay 2 ..., the rising edge c of read clock signal is in the second logic level 1 for writing indication signal, and since sync logic is only received in the rising edge of read clock signal to indication signal is write, therefore, as shown in Fig. 9 (a), when being sent to sync logic after delay line will write the default time delay 1 of indication signal delay, the default time delay f-1 of default time delay 2 ..., sync logic can Detect that writing indication signal by the jump of the first logic level 0 is the second logic level 1 with the rising edge c in read clock signal.Assuming that sync logic includes three triggers, it that is to say that sync logic can will write indication signal and postpone two clock cycle, then address comparison logic circuit can detect that writing indication signal by the jump of the first logic level 0 is the second logic level 1 in the rising edge e of read clock signal at this time, and the read address that address comparison logic circuit obtains is the read address received in the rising edge e of read clock signal.Since read/write address difference is address comparison logic circuit based on specified write address and is detecting that write indication signal is determined to obtain by the jump of the first logic level for the read address obtained when the second logic level, therefore, default time delay 1, the default corresponding read/write address difference of time delay f-1 of default time delay 2 ... are equal, such as, in corresponding relationship between default time delay as shown in table 1 below and read/write address difference, time delay 1 is preset, the default corresponding read/write address difference of time delay f of default time delay 2 ... is E.

Due to when delay line, which will write indication signal, to postpone to be sent to sync logic after default time delay f, the rising edge c of read clock signal, which is exactly in, writes the trip point that the first logic level 0 of indication signal is jumped to the second logic level 1, rising edge d after the rising edge c of read clock signal is in the second logic level 1 for writing indication signal, and since sync logic is only received in the rising edge of read clock signal to indication signal is write, therefore, as shown in Fig. 9 (b), when being sent to sync logic after delay line will write the default time delay f of indication signal delay, sync logic can detect that writing indication signal by the jump of the first logic level 0 is the second logic level 1 in the rising edge d of read clock signal.Assuming that sync logic includes three triggers, it that is to say that sync logic can will write indication signal and postpone two clock cycle, then address comparison logic circuit can detect that writing indication signal by the jump of the first logic level 0 is the second logic level 1 in the rising edge f after the rising edge e of read clock signal at this time, and the read address that address comparison logic circuit obtains is the read address received in the rising edge f of read clock signal.And since the address difference between read address of the read address generation circuit in the rising edge f generation of read clock signal and the read address of the rising edge e generation in read clock signal is 1, therefore, the default corresponding read/write address difference of time delay f, which can jump, presets the resulting address difference of any default corresponding address subtractive 1 of time delay in time delay f-1 for default time delay 1, default time delay 2 ..., such as, in corresponding relationship between default time delay as shown in table 1 below and read/write address difference, the corresponding read/write address difference jump of pre-set delay f is E-1.

Table 1

It should be noted that in embodiments of the present invention, being only illustrated for presetting the corresponding relationship between time delay and read/write address difference shown in above-mentioned table 1, above-mentioned table 1 does not constitute the embodiment of the present invention and limits.

Therefore, when the sequence of N number of read/write address difference is to sort to obtain according to the ascending sequence of N number of default time delay, default time delay f is the corresponding default time delay of read/write address difference of first jump in N number of read/write address difference, be that is to say, presetting time delay f is the first time delay.

And when the sequence of N number of read/write address difference is to sort to obtain according to the descending sequence of N number of default time delay, the previous position read/write address difference of the read/write address difference of the last one jump is identical as the read/write address difference of above-mentioned first jump in N number of read/write address difference.Therefore, when the sequence of N number of read/write address difference is to sort to obtain according to the descending sequence of N number of default time delay, default time delay f is the corresponding default time delay of previous position read/write address difference of the read/write address difference of the last one jump in N number of read/write address difference, it that is to say, presetting time delay f is the first time delay.

Therefore, processor is based on N number of read/write address difference and interconnection delay, and delay when determining decimal can be poor based on N number of read/write address, and Yanzhong determines the first time delay when N number of default from this, and the sum of the first time delay and interconnection delay are determined as decimal time delay.

Further, processor is based on N number of read/write address difference and interconnection delay, and after determining decimal time delay, processor is also based on the first time delay, determines that the second time delay, the second time delay are that can eliminate the metastable time delay of sync logic；Processor is based on the first time delay and the second time delay, is reset by the read address that address comparison logic circuit generates read address generation circuit.

Wherein, processor is based on the first time delay, determine that the operation of the second time delay can be with are as follows: when the first time delay is less than or equal to signal stabilization time, the sum of first time delay and the first default time delay are determined as the second time delay, first default time delay is greater than signal stabilization time and is less than third time delay, signal stabilization time is the sum of settling time and retention time of first order trigger, the trigger being connect in multiple triggers that first order trigger includes for sync logic with delay line, difference of the third time delay between clock cycle and signal stabilization time, signal stabilization time is less than third time delay；Alternatively, being delayed when the first time delay is greater than signal stabilization time and is less than third, the first time delay is subtracted into the second default time delay, obtains the second time delay, the second default time delay is greater than signal stabilization time and is less than or equal to decimal time delay；Alternatively, being delayed when the first time delay is greater than or equal to third, the first time delay is subtracted into the first default time delay, obtains the second time delay.

It should be noted that, first default time delay and the second default time delay can be preset, and first default time delay can for be greater than signal stabilization time and be less than third time delay in the range of any time delay, the second default time delay can for be greater than signal stabilization time and be less than or equal to decimal time delay in the range of any Time delay, the embodiment of the present invention are not specifically limited in this embodiment.

Due to the first order trigger in sync logic be read clock signal rising edge receive delay line send write indication signal, therefore, stable indication signal is write to guarantee that first order trigger can be received in the rising edge of read clock signal, this write indication signal should the rising edge of read clock signal arrival before the first specified time in stablize it is constant, and stablize within the second specified time after the arrival of the rising edge of the read clock signal constant, what otherwise first order trigger received write indication signal can be unstable, cause sync logic that metastable state occurs.

It should be noted that the first specified time can be greater than or equal to the settling time of first order trigger, the second specified time can be greater than or equal to the retention time of first order trigger, and the embodiment of the present invention is not specifically limited in this embodiment.

When being sent to sync logic due to delaying when delay line will write indication signal delay first, the rising edge of read clock signal can be placed exactly in the trip point for writing indication signal, therefore, in order to eliminate the metastable state of sync logic, guarantee that sync logic receives to write indication signal more stable, it can be based on the first time delay, determine the second time delay, it is delayed when delay line can will write indication signal delay second in turn and is sent to sync logic, to guarantee the rising edge of read clock signal positioned at the stable point for writing indication signal, and then guarantees that sync logic can receive in the rising edge of read clock signal and stable write indication signal.

As shown in Figure 10 (a), signal stabilization time is t, when the first time delay is less than or equal to signal stabilization time, the sum of first time delay and the first default time delay can be determined as the second time delay, at this time, delay line will be delayed when being sent to sync logic when will write indication signal delay second, the rising edge c of read clock signal is placed exactly in the stability region A for writing indication signal, to guarantee sync logic the rising edge of read clock signal can receive it is stable write indication signal, avoid metastable generation.

As shown in Figure 10 (b), signal stabilization time is t, it is delayed when the first time delay is greater than signal stabilization time and is less than third, first time delay can be subtracted to the second default time delay, obtain the second time delay, at this time, delay line will be delayed when being sent to sync logic when will write indication signal delay second, the rising edge c of read clock signal is placed exactly in the stability region B for writing indication signal, to guarantee sync logic the rising edge of read clock signal can receive it is stable write indication signal, avoid metastable generation.

As shown in Figure 10 (c), signal stabilization time t is delayed when the first time delay is greater than or equal to third, First time delay can be subtracted to the first default time delay, obtain the second time delay, at this time, delay line will be delayed when being sent to sync logic when will write indication signal delay second, the rising edge c of read clock signal is placed exactly in the stability region B for writing indication signal, to guarantee sync logic the rising edge of read clock signal can receive it is stable write indication signal, avoid metastable generation.

Wherein, processor is based on the first time delay and the second time delay, may include the following two kinds mode by the operation that the read address that address comparison logic circuit generates read address generation circuit is reset:

First way: the first time delay is sent to address comparison logic circuit by processor, and sets the second time delay for the time delay of delay line；When delay line, which detects, writes indication signal, this is write into indication signal, address comparison logic circuit is sent to by sync logic；When address comparison logic circuit the rising edge of read clock signal detect this write indication signal by the first logic level jump be the second logic level when, obtain the read address carried in the read address signal being currently received, read address based on specified write address and acquisition, determine that the second read/write address is poor, the second read/write address difference is that the corresponding read/write address of the second time delay is poor；The delay when address comparison logic circuit receives first, poor based on specified write address, the first time delay, the second read/write address difference and specified read/write address, the read address currently generated to read address generation circuit is reset.

It should be noted that specified read/write address difference can be preset, such as this, which specifies read/write address difference, to be 7,8, and the embodiment of the present invention is not specifically limited in this embodiment.

Since the time delay of asynchronous FIFO circuit includes integer time delay and decimal time delay, and decimal time delay is the introduced time delay of phase difference between read clock signal and write clock signal, and therefore, the decimal time delay of same asynchronous FIFO circuit is fixed.In order to guarantee that the time delay of asynchronous FIFO circuit is fixed, need to guarantee that synchronization is that specified read/write address is poor to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation, to guarantee that the integer time delay of same asynchronous FIFO circuit is fixed.And due to certain influences that can not survey factor, the read address that may result in the generation of read address generation circuit is wrong, synchronization is not that specified read/write address is poor to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation at this time, so as to cause wrong based on the time delay of the asynchronous FIFO circuit for specifying read/write address difference to determine at this time.Therefore, during the work of asynchronous FIFO circuit, it can determine in real time currently to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation, and when detecting the address difference not is specified read/write address difference, it is reset by the read address that address comparison logic circuit generates read address generation circuit, to guarantee that synchronization is that specified read/write address is poor to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation, to guarantee the accuracy of the time delay based on the determining asynchronous FIFO circuit of specified read/write address difference.

Since what address comparison logic circuit was used to send based on sync logic writes indication signal and reading ground The read address signal that location generation circuit is sent, it is currently poor to the read/write address between the read address that random access storage device carries out the write address of write operation and carries out read operation to determine, and the read address generated when the read/write address difference is not equal to specified read/write address difference to read address generation circuit is reset.When metastable state occurs for sync logic, what sync logic received writes the possible inaccuracy of indication signal, to influence the accuracy for the read/write address difference that address comparison logic circuit determines, and then the read address resetting for causing address comparison logic circuit to generate read address generation circuit is wrong.Again since the second time delay can eliminate the metastable state of sync logic, therefore, processor can set the second time delay for the time delay of delay line, sync logic, which can receive, at this time stable writes indication signal, it thereby may be ensured that the accuracy for the read/write address difference that address comparison logic circuit determines, and then the read address for guaranteeing that address comparison logic circuit can generate read address generation circuit is correctly reset.

Since the purpose that the read address that address comparison logic circuit generates read address generation circuit is reset is currently poor to the specified read/write address of address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation in order to make.Therefore, it is delayed when processor sets second for delay line, when delay line, which detects, writes indication signal, this can be write into indication signal by sync logic and be sent to address comparison logic circuit, so as to address comparison logic circuit can detect this write indication signal by the first logic level jump be the second logic level when, poor based on specified write address, the first time delay, the second read/write address difference and specified read/write address, the read address currently generated to read address generation circuit is reset.

It should be noted that delay when Yanzhong does not include second when this is N number of default, does not include at this time that the corresponding read/write address of the second time delay is poor in N number of read/write address difference, it is therefore desirable to be determined to the corresponding read/write address difference of the second time delay；And be delayed when this is N number of default, Yanzhong includes second, in order to guarantee the accuracy of determining the second read/write address difference, the corresponding read/write address difference of the second time delay can also be determined again.Therefore, whether Yanzhong includes the second time delay when no matter this is N number of default, it is delayed when processor sets second for the time delay of delay line, address comparison logic circuit can pass through delay line, sync logic and read address generation circuit, determine that the corresponding read/write address of the second time delay is poor, it that is to say, determine that the second read/write address is poor.

In addition, when address comparison logic circuit the rising edge of read clock signal detect this write indication signal by the first logic level jump be the second logic level when, obtain the read address carried in the read address signal being currently received, read address based on specified write address and acquisition, determine that the operation of the second read/write address difference is similar with the operation of step (2) in above-mentioned steps 702, the embodiment of the present invention repeats no more this.

The second way: being delayed when Yanzhong includes second when N number of default, and processor is from N number of read-write In the difference of location, the second read/write address of acquisition is poor, and the second read/write address difference is that the corresponding read/write address of the second time delay is poor；First time delay and the second read/write address difference are sent to address comparison logic circuit by processor, and set the second time delay for the time delay of delay line；When delay line, which detects, writes indication signal, indication signal will be write by sync logic and be sent to address comparison logic circuit；When address comparison logic circuit is when the rising edge of read clock signal detects that write indication signal is the second logic level and is received the first time delay and the second read/write address difference by the jump of the first logic level, poor based on specified write address, the first time delay, the second read/write address difference and specified read/write address, the read address currently generated to read address generation circuit is reset.

It should be noted that, it is delayed when this is N number of default, Yanzhong includes second, it include at this time that the corresponding read/write address of the second time delay is poor in N number of read/write address difference, therefore, it is poor that processor can directly acquire the corresponding read/write address of the second time delay from N number of read/write address difference, and the corresponding read/write address difference of second time delay is sent to address comparison logic circuit, address comparison logic circuit is without passing through delay line at this time, sync logic and read address generation circuit determine the corresponding read/write address difference of the second time delay again, to save the process resource in asynchronous FIFO circuit.

Wherein, in above-mentioned first way and the second way, address comparison logic circuit is based on specifying write address, the first time delay, the second read/write address difference and specified read/write address poor, and the operation reset to the read address that read address generation circuit currently generates may include such as one of under type (1) and mode (2):

(1), when the first time delay is less than or equal to signal stabilization time and 1 resulting address difference is added to be not equal to specified read/write address difference for the second read/write address difference, the number for the trigger that address comparison logic circuit includes based on specified write address and sync logic, it determines the first address, and sets the first address for the read address that read address generation circuit currently generates.

When the first time delay is less than or equal to signal stabilization time, as shown in Figure 10 (a), delay line will be delayed when being sent to sync logic when will write indication signal delay second, the rising edge c of read clock signal is located at the stability region A for writing the first logic level 0 of indication signal, and the rising edge d after the rising edge c of read clock signal is located at the stability region B for writing the second logic level 1 of indication signal.Since sync logic is only received in the rising edge of read clock signal to indication signal is write, sync logic can detect that writing indication signal by 0 jump of the first logic electricity is the second logic level 1 in the rising edge d of read clock signal.As shown in Fig. 9 (b), assuming that sync logic includes three triggers, then address comparison logic circuit can detect that writing indication signal by the jump of the first logic level 0 is the second logic level 1 in the rising edge f after the rising edge e of read clock signal at this time, and the read address that address comparison logic circuit obtains at this time is the read address received in the rising edge f of read clock signal.

When currently to random access storage device carry out write operation write address and carry out read operation read address it Between address difference when being specified read/write address difference, the read/write address difference that address comparison logic circuit is determined based on the read address that the rising edge e in read clock signal is received should be poor for specified read/write address, since read address generation circuit is 1 in the rising edge f of the read clock signal read address generated and the address difference between the read address that the rising edge e of read clock signal is generated, therefore, the delay when delay line will write indication signal delay second, the second read/write address difference that address comparison logic circuit is determined based on the read address that the rising edge f in read clock signal is received is poorer than specified read/write address small by 1.Therefore, when the first time delay is less than or equal to signal stabilization time and 1 resulting address difference is added to be not equal to specified read/write address difference for the second read/write address difference, it can determine currently be not that specified read/write address is poor to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation.The number for the trigger that address comparison logic circuit can include based on specified write address and sync logic at this time determines the first address, and sets the first address for the read address that read address generation circuit currently generates.

Wherein, the number for the trigger that address comparison logic circuit includes based on specified write address and sync logic, determine that the operation of the first address can be with are as follows: the number for the trigger that address comparison logic circuit includes based on specified write address and sync logic, determine the write address that write operation is currently carried out to random access storage device, it is poor based on the write address and specified read/write address, determine the first address, the address difference between the write address and the first address is that specified read/write address is poor.

Wherein, the number for the trigger that address comparison logic circuit includes based on specified write address and sync logic, determine that the operation for the write address for currently carrying out write operation to random access storage device can be with are as follows: the number for the trigger that sync logic includes is subtracted 1 and obtains the first numerical value by address comparison logic circuit, 1 is added to obtain the 5th numerical value the first numerical value, based on specified write address and the 5th numerical value, it determines that the address difference between the specified write address is the address of the 5th numerical value, determining address is determined as currently to carry out random access storage device the write address of write operation.

When the first time delay is less than or equal to signal stabilization time, as shown in Fig. 9 (b), it is the second logic level 1 that write address generation circuit generated, which writes indication signal and jumped in the rising edge a of write clock signal by the first logic level 0, delay line is delayed when this is write indication signal delay second, and sync logic detects that writing indication signal by the jump of the first logic level 0 is the second logic level 1 in the rising edge d of read clock signal.Since the rising edge d of read clock signal is after the rising edge b of write clock signal, the rising edge b of clock is write after writing the rising edge a of clock, therefore, detect that this was write in the period of the jump of indication signal in the rising edge d of read clock signal from writing rising edge a of the indication signal in write clock signal and jumping to sync logic, write address generation circuit can generate a write address in the rising edge b of write clock signal.And during sync logic will write indication signal and be sent to address comparison logic circuit, due to synchronous logic Circuit can will write indication signal and postpone for the first numerical value clock cycle, and therefore, write address generation circuit can generate the first numerical value write address in this process.It that is to say, when address comparison logic circuit detect write indication signal by the first logic level 0 jump be the second logic level 1 when, produce the first numerical value adds 1 write address to write address generation circuit again after generating specified write address, and the 5th numerical value is exactly that determination obtains after the first numerical value adds 1, therefore, it is the 5th numerical value that the address difference between the write address and specified write address of write operation is currently carried out to random access storage device, so the address that the address difference between specified write address is the 5th numerical value can be determined as currently carrying out random access storage device the write address of write operation.

Wherein, based on currently to random access storage device carry out write operation write address and specified read/write address it is poor, determine that the operation of the first address can be with reference to the relevant technologies, the embodiment of the present disclosure is to this without elaborating.

Such as, specified read/write address difference is 8, specified write address is 9, the number for the trigger that sync logic includes is 3, then subtracting 1 for the number 3 for the trigger that sync logic includes to obtain the first numerical value is 2, adding 1 to obtain the 5th numerical value the first numerical value is 3, then the write address for currently carrying out write operation to random access storage device is the write address 12 that address difference between specified write address 9 is the 5th numerical value 3.Since specified read/write address difference is 8, it can be based on the write address 12 and specified read/write address poor 8, determine that the first address is 4, later, the read address that address comparison logic circuit can currently generate read address generation circuit is set as the first address 4.

(2), when the first time delay is greater than signal stabilization time and the second read/write address difference is not equal to specified read/write address difference, the number for the trigger that address comparison logic circuit includes based on specified write address and sync logic, it determines the second address, and sets the second address for the read address that read address generation circuit currently generates.

When the first time delay is greater than signal stabilization time, as shown in Figure 10 (b) or Figure 10 (c), delay line will be delayed when being sent to sync logic when will write indication signal delay second, and the rising edge c of read clock signal is located at the stability region B for writing the second logic level 1 of indication signal.Since sync logic is only received in the rising edge of read clock signal to indication signal is write, sync logic can detect that writing indication signal by 0 jump of the first logic electricity is the second logic level 1 in the rising edge c of read clock signal.As shown in Fig. 9 (a), assuming that sync logic includes three triggers, then address comparison logic circuit can detect that writing indication signal by the jump of the first logic level 0 is the second logic level 1 in the rising edge e of read clock signal at this time, and the read address that address comparison logic circuit obtains is the read address received in the rising edge e of read clock signal.

When currently carrying out the address difference between the write address of write operation and the read address for carrying out read operation to random access storage device is specified read/write address difference, address comparison logic circuit is based on the rising in read clock signal The read/write address difference that the read address received along e determines should be poor for specified read/write address, therefore, when the first time delay is greater than signal stabilization time and the second read/write address difference is not equal to specified read/write address difference, it can determine currently be not that specified read/write address is poor to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation.The number for the trigger that address comparison logic circuit can include based on specified write address and sync logic at this time determines the second address, and sets the second address for the read address that read address generation circuit currently generates.

Wherein, the number for the trigger that address comparison logic circuit includes based on specified write address and sync logic, determine that two address operation can be with are as follows: the number for the trigger that address comparison logic circuit includes based on specified write address and sync logic, determine the write address that write operation is currently carried out to random access storage device, it is poor based on the write address and specified read/write address, determine the second address, the address difference between the write address and the second address is that specified read/write address is poor.

Wherein, the number for the trigger that address comparison logic circuit includes based on specified write address and sync logic, determine that the operation for the write address for currently carrying out write operation to random access storage device can be with are as follows: the number for the trigger that sync logic includes is subtracted 1 by address comparison logic circuit, obtain the first numerical value, based on specified write address, the determining address difference between specified write address is the address of the first numerical value, and determining address is determined as currently to carry out random access storage device the write address of write operation.

When the first time delay is greater than signal stabilization time, as shown in Fig. 9 (a), it is the second logic level 1 that write address generation circuit generated, which writes indication signal and jumped in the rising edge a of write clock signal by the first logic level 0, delay line is delayed when this is write indication signal delay second, and sync logic detects that writing indication signal by the jump of the first logic level 0 is the second logic level 1 in the rising edge c of read clock signal.Since the rising edge c of read clock signal is after the rising edge a of write clock signal, therefore, detect that this was write in the period of the jump of indication signal in the rising edge c of read clock signal from writing rising edge a of the indication signal in write clock signal and jumping to sync logic, write address generation circuit will not generate write address.And during sync logic will write indication signal and be sent to address comparison logic circuit, postponed for the first numerical value clock cycle since sync logic can will write indication signal, therefore, write address generation circuit can generate the first numerical value write address in this process.It that is to say, when address comparison logic circuit detect write indication signal by the first logic level 0 jump be the second logic level 1 when, write address generation circuit produces the first numerical value write address after generating specified write address again, so, it is the first numerical value that the address difference between the write address and specified write address of write operation is currently carried out to random access storage device, therefore, the address that the address difference between specified write address is the first numerical value can be determined as currently carrying out random access storage device the write address of write operation.

Wherein, based on currently to random access storage device carry out write operation write address and specified read/write address it is poor, determine that two address operation can be with reference to the relevant technologies, the embodiment of the present disclosure is to this without elaborating.

Such as, specified read/write address difference is 8, specified write address is 9, the number for the trigger that sync logic includes is 3, subtracting 1 for the number 3 for the trigger that sync logic includes to obtain the first numerical value is 2, the write address for then currently carrying out write operation to random access storage device is the write address 11 that address difference between specified write address 9 is the first numerical value 2, since specified read/write address difference is 8, therefore, it can be based on the write address 11 and specified read/write address poor 8, determine that the second address is 3, later, the read address that address comparison logic circuit can currently generate read address generation circuit is set as the second address 3.

Step 704: processor is based on decimal time delay, determines the time delay of asynchronous FIFO circuit.

Specifically, processor obtains integer time delay, and the sum of decimal time delay and integer time delay are determined as to the time delay of asynchronous FIFO circuit, integer time delay is the synchronization time delay introduced to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation.

Wherein, it is delayed when processor obtains integer, specified read/write address difference and the product of clock cycle can be determined as integer time delay, certainly, in practical application, processor can also obtain integer time delay otherwise, and the embodiment of the present invention is not specifically limited in this embodiment.

For example, specified read/write address difference is 8, clock cycle 10ns, then specified read/write address poor 8 can be multiplied by processor with clock cycle 10ns, and obtaining integer time delay is 80ns,

Further, when processor receives reset setting instruction, third address is set by write address electrification reset value, the 4th address is set by read address electrification reset value, third address is that specified read/write address is poor with four address address difference, write address electrification reset value is the initial write address that write address generation circuit generates when powering on, and read address electrification reset value is the initial read address that read address generation circuit generates when powering on.

In addition, in embodiments of the present invention, third address is set by write address electrification reset value, the 4th address is set by read address electrification reset value, and third address is that specified read/write address is poor with four address address difference, asynchronous FIFO circuit can be guaranteed when powering on rigid start-up operation, it is that specified read/write address is poor to the address difference between the read address that random access storage device carries out the write address of write operation and carries out read operation, to guarantee that the time delay of the asynchronous FIFO circuit in whole work process is all the same, guarantee the accuracy of the time delay of determining asynchronous FIFO circuit.

It, can be with it should be noted that delayed in the embodiment of the present invention when determining asynchronous FIFO circuit The asynchronous FIFO circuit of the determination time delay is applied in the digital signal transceiver of base station in wireless communication system, such as, it can be applied to MIMO (the Multi-Input Multi-Output of base station, multiple-input and multiple-output) or massive MIMO multiaerial system in digital signal transceiver in, to guarantee that each antenna to the transmitting-receiving Timing Synchronization for signal of eating dishes without rice or wine, improves the Timing Synchronization precision of base station.Certainly, the asynchronous FIFO circuit of the determination time delay can also be applied in synchronous transmission network, for example, can be applied in the Ethernet using IEEE-1588 agreement, to guarantee the accurate transmission of timestamp in a network in IEEE-1588 agreement, the clock synchronization accuracy between network node is improved.

In embodiments of the present invention, during carrying out read operation and write operation to random access storage device, multiple read address signals of generation are sent to address comparison logic circuit by read address generation circuit, the indication signal of writing of generation is sent to delay line by write address generation circuit, processor passes through read address generation circuit, delay line, sync logic and address comparison logic circuit, indication signal is write based on this, multiple read address signal and the read clock signal for reading clock generation circuit generation, N number of read/write address is poor correspondingly with N number of default time delay in delay line for acquisition, later, processor is based on N number of read/write address difference and interconnection delay, determine decimal time delay, and it is based on the decimal time delay, determine the time delay of asynchronous FIFO circuit, to realize to the accurate of the time delay of asynchronous FIFO circuit It determines.In addition, in embodiments of the present invention, processor is also based on the first time delay, determine the second time delay, and it is based on the first time delay and the second time delay, it is reset by the read address that address comparison logic circuit generates read address generation circuit, since the second time delay can eliminate the metastable state of sync logic, it may therefore be assured that address comparison logic circuit correctly resets the read address that read address generation circuit generates.

Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment may be implemented by hardware, relevant hardware can also be instructed to complete by program, the program can store in a kind of computer readable storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..

The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, and all within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.

Claims

A kind of asynchronous First Input First Output fifo circuit, it is characterized in that, the asynchronous FIFO circuit includes: to write clock generation circuit, read clock generation circuit, write address generation circuit, read address generation circuit, random access storage device, delay line, sync logic, address comparison logic circuit and processor；

The output end for writing clock generation circuit is connect with the input terminal of the write address generation circuit, first output end of the write address generation circuit is connect with the first input end of the random access storage device, the second output terminal of the write address generation circuit is connect with the first input end of the delay line, second input terminal of the delay line is connect with the first output end of the processor, the output end of the delay line is connect with the first input end of the sync logic, the output end of the sync logic is connect with the first input end of the address comparison logic circuit, second input terminal of the second input terminal of the sync logic and the address comparison logic circuit is connect with the output end for reading clock generation circuit respectively；

The output end for reading clock generation circuit is also connect with the input terminal of the read address generation circuit, the output end of the read address generation circuit is connect with the second input terminal of the random access storage device, the output end of the read address generation circuit is also connect with the third input terminal of the address comparison logic circuit, and the first output end of the address comparison logic circuit is connect with the input terminal of the processor.
Asynchronous FIFO circuit as described in claim 1, which is characterized in that

The second output terminal of the address comparison logic circuit is connect with the set end of the read address generation circuit.
Asynchronous FIFO circuit as claimed in claim 1 or 2, which is characterized in that

The second output terminal of the processor is connect with the reset terminal of the write address generation circuit, and the third output end of the processor is connect with the reset terminal of the read address generation circuit.
Asynchronous FIFO circuit as described in claim 1-3 any claim, which is characterized in that the delay line includes: N-1 delay section and N number of tap, and the N is the natural number greater than 1；

The N-1 delay section is connected in series, one end of i-th of delay section is connect with i-th of tap in N number of tap in the N-1 delay section, the other end of i-th of delay section is connect with i+1 tap in N number of tap in the N-1 delay section, and the i is greater than or equal to 1 and is less than or equal to N-1.
Asynchronous FIFO circuit as described in claim 1-4 any claim, it is characterized in that, the sync logic includes multiple concatenated triggers, and each trigger is used to write indication signal in the rising edge reception of the read clock signal of the reading clock generation circuit generation in the multiple concatenated trigger.
Asynchronous FIFO circuit as claimed in claim 4, which is characterized in that

The read address generation circuit, for the multiple read address signals generated to be sent to the address comparison logic circuit；

The write address generation circuit, indication signal of writing for that will generate is sent to the delay line, the indication signal of writing is that at least two write addresses based on write address generation circuit generation generate, and the indication signal of writing is jumped when the write address generation circuit generates specified write address by the first logic level as the second logic level；

The processor, for passing through the read address generation circuit, the delay line, the sync logic and the address comparison logic circuit, indication signal, the multiple read address signal and the read clock signal reading clock generation circuit and generating are write based on described, obtain that N number of read/write address is poor, N number of default time delay in N number of read/write address difference and the delay line corresponds；

The processor, it is also used to based on N number of read/write address difference and interconnection delay, determine decimal time delay, and it is based on the decimal time delay, determine the time delay of the asynchronous FIFO circuit, the introduced time delay of wiring of the interconnection delay between the write address generation circuit and the sync logic, the decimal time delay are the introduced time delay of the phase difference between the read clock signal and the write clock signal for writing clock generation circuit generation.
Asynchronous FIFO circuit as claimed in claim 6, which is characterized in that

The delay line, for when detect it is described write indication signal when, by it is described write indication signal and postpone to delay when i-th of tap is corresponding default in N number of tap the address comparison logic circuit is sent to by the sync logic, N number of tap and N number of default time delay correspond；

The address comparison logic circuit, for when the rising edge in the read clock signal detect it is described to write indication signal by first logic level jump be second logic level when, obtain the read address carried in the read address signal being currently received, and the read address based on the specified write address and acquisition, it determines that the corresponding read/write address of i-th of tap is poor, the corresponding read/write address difference of i-th of tap is sent to the processor；

The processor, for when receiving the corresponding read/write address difference of i-th of tap, described in order I=i+1, again through the delay line by it is described write indication signal and postpone to delay when i-th of tap is corresponding default in N number of tap the address comparison logic circuit is sent to by the sync logic.
A kind of time delay determines method, applied in asynchronous FIFO circuit described in the claims 1-7 any claim, which is characterized in that the described method includes:

During carrying out read operation and write operation to the random access storage device, multiple read address signals of generation are sent to the address comparison logic circuit by the read address generation circuit, the indication signal of writing of generation is sent to the delay line by the write address generation circuit, the indication signal of writing is that at least two write addresses based on write address generation circuit generation generate, and the indication signal of writing is jumped when the write address generation circuit generates specified write address by the first logic level as the second logic level；

The processor passes through the read address generation circuit, the delay line, the sync logic and the address comparison logic circuit, indication signal, the multiple read address signal and the read clock signal reading clock generation circuit and generating are write based on described, it is poor to obtain N number of read/write address, N number of default time delay in N number of read/write address difference and the delay line corresponds, and the N is the natural number greater than 1；

The processor is based on N number of read/write address difference and interconnection delay, determine decimal time delay, the introduced time delay of wiring of the interconnection delay between the write address generation circuit and the sync logic, the decimal time delay are the introduced time delay of the phase difference between the read clock signal and the write clock signal for writing clock generation circuit generation；

The processor is based on the decimal time delay, determines the time delay of the asynchronous FIFO circuit.
Method according to claim 8, which is characterized in that the delay line includes N-1 delay section and N number of tap, and N number of tap and N number of default time delay correspond；

The processor passes through the read address generation circuit, the delay line, the sync logic and the address comparison logic circuit, indication signal, the multiple read address signal and the read clock signal reading clock generation circuit and generating are write based on described, it is poor to obtain N number of read/write address, comprising:

When the delay line detect it is described write indication signal when, by it is described write indication signal and postpone to delay when i-th of tap is corresponding default in N number of tap the address comparison logic circuit is sent to by the sync logic, the i is greater than or equal to 1 and is less than or equal to N-1；

When the address comparison logic circuit the rising edge of the read clock signal detect it is described to write indication signal by first logic level jump be second logic level when, obtain the read address carried in the read address signal being currently received, based on the read address of the specified write address and acquisition, i-th of pumping is determined Corresponding read/write address is poor, and the corresponding read/write address difference of i-th of tap is sent to the processor；

When the processor receives the corresponding read/write address difference of i-th of tap, the i=i+1 is enabled, return is described to be postponed the indication signal of writing to delay the step of being sent to the address comparison logic circuit by the sync logic when i-th of tap is corresponding default in N number of tap.
Method as claimed in claim 9, which is characterized in that read address of the address comparison logic circuit based on specified write address and acquisition determines that the corresponding read/write address of i-th of tap is poor, comprising:

The address comparison logic circuit determines the address difference between the specified write address and the read address of acquisition；

The number for the trigger that the sync logic includes is subtracted 1 by the address comparison logic circuit, obtains the first numerical value；

Determining address difference is added by the address comparison logic circuit with first numerical value, and it is poor to obtain the corresponding read/write address of i-th of tap.
Method as described in claim 8-10 any claim, which is characterized in that the processor is based on the N number of read/write address difference and interconnection delay, before determining decimal time delay, further includes:

The processor obtains the introduced maximum delay and minimal time delay of wiring between the write address generation circuit and the sync logic from the wiring report of the rear end of storage, and the rear end wiring report is for recording the introduced time delay of all wirings that the asynchronous FIFO circuit includes；

The average value of the maximum delay and the minimal time delay is determined as the interconnection delay by the processor.
Method as described in claim 8-11 any claim, which is characterized in that the processor is based on N number of read/write address difference and interconnection delay, determines decimal time delay, comprising:

The processor be based on N number of read/write address it is poor, from it is described N number of default when Yanzhong determine the first time delay；

The sum of first time delay and the interconnection delay are determined as the decimal time delay by the processor.
Method as claimed in claim 12, which is characterized in that the processor be based on N number of read/write address it is poor, from it is described N number of default when Yanzhong determine the first time delay, comprising:

The processor is based on N number of default time delay, is ranked up to N number of read/write address difference, obtains the sequence of N number of read/write address difference；

Sequence of the processor based on N number of read/write address difference, it is poor that the first read/write address is obtained from N number of read/write address difference, the first read/write address difference is to be obtained based on the read/write address difference determination jumped in N number of read/write address difference, and the read/write address difference of the jump is that the read/write address different from previous position read/write address difference is poor；

The corresponding default time delay of the first read/write address difference is determined as first time delay by the processor.
Method as described in claim 12 or 13, which is characterized in that the processor is based on the N number of read/write address difference and interconnection delay, after determining decimal time delay, further includes:

The processor is based on first time delay, determines that the second time delay, second time delay are that can eliminate the metastable time delay of the sync logic；

The processor is based on first time delay and second time delay, is reset by the read address that the address comparison logic circuit generates the read address generation circuit.
Method as claimed in claim 14, which is characterized in that the processor is based on first time delay, determines the second time delay, comprising:

When first time delay is less than or equal to signal stabilization time, the sum of first time delay and the first default time delay are determined as second time delay by the processor, the first default time delay is greater than the signal stabilization time and is less than third time delay, the signal stabilization time is the sum of settling time and retention time of first order trigger, the trigger being connect in multiple triggers that the first order trigger includes for the sync logic with the delay line, difference of the third time delay between clock cycle and the signal stabilization time, the clock cycle is the period of the read clock signal or the write clock signal, the read clock signal is equal with the period of the write clock signal, the signal stabilization time is less than the third time delay；Alternatively,

It is delayed when first time delay is greater than the signal stabilization time and is less than the third, first time delay is subtracted the second default time delay by the processor, second time delay is obtained, the second default time delay is greater than the signal stabilization time and is less than or equal to the decimal time delay；Alternatively,

It is delayed when first time delay is greater than or equal to the third, first time delay is subtracted the described first default time delay by the processor, obtains second time delay.
Method as described in claims 14 or 15, which is characterized in that the processor is based on first time delay and second time delay, is reset by the read address that the address comparison logic circuit generates the read address generation circuit, comprising:

First time delay is sent to the address comparison logic circuit by the processor；

The time delay of the delay line is set second time delay by the processor；

When the delay line detect it is described write indication signal when, write indication signal by described the address comparison logic circuit be sent to by the sync logic；

When the address comparison logic circuit the rising edge of read clock signal detect it is described to write indication signal by first logic level jump be second logic level when, obtain the read address carried in the read address signal being currently received, read address based on the specified write address and acquisition, determine that the second read/write address is poor, the second read/write address difference is that the corresponding read/write address of second time delay is poor；

The delay when the address comparison logic circuit receives described first, poor based on the specified write address, first time delay, second read/write address difference and specified read/write address, the read address currently generated to the read address generation circuit is reset.
Method as described in claims 14 or 15, which is characterized in that the processor is based on first time delay and second time delay, is reset by the read address that address comparison logic circuit generates the read address generation circuit, comprising:

Delay when Yanzhong includes described second when described N number of default, the processor is from N number of read/write address difference, and the second read/write address of acquisition is poor, and the second read/write address difference is that the corresponding read/write address of second time delay is poor；

First time delay and the second read/write address difference are sent to the address comparison logic circuit by the processor；

The time delay of the delay line is set second time delay by the processor；

When the delay line detect it is described write indication signal when, write indication signal by described the address comparison logic circuit be sent to by the sync logic；

When the address comparison logic circuit the rising edge of the read clock signal detect it is described write indication signal and be second logic level and received first time delay and the second read/write address difference by first logic level jump when, poor based on the specified write address, first time delay, second read/write address difference and specified read/write address, the read address currently generated to the read address generation circuit is reset.
Method as described in claim 16 or 17, it is characterized in that, the address comparison logic circuit is poor based on the specified write address, first time delay, second read/write address difference and specified read/write address, and the read address currently generated to the read address generation circuit is reset, comprising:

When first time delay is less than or equal to signal stabilization time and the second read/write address difference adds 1 resulting address difference not equal to the specified read/write address difference, the number for the trigger that the address comparison logic circuit includes based on the specified write address and the sync logic, it determines the first address, and sets first address for the read address that the read address generation circuit currently generates；Alternatively,

When first time delay is greater than the signal stabilization time and the second read/write address difference is not equal to the specified read/write address difference, the number for the trigger that the address comparison logic circuit includes based on the specified write address and the sync logic, it determines the second address, and sets second address for the read address that the read address generation circuit currently generates.
Method as described in claim 8-18 any claim, which is characterized in that the processor is based on the decimal time delay, determines the time delay of the asynchronous FIFO circuit, comprising:

The processor obtains integer time delay, and the integer time delay is the synchronization time delay introduced to the address difference between the read address that the random access storage device carries out the write address of write operation and carries out read operation；

The sum of the decimal time delay and the integer time delay are determined as the time delay of the asynchronous FIFO circuit by the processor.
Method as described in claim 8-19 any claim, which is characterized in that the method also includes:

When the processor receives reset setting instruction, third address is set by write address electrification reset value, the 4th address is set by read address electrification reset value, the third address is that specified read/write address is poor with the four address address difference, the write address electrification reset value is the initial write address that the write address generation circuit generates when powering on, and the read address electrification reset value is the initial read address that the read address generation circuit generates when powering on.