JP2017034383A - Transmission equipment and synchronization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To synchronize between devices with high accuracy without increasing a clock frequency.SOLUTION: A first board 110 receives time information by latching a frame, which is a frame transmitted from the self-device and returned before a second board 120 latches with a reference clock, using the reference clock of the self-device. Also, the first board 110 determines a phase difference between the latched frame and the reference clock of the self-device, on the basis of a plurality of clocks generated by delaying the reference clock of the self-device. Further, the first board 110 calculates a frame transmission delay amount between the self-device and the second board 120, on the basis of the reception time of the time information, the received time information and the determined phase difference. Then, the first board 110 corrects the time which is indicated by the time information included in the frame transmitted from the self-device to the second board 120, on the basis of the calculated transmission delay amount.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a transmission apparatus and a synchronization method.

  2. Description of the Related Art Conventionally, a technique is known in which k clock signals whose phases are shifted with respect to a first clock signal are generated and each of them is latched to obtain k 1-bit signals (for example, the following patent Reference 1). In addition, a technique is known in which a transmission delay time is calculated by turning back a time notification frame between devices, and the time notification frame is corrected based on the calculated delay time (see, for example, Patent Document 2 below).

  In addition, a technique for measuring a transmission line delay by turning back a transmission line delay measurement frame between apparatuses is known (for example, see Patent Document 3 below). In addition, a technique for correcting the reference timing of the sampling pulse oscillation circuit based on a deviation value between the reference timing and the reception timing in a timing synchronization apparatus connected to a communication network is known (for example, see Patent Document 4 below). .)

JP 2011-2111346 A JP 2009-128174 A International Publication No. 2008/123272 JP 2009-182659 A

  However, in the above-described conventional technique, for example, when measuring a transmission delay amount between devices, an error due to a phase difference between a time frame including time information and a reference clock in the device that latches the time frame occurs. There is a case. For this reason, there exists a problem that it cannot synchronize between apparatuses accurately.

  It is also possible to reduce the above-mentioned error by increasing the frequency of the reference clock, but this requires a device that supports high-speed transmission and high-speed processing, so it is difficult to increase the frequency of the reference clock. is there.

  In one aspect, an object of the present invention is to provide a transmission apparatus and a synchronization method that can accurately synchronize apparatuses without increasing the clock frequency.

  In order to solve the above-described problems and achieve the object, according to one aspect of the present invention, the first transmission device transmits a frame including time information based on the clock of the first transmission device to the second transmission device. The second transmission device returns the frame transmitted by the first transmission device before being latched by the reference clock of the second transmission device to the first transmission device, and the first transmission device returns the first transmission device to the first transmission device. A transmission device receives the time information by latching the frame returned by the second transmission device with a reference clock of the first transmission device, and the first transmission device receives a reference of the first transmission device. Determining a phase difference between the frame latched by the first transmission device and a reference clock of the first transmission device based on a plurality of clocks generated by delaying the clock; Transmission delay of the frame between the first transmission device and the second transmission device based on the time when the transmission device receives the time information, the received time information, and the determined phase difference The second transmission device corrects the time indicated by the time information included in the frame transmitted from the first transmission device to the second transmission device based on the calculated transmission delay amount. Receives the time information by latching the frame transmitted by the first transmission device with a reference clock of the second transmission device, and the second transmission device receives the reference clock of the second transmission device. Determining a phase difference between the frame latched by the second transmission device and a reference clock of the second transmission device based on a plurality of clocks generated by delaying; Transmission device, and the time information received, and the phase difference is determined, the transmission apparatus and synchronizing method of clocks of the second transmission device is synchronized with the clock of the first transmission device based on are proposed.

  According to one aspect of the present invention, there is an effect that synchronization between devices can be accurately performed without increasing the clock frequency.

FIG. 1 is a diagram illustrating an example of a synchronization system according to an embodiment. FIG. 2 is a sequence diagram illustrating an example of time synchronization processing in the synchronization system according to the embodiment. FIG. 3 is a diagram illustrating an example of a time frame according to the embodiment. FIG. 4 is a diagram illustrating an example of transmission / reception timing of a time frame in the synchronization system according to the embodiment. FIG. 5 is a diagram illustrating an example of the clock shift circuit and the reception timing measurement circuit according to the embodiment. FIG. 6 is a diagram illustrating an example of shift register values in the 8-stage shift register according to the embodiment. FIG. 7 is a diagram illustrating an example of the phase determination based on the shift register value according to the embodiment. FIG. 8 is a diagram illustrating an example of correction of time information by the first board according to the embodiment. FIG. 9 is a diagram illustrating an example of synchronization between the boards according to the embodiment. FIG. 10 is a diagram illustrating an example of an apparatus to which the synchronization system according to the embodiment is applied.

  Embodiments of a transmission apparatus and a synchronization method according to the present invention will be described below in detail with reference to the drawings.

(Embodiment)
(Synchronization system according to the embodiment)
FIG. 1 is a diagram illustrating an example of a synchronization system according to an embodiment. As shown in FIG. 1, the synchronization system 100 according to the embodiment includes a first board 110 and a second board 120. The first board 110 transmits a time frame including time information indicating the time based on the clock of the first board 110 (self apparatus) to the second board 120 (other transmission apparatus), whereby the clock of the second board 120 is displayed. Is a transmission device that synchronizes with the clock of the first board 110. The clock is a processing unit that generates time information indicating the current time (for example, year, month, day, hour, minute, second,...).

  Transmission of signals between the first board 110 and the second board 120 can be performed by an electric signal via an electric signal line, for example. However, the transmission of signals between the first board 110 and the second board 120 is not limited to an electric signal via an electric signal line, and may be performed by, for example, an optical signal via a light transmission path or a radio signal. May be. Here, it is assumed that the time required for signal transmission between the first board 110 and the second board 120 is the same in both directions.

  The first board 110 includes, for example, a reference clock generation circuit 111, a counter 112, a correction circuit 113, a clock shift circuit 114, and a reception timing measurement circuit 115. Further, the first board 110 may further include a buffer 119.

  The reference clock generation circuit 111 generates a reference clock that is an internal clock in the first board 110. Then, the reference clock generation circuit 111 outputs the generated reference clock to each part of the first board 110 as an operation clock. For example, the counter 112, the correction circuit 113, and the clock shift circuit 114 operate using the reference clock output from the reference clock generation circuit 111 as an operation clock.

  The counter 112 is a clock that generates time information indicating the current time by counting up based on the reference clock output from the reference clock generation circuit 111. For example, every time the reference clock output from the reference clock generation circuit 111 rises, the counter 112 adds a predetermined time (for example, 8 [ns] in the example shown in FIG. 4) to the currently held time. To generate time information. Then, the counter 112 outputs the generated time information to the correction circuit 113.

  The correction circuit 113 determines the time indicated by the time information output from the reference clock generation circuit 111 based on a transmission delay amount between the first board 110 and the second board 120, a delay amount in the first board 110, and the like. To correct.

  For example, the correction circuit 113 directly corrects the time information from the reference clock generation circuit 111. Alternatively, the correction circuit 113 may correct the time information by generating information indicating the time indicated by the time information from the reference clock generation circuit 111 and the correction value for the time as corrected time information. Good.

  The time information corrected by the correction circuit 113 is stored in a time frame and transmitted to the second board 120. Accordingly, when the time information reaches the second board 120, the time indicated by the time information can be made to coincide with the time in the first board 110. Further, in order to secure the signal power of the time frame transmitted from the first board 110 to the second board 120, the time frame is amplified by the buffer 119 provided between the correction circuit 113 and the transmission end of the first board 110. It is good also as a structure.

  For example, the correction circuit 113 includes an addition unit 116, a difference calculation unit 117, and a division unit 118. The adding unit 116 is a correcting unit that corrects the time information by adding a predetermined time to the time information output from the counter 112. The adder 116 transmits (sends) time information obtained by adding a predetermined time to the second board 120. The predetermined time that the addition unit 116 adds to the time information includes, for example, the transmission delay amount of the time frame between the first board 110 and the second board 120 that is notified from the division unit 118. The calculation of the transmission delay amount by the division unit 118 will be described later.

  In addition, the processing time in the first board 110 from when the time information is transmitted from the counter 112 to when the time information is transmitted to the second board 120 is the predetermined time that the adding unit 116 adds to the time information. It may be included. This processing time can be a fixed value calculated based on, for example, an actual measurement result, a simulation result, or a theoretical value.

  The clock shift circuit 114 generates a plurality of clocks having different timings (phases) by shifting (delaying) the reference clock output from the reference clock generation circuit 111. Then, the clock shift circuit 114 outputs the generated plurality of clocks to the reception timing measurement circuit 115.

  The reception timing measurement circuit 115 receives a time frame transmitted from the first board 110 to the second board 120 and immediately returned by the second board 120. The time frame immediately returned by the second board 120 is a time frame returned to the first board 110 before the second board 120 latches with the reference clock of the second board 120.

  The reception timing measurement circuit 115 (reception unit) receives the time information transmitted from the first board 110 to the second board 120 by the time frame by latching the input time frame with the reference clock of the first board 110. . The reference clock used by the reception timing measurement circuit 115 for latching the time frame is, for example, the reference clock output from the reference clock generation circuit 111. Alternatively, the reference clock used by the reception timing measurement circuit 115 for latching the time frame may be a clock having a shift amount of 0 [ns] among a plurality of clocks output from the clock shift circuit 114.

  The reception timing measurement circuit 115 also receives the input time frame and the reference clock from the reference clock generation circuit 111 based on the input time frame and the plurality of clocks output from the clock shift circuit 114. Determine the phase difference between. Then, the reception timing measurement circuit 115 outputs time information of the received time frame and phase difference information indicating the determined phase difference to the correction circuit 113.

  The difference calculation unit 117 of the correction circuit 113 is based on the time information and phase difference information from the reception timing measurement circuit 115 and the time information from the counter 112, between the first board 110 and the second board 120. Calculate the round trip transmission delay. For example, the time information value from the counter 112 is a, the time information value from the reception timing measurement circuit 115 is b, and the phase difference information value from the reception timing measurement circuit 115 is c. In this case, a indicates the time frame reception time, b indicates the time frame transmission time, and c indicates the phase difference between the time frame and the reference clock. The difference calculation unit 117 can calculate a round-trip transmission delay amount between the first board 110 and the second board 120 by calculating, for example, a−b + c. Then, the difference calculation unit 117 outputs the calculation result to the division unit 118.

  The division unit 118 divides the calculation result output from the difference calculation unit 117 by “2”. Thereby, the one-way transmission delay amount between the first board 110 and the second board 120 can be accurately calculated. The division unit 118 notifies the addition unit 116 of the calculated transmission delay amount.

  As described above, the time (a) when the time information is received by the difference calculation unit 117 and the division unit 118, the received time information (b), and the phase difference (c) determined by the reception timing measurement circuit 115. The transmission delay amount can be calculated based on the above.

  The second board 120 includes, for example, a return unit 121, a reference clock generation circuit 122, a clock shift circuit 123, a reception timing measurement circuit 124, and a counter 125. The second board 120 may further include a buffer 126.

  The return unit 121 is a time frame transmitted from the first board 110 and input to the second board 120, and the time frame before being latched by the reference clock of the second board 120 by the reception timing measurement circuit 124 is the first time frame. Return to board 110 (immediate return). This prevents the phase difference between the time frame input to the second board 120 and the reference clock of the second board 120 from affecting the round-trip transmission delay time of the time frame. Can do. Therefore, in the first board 110, it is possible to calculate the transmission delay amount between the first board 110 and the second board 120 with high accuracy.

  For example, the return unit 121 branches the signal between the reception end of the second board 120 and the reception timing measurement circuit 124 and connects the branched signal to the transmission path from the second board 120 to the first board 110. Can be realized by physical wiring. This physical wiring is, for example, a wiring used for transmission from the first board 110 to the second board 120 and a wiring used for transmission (return) from the second board 120 to the first board 110. Same thing. In order to secure the signal power of the time frame returned from the second board 120 to the first board 110, a buffer 126 may be provided in the return unit 121 to amplify the time frame.

  The reference clock generation circuit 122 generates a reference clock that is an internal clock in the second board 120. The reference clock generation circuit 122 outputs the generated reference clock to each unit of the second board 120 as an operation clock. For example, the clock shift circuit 123 and the reception timing measurement circuit 124 operate using the reference clock output from the reference clock generation circuit 122 as an operation clock.

  The reference clock of the second board 120 generated by the reference clock generation circuit 122 may not be synchronized with the reference clock of the first board 110. However, the reference clock of the second board 120 generated by the reference clock generation circuit 122 is frequency-synchronized with the reference clock of the first board 110. The frequency synchronization between the reference clock of the first board 110 and the reference clock of the second board 120 is performed by the first board 110 transmitting the reference clock of the reference clock generation circuit 111 to the second board 120, for example. Can do. In this case, the second board 120 synchronizes the frequency of the reference clock of the reference clock generation circuit 122 with the frequency of the reference clock received from the first board 110.

  The frequency synchronization method between the reference clock of the first board 110 and the reference clock of the second board 120 is not limited to this. For example, frequency synchronization between the reference clock of the first board 110 and the reference clock of the second board 120 is performed using CDR (Clock Data Recovery) in transmission between the first board 110 and the second board 120. Also good. In this case, the second board 120 synchronizes the frequency of the reference clock of the reference clock generation circuit 122 with the frequency of the clock recovered by the CDR (recovery clock).

  The clock shift circuit 123 generates a plurality of clocks having different timings (phases) by shifting (delaying) the reference clock output from the reference clock generation circuit 122. Then, the clock shift circuit 123 outputs the generated plurality of clocks to the reception timing measurement circuit 124.

  The time frame transmitted from the first board 110 to the second board 120 is input to the reception timing measurement circuit 124. The reception timing measurement circuit 124 receives the time information transmitted from the first board 110 to the second board 120 by the time frame by latching the input time frame with the reference clock of the second board 120. The reference clock used for latching by the reception timing measurement circuit 124 may be, for example, the reference clock output from the reference clock generation circuit 122, or the shift amount of each clock output from the clock shift circuit 123 is 0 [ns]. The clock may be.

  Further, the reception timing measurement circuit 124, based on the input time frame and each clock from the clock shift circuit 123, between the input time frame and the reference clock from the reference clock generation circuit 122. The phase difference is determined. Then, the reception timing measurement circuit 124 outputs time information of the received time frame and phase difference information indicating the determined phase difference to the counter 125.

  The counter 125 is a clock that generates time information based on the reference clock output from the reference clock generation circuit 122 and the time information output from the reception timing measurement circuit 124. The counter 125 is a synchronization unit that synchronizes the clock of the second board 120 with the clock of the first board 110 by correcting the time information to be generated based on the phase difference information output from the reception timing measurement circuit 124. It has the function of. Thereby, even if there is a phase difference between the time frame input to the second board 120 and the reference clock from the reference clock generation circuit 122, the time information of the first board 110 and the second board 120 Time information can be synchronized. The time information generated by the counter 125 is output to each functional unit that requires time information in the second board 120.

(Time synchronization processing in the synchronization system according to the embodiment)
FIG. 2 is a sequence diagram illustrating an example of time synchronization processing in the synchronization system according to the embodiment. In the synchronization system 100 shown in FIG. 1, for example, each step shown in FIG. 2 is executed as time synchronization processing. First, the first board 110 latches time information indicating the current time of the internal time of the first board 110 with the reference clock of the first board 110 (step S201). Step S201 is performed, for example, by the correction circuit 113 latching the time information output from the counter 112 with the reference clock output from the reference clock generation circuit 111.

  Next, the time information obtained by adding the transmission delay amount between the first board 110 and the second board 120 and the predetermined processing time to the time information latched by the first board 110 in step S201 is obtained as a time frame. (Step S202). Step S202 is performed by the correction circuit 113, for example.

  The transmission delay amount added to the time information in step S202 can be, for example, “0” in the initial state, and the transmission delay amount calculated in step S206 after step S206. The processing time added to the time information in step S202 is, for example, the time taken from latching the time information in step S201 to storing the time information in the time frame in step S202. Further, the processing time added to the time information in step S202 may include the time taken until the time frame is transmitted in step S203 described later.

  Next, the first board 110 transmits (sends) the time frame storing the time information in step S202 to the second board 120 (step S203). Step S203 is performed via a transmission path between the first board 110 and the second board 120, for example.

  Next, the second board 120 returns the time frame transmitted in step S203 without being latched by the reference clock of the second board 120 (step S204). Step S <b> 204 is performed, for example, by the return unit 121 via the transmission path between the first board 110 and the second board 120.

  Next, the first board 110 determines the phase difference between the reference clock of the first board 110 and the time frame received from the second board 120 in step S204 (step S205). Step S205 is performed by, for example, the clock shift circuit 114 and the reception timing measurement circuit 115.

  Next, the first board 110 calculates the transmission delay amount between the first board 110 and the second board 120 (step S206), and returns to step S201. Thereby, the time information corrected based on the transmission delay amount between the first board 110 and the second board 120 is transmitted from the first board 110 to the second board 120. The calculation of the transmission delay amount in step S206 can be performed based on the time when the time frame is received in step S204, the time information of the time frame received in step S204, and the phase difference determined in step S205. Step S206 is performed by the difference calculation unit 117 and the division unit 118, for example.

  Further, the second board 120 determines a phase difference between the reference clock of the second board 120 and the time frame received from the first board 110 in step S203 (step S207). Step S207 is performed by the clock shift circuit 123 and the reception timing measurement circuit 124, for example.

  Next, the second board 120 calculates the current time based on the time information stored in the time frame received from the first board 110 in step S203 and the phase difference determined in step S207 (step S208). ), A series of processing ends. Further, every time the second board 120 receives a time frame from the first board 110 in step S203, the second board 120 calculates the current time based on the time information stored in the time frame in steps S207 and S208.

  Here, the time information stored in the time frame transmitted from the first board 110 on and after the second time becomes the time information corrected based on the transmission delay amount between the first board 110 and the second board 120. . Therefore, the second board 120 calculates the current time based on the time information corrected based on the transmission delay amount between the first board 110 and the second board 120, and thereby between the first board 110 and the second board 120. Synchronize with high accuracy.

(Time frame according to the embodiment)
FIG. 3 is a diagram illustrating an example of a time frame according to the embodiment. For example, the first board 110 transmits a time frame 300 shown in FIG. 3 to the second board 120. The time frame 300 includes a frame detection unit 310 and time information 320. The frame detection unit 310 is a known pattern (preamble) in the first board 110 and the second board 120 for detecting the time frame 300.

  As an example, the frame detection unit 310 may be a 1 [Byte] bit string of “01010001”. In this case, the second board 120 can detect the time frame 300 by detecting the bit string “01010001” from the received signal from the first board 110 and can acquire the time information 320.

  The time information 320 is information indicating the current time (for example, year, month, day, hour, minute, second,...) At the time inside the first board 110. As an example, the time information 320 may be a 10 [byte] bit string in which the least significant bit is 500 [psec], the second least significant bit is 1 [nsec],.

  For example, the first board 110 periodically transmits a time frame 300 shown in FIG. However, the time frame transmission method by the first board 110 is not limited to this. For example, the first board 110 may periodically perform an operation of continuously transmitting a plurality of time information 320 following the frame detection unit 310.

(Time frame transmission / reception timing in the synchronization system according to the embodiment)
FIG. 4 is a diagram illustrating an example of transmission / reception timing of a time frame in the synchronization system according to the embodiment. In FIG. 4, the horizontal direction indicates time. Time 410 is the time inside the first board 110. However, in FIG. 4, the time 410 indicates only the time (8 [ns], 16 [ns], 24 [ns],...) In units of 8 [ns].

  The reference clock 420 is a reference clock inside the first board 110. For example, the reference clock 420 is a reference clock generated by the reference clock generation circuit 111 shown in FIG.

  The time frame 430 is a time frame that the first board 110 transmits (sends) to the second board 120. In the example illustrated in FIG. 4, the time frame 430 is transmitted at 8 [ns] at time 410. Therefore, in the time frame 430, information indicating 8 [ns] is stored as time information following “01010001” corresponding to the frame detection unit 310 illustrated in FIG. However, in the example illustrated in FIG. 4, the time information is not corrected based on the transmission delay amount between the first board 110 and the second board 120.

  The time frame 440 is a time frame that the second board 120 receives from the first board 110 and returns to the first board 110. The timing of the time frame 440 received by the second board 120 is delayed by the transmission delay amount between the first board 110 and the second board 120 with respect to the timing of the time frame 430 transmitted by the first board 110.

  The time frame 450 is a time frame that the first board 110 receives from the second board 120. The round trip transmission delay amount 401 is the time from when the first board 110 transmits the time frame 430 to when the first board 110 receives the time frame 450, that is, the round trip between the first board 110 and the second board 120. Transmission delay amount.

  The phase difference 402 is a phase difference between the reference clock 420 of the first board 110 and the time frame 450 received by the first board 110 from the second board 120. The phase difference 402 occurs due to, for example, a shift between the time frame delay amount and the clock delay. For example, even in a configuration in which a clock is extracted by CDR, the data phase and the clock phase do not necessarily match, and a phase difference 402 is generated. This is because, in the CDR, the clock is reproduced following the data change, but the clock edge is generated not at the data change point but at a phase that reliably penetrates the data. Therefore, a phase difference 402 occurs between the time frame and the reference clock that latches the time frame. Such a phase difference similarly occurs when the second board 120 latches the time frame from the first board 110.

  The first board 110 reciprocates based on time information (8 [ns]) obtained by latching the time frame 450 with the reference clock 420 and the phase difference 402 between the reference clock 420 and the time frame 450. The transmission delay amount 401 can be calculated with high accuracy.

(Clock shift circuit and reception timing measurement circuit according to the embodiment)
FIG. 5 is a diagram illustrating an example of the clock shift circuit and the reception timing measurement circuit according to the embodiment. For example, the clock shift circuit 114 and the reception timing measurement circuit 115 shown in FIG. 1 can be realized by the clock shift circuit 501 and the reception timing measurement circuit 502 shown in FIG.

  The clock shift circuit 501 shifts (delays) the 125 [MHz] reference clock input from the reference clock generation circuit 111 (see, for example, FIG. 1) 15 times by 0.5 [ns]. As a result, 16 clocks are generated, each shifted by 0 [ns] (no shift), 0.5 [ns], 1 [ns],... 7.5 [ns]. The clock shift circuit 501 outputs the 16 clocks generated by the clock shift to the reception timing measurement circuit 502.

  The reception timing measurement circuit 502 includes a time information reception circuit 510, 16 8-stage shift registers (8-stage shift registers 521 to 536), 16 frame detection sections (frame detection sections 541 to 556), and a phase determination Part 560.

  A time frame returned from the second board 120 (see, for example, FIG. 1) is input to the time information receiving circuit 510. The time information receiving circuit 510 receives a 0 [ns] -shifted clock (that is, a reference clock) among the clocks output from the clock shift circuit 501. The time information receiving circuit 510 receives time information by latching the input time frame with the input 0 [ns] shift clock. Then, the time information receiving circuit 510 outputs the received time information to the correction circuit 113 (see, for example, FIG. 1).

  Each of the 8-stage shift registers 521 to 536 receives the time frame returned from the second board 120 (see, for example, FIG. 1). The 8-stage shift registers 521 to 536 receive clocks having different shift amounts output from the clock shift circuit 501. For example, a clock of 0 [ns] shift is input to the 8-stage shift register 521. The 8-stage shift register 522 receives a clock of 0.5 [ns] shift. The 8-stage shift register 536 receives a clock of 7.5 [ns] shift.

  The 8-stage shift register 521 includes eight flip-flops (flip-flops 571 to 578). A time frame is input to the first flip-flop 571. The flip-flops 571 to 578 are connected in series with each other. For example, the output of the flip-flop 571 is connected to the input of the flip-flop 572, and the output of the flip-flop 572 is connected to the input of the flip-flop 573.

  Each of the flip-flops 571 to 578 latches an input value by a clock of 0 [ns] shift input to the 8-stage shift register 521. Thereby, the flip-flops 571 to 578 hold an 8-bit value obtained by latching the time frame with a clock of 0 [ns] shift. The 8-stage shift register 521 outputs each value held by the flip-flops 571 to 578 to the frame detection unit 541.

  Although the 8-stage shift register 521 has been described, the 8-stage shift registers 522 to 536 similarly hold 8-bit values obtained by latching the time frame with clocks having different shift amounts, and each of the held values is a frame detection unit. Output to 542 to 556. For example, the flip-flop 572 holds an 8-bit value obtained by latching the time frame with a clock of 0.5 [ns] shift, and outputs each held value to the frame detection unit 542.

  The frame detection unit 541 detects a time frame based on each value output from the 8-stage shift register 521. Similarly, the frame detection units 542 to 556 detect time frames based on the values output from the 8-stage shift registers 522 to 536, respectively. The detection of the time frame by the frame detection units 541 to 556 will be described later (see, for example, FIGS. 6 and 7). Frame detection units 541 to 556 output the detection result of the time frame to phase determination unit 560.

  The phase determination unit 560 determines the phase difference between the reference clock and the time frame based on the detection results output from the frame detection units 541 to 556. The determination of the phase difference by the phase determination unit 560 will be described later (see, for example, FIG. 7). Phase determination unit 560 outputs phase difference information indicating the determined phase difference to correction circuit 113 (see, for example, FIG. 1).

  The case where the clock shift circuit 114 and the reception timing measurement circuit 115 of the first board 110 shown in FIG. 1 are realized by the clock shift circuit 501 and the reception timing measurement circuit 502 has been described. Similarly, the clock shift circuit 123 and the reception timing measurement circuit 124 of the second board 120 shown in FIG. 1 can be realized by the clock shift circuit 501 and the reception timing measurement circuit 502, respectively.

  In this case, the clock shift circuit 501 shifts (delays) the 125 [MHz] reference clock input from the reference clock generation circuit 122 (see, for example, FIG. 1) 15 times by 0.5 [ns]. The time frame transmitted from the first board 110 (see, for example, FIG. 1) is input to the time information receiving circuit 510 and the 8-stage shift registers 521 to 536. Further, the time information receiving circuit 510 outputs the received time information to the counter 125 (for example, see FIG. 1). Phase determination unit 560 outputs phase difference information indicating the determined phase difference to counter 125 (see, for example, FIG. 1).

(Shift register value in the 8-stage shift register according to the embodiment)
FIG. 6 is a diagram illustrating an example of shift register values in the 8-stage shift register according to the embodiment. In FIG. 6, the same parts as those shown in FIG. In FIG. 6, the horizontal direction indicates time.

  The shift register value 601 indicates each value held by the 8-stage shift register 521 corresponding to a clock of 0 [ns] shift in the vicinity of “01” at the end in the frame detection unit 310. Similarly, the shift register values 602 to 616 indicate the values held by the 8-stage shift registers 522 to 536 in the vicinity of “01” at the end in the frame detection unit 310, respectively.

  In other words, the shift register values 601 to 616 are as shown in FIG. The phase determination timing 620 is a timing at which the phase determination unit 560 determines a phase, and is a rising timing of the last two bits (“01”) in the frame detection unit 310.

(Phase determination based on shift register value according to embodiment)
FIG. 7 is a diagram illustrating an example of the phase determination based on the shift register value according to the embodiment. The table 700 illustrated in FIG. 7 includes shift register values 601 to 616 at the phase determination timing 620 illustrated in FIG. 6 and frame detection results (OK / NG) by the frame detection units 541 to 556 based on the shift register values 601 to 616. , Indicate.

  The frame detection units 541 to 556 output “OK” as the detection result when the shift register values 601 to 616 match the frame detection unit 310 (“01010001”), respectively, and “NG” as the detection result when they do not match. Is output. In the example illustrated in FIG. 7, the frame detection units 541 to 548 output “NG” as the detection result, and the frame detection units 549 to 556 output “OK” as the detection result.

  For example, the phase determination unit 560 checks the detection results of the frame detection units 541 to 556 in ascending order of the corresponding shift amount, and detects the frame that outputs “OK” at the beginning of the frame detection units 541 to 556. Specify the part. In the example illustrated in FIG. 7, the phase determination unit 560 identifies a frame detection unit (frame detection unit 549) corresponding to a 4 [ns] shift.

  Then, the phase determination unit 560 determines the shift amount corresponding to the identified frame detection unit as a phase difference between the reference clock and the time frame. In the example illustrated in FIG. 7, the phase determination unit 560 determines 4 [ns], which is a shift amount corresponding to the identified frame detection unit, as a phase difference between the reference clock and the time frame, and 4 [ns]. Is output to the correction circuit 113.

  As described above, the reception timing measurement circuit 502 determines whether the time frame latched by the own device and the reference clock of the own device are based on a plurality of clocks generated by the clock shift circuit 501 delaying the reference clock of the own device. The phase difference between them can be determined. For example, the reception timing measurement circuit 502 determines a phase difference based on a comparison between each latch result of a time frame based on a plurality of clocks from the clock shift circuit 501 and a predetermined pattern (frame detection unit 310) included in the time frame. can do.

(Calculation of transmission delay)
Next, calculation of the transmission delay amount by the first board 110 will be described. For example, as shown in FIG. 4, the time information of the time frame returned by the second board 120 and received by the first board 110 is 8 [ns], and the time at which the first board 110 received the time frame. Is 16 [ns]. Further, as shown in FIG. 7, it is assumed that the phase difference between the reference clock determined by the first board 110 and the time frame is 4 [ns]. In this case, the first board 110 calculates the transmission delay amount between the first board 110 and the second board 120 as (16−8 + 4) ÷ 2 = 6 [ns].

  Thus, the first board 110 receives the time (16 [ns]) when the time information is received from the time frame returned from the second board 120, the time (8 [ns]) indicated by the time information, A value half the value obtained by adding the phase difference determination result (4 [ns]) to the difference is calculated. Thereby, the transmission delay amount between the first board 110 and the second board 120 can be calculated with high accuracy.

(Correction of time information by the first board according to the embodiment)
FIG. 8 is a diagram illustrating an example of correction of time information by the first board according to the embodiment. In FIG. 8, the same parts as those shown in FIG. A reference clock 810 shown in FIG. 8 is a reference clock for the second board 120. As described above, it is assumed that the reference clock 810 of the second board 120 is frequency-synchronized with the reference clock 420 of the first board 110.

  When the first board 110 calculates the transmission delay amount between the first board 110 and the second board 120 based on the time frame returned from the second board 120, the time information transmitted to the second board 120 indicates The time is corrected by the transmission delay amount.

  In the example illustrated in FIG. 8, the first board 110 calculates 6 [ns] as a transmission delay amount between the first board 110 and the second board 120. In this case, the first board 110 corrects the time indicated by the time information in the time frame 430 transmitted to the second board 120 from the original 8 [ns] to 8 + 6 = 14 [ns].

  Accordingly, the second board 120 can receive the time frame 440 including the time information corrected by the transmission delay amount between the first board 110 and the second board 120. However, between the time indicated by the time information obtained by the second board 120 latching the time frame 440 with the reference clock 810 and the current time in the first board 110, the time frame 440 and the reference clock 810 There is a shift corresponding to the phase difference 801 between them.

  On the other hand, the second board 120 determines the phase difference 801 between the time frame 440 and the reference clock 810 based on each clock generated by delaying the reference clock of the second board 120, and obtains it from the time frame 440. The phase difference 801 is subtracted from the time information. In the example illustrated in FIG. 8, it is assumed that the second board 120 determines that the phase difference 801 is 2 [ns]. In the example illustrated in FIG. 8, the time information acquired from the time frame 440 by the second board 120 is 14 [ns]. Therefore, the second board 120 calculates 14-2 = 12 [ns] as the current time in the first board 110.

  The first board 110 does not directly correct the time information of the time frame 430 transmitted to the second board 120, but the time information before correction (for example, 8 [ns]) and a correction value ( For example, 6 [ns]) may be transmitted by a time frame. Also in this case, the second board 120 can obtain the corrected time information by the calculation based on the time information and the correction value.

(Synchronization between boards according to the embodiment)
FIG. 9 is a diagram illustrating an example of synchronization between the boards according to the embodiment. In FIG. 9, the same parts as those shown in FIG. The second board 120 generates time information based on the reference clock 810 of the second board 120 based on the calculated current time of the first board 110. A time 910 illustrated in FIG. 9 is a time indicated by the time information generated by the counter 125 of the second board 120 based on the current time of the first board 110.

  As shown in FIG. 9, according to the present embodiment, even if the timing between the reference clock 420 of the first board 110 and the reference clock 810 of the second board 120 is not synchronized, the first board 110 The time 410 and the time 910 of the second board 120 can be synchronized.

(Apparatus applying the synchronization system according to the embodiment)
FIG. 10 is a diagram illustrating an example of an apparatus to which the synchronization system according to the embodiment is applied. The synchronization system 100 shown in FIG. 1 can be applied to the apparatus system 1000 shown in FIG. 10, for example. The device system 1000 includes devices 1010 and 1020, for example. Each of the devices 1010 and 1020 has a shelf configuration capable of connecting a plurality of card-type devices. The apparatus 1010 includes a master processing card 1011 and a slave processing card 1012. The apparatus 1020 includes a master processing card 1021 and a slave processing card 1022.

  Here, a case where the synchronization system 100 is applied to synchronization between cards in the apparatus 1010 will be described. The slave processing card 1012 of the apparatus 1010 includes a correction processing unit 1012a, an internal clock 1012b, a PTP processing unit 1012c, and a PKT processing unit 1012d.

  The PKT processing unit 1012d transmits and receives PTP (Precision Time Protocol) packets to and from other devices connected to the slave processing card 1012. The PTP processing unit 1012c performs PTP processing based on IEEE 1588 by transmitting and receiving PTP packets to and from other devices connected to the slave processing card 1012 via the PKT processing unit 1012d, and the internal clock 1012b Synchronize with the internal clock. The internal clock 1012b is a clock that measures time in the slave processing card 1012.

  The correction processing unit 1012a synchronizes the internal clock 1011c of the master processing card 1011 with the internal clock 1012b by transmitting a time frame storing time information based on the internal clock 1012b to the master processing card 1011. Thereby, the time synchronization between the slave processing card 1012 and the master processing card 1011 can be performed.

  The master processing card 1011 includes a PKT processing unit 1011a, a PTP processing unit 1011b, an internal clock 1011c, and a correction processing unit 1011d. The correction processing unit 1011d synchronizes the internal clock 1011c with the internal clock 1012b of the slave processing card 1012 based on the time frame transmitted from the correction processing unit 1012a of the slave processing card 1012. The internal clock 1011c is a clock that measures time in the master processing card 1011.

  The PTP processing unit 1011b performs PTP processing based on IEEE 1588 by transmitting and receiving PTP packets to and from the device 1020 connected to the device 1010 via the PKT processing unit 1011a, and the internal clock of the device 1020 is set to the internal clock 1011c. Synchronize with. The PKT processing unit 1011a transmits and receives PTP packets to and from the device 1020 connected to the master processing card 1011.

  When the synchronization system 100 is applied to the device system 1000, for example, the first board 110 can be applied to the internal clock 1012b and the correction processing unit 1012a of the slave processing card 1012. Further, the second board 120 can be applied to the internal clock 1011c and the correction processing unit 1011d of the master processing card 1011. Thus, time synchronization between the cards can be accurately performed with the internal clock 1012b and the correction processing unit 1012a as a master and the internal clock 1011c and the correction processing unit 1011d as a slave.

  Each unit of the master processing card 1011 and the slave processing card 1012 can be realized by a digital circuit, for example. For example, the PKT processing unit 1011a, the internal clock 1011c, and the correction processing unit 1011d of the master processing card 1011 can be realized by an FPGA (Field Programmable Gate Array) or the like. The PTP processing unit 1011b of the master processing card 1011 can be realized by a DSP (Digital Signal Processor) or the like.

  Similarly, the PKT processing unit 1012d, the internal clock 1012b, and the correction processing unit 1012a of the slave processing card 1012 can be realized by an FPGA or the like. Further, the PTP processing unit 1012c of the slave processing card 1012 can be realized by a DSP or the like.

  As described above, according to the synchronization system 100 according to the embodiment, the time frame is determined based on the transmission delay amount between the devices obtained by reciprocating the time frame between the devices (between the first board 110 and the second board 120). By correcting this information, synchronization between devices can be achieved.

  In addition, a plurality of clocks generated by delaying the reference clock are used to determine a phase difference between the received time frame and a reference clock that latches the received time frame, and the determination result is used as an apparatus. The amount of transmission delay can be calculated with high accuracy. As a result, even if there is a phase difference between the received time frame and the reference clock, the transmission delay amount between the devices can be calculated with higher accuracy than the frequency of the reference clock, and synchronization between the devices can be accurately performed. . For this reason, it is possible to synchronize the devices accurately without increasing the frequency of the reference clock (clock frequency).

  As described above, according to the transmission device and the synchronization method, synchronization between devices can be accurately performed without increasing the clock frequency.

  For example, conventionally, time synchronization is used to control a device at a critical timing in various fields including communication equipment. Also in the field of networks, IEEE 1588 standardizes a method for realizing packet-based time synchronization. As such a time synchronization method, for example, a method of synchronizing (matching) the time between devices by transmitting and receiving time packets can be considered.

  Here, to match the time accurately, naturally it is necessary to consider transmission delays between multiple boards in the same device, and it is mounted on each board to set the time accurately. It is also required to correct the time by calculating the propagation delay of the device.

  In particular, in a micro time world such as a semiconductor device, time management in units of microseconds or nanoseconds may be required. In order to perform such time management with high accuracy, time synchronization with high accuracy is required, and it is required to accurately manage transmission delay, propagation delay in the device, and the like. For example, if the time is not exactly the same, when a failure occurs in a plurality of boards (for example, the master processing card 1011 and the slave processing card 1012 shown in FIG. 10) in the same apparatus, it becomes a reference for each board. The time will be different. For this reason, there arises a problem that the failure occurrence order cannot be accurately grasped from the failure log. If this is a large system, it will be more difficult to analyze the failure because tens or hundreds of devices are connected.

  In general, in order to increase the accuracy of time (to reduce the correction error), it is conceivable to increase the transmission speed to reduce the propagation delay or increase the processing speed. However, when the transmission speed and processing speed are increased, for example, the design of the apparatus becomes complicated, and there is a problem that the difficulty of realization increases in terms of increased power consumption, signal attenuation, noise countermeasures, and high-frequency countermeasures. There is also a problem that an expensive device corresponding to high-speed transmission and high-speed processing is required. Furthermore, for example, a device operating at 1 [GHz] is required to precisely adjust the time to the nanosecond unit, and it is difficult to realize a device operating at 1 [GHz] with the current technology.

  Further, in the prior art, since a shift in the clock phase of each device is not taken into consideration, a correction error corresponding to a maximum of clock cycles occurs. That is, in the prior art, time is synchronized only with clock frequency accuracy, and it is necessary to use a high-frequency clock in order to realize highly accurate time synchronization. However, if a high-frequency clock is used, the degree of difficulty in realizing the device increases as described above, and the time synchronization accuracy that can be realized is limited.

  In contrast, according to the above-described embodiment, time synchronization can be performed by correcting the information of the time frame based on the transmission delay amount obtained by reciprocating the time frame between the devices. Also, using multiple clocks generated by delaying the reference clock that latches the received time frame, the phase difference between the reference clock and the received time frame is determined, and the transmission delay amount is higher than the clock frequency. Can be obtained. As a result, the devices can be accurately synchronized without increasing the clock frequency.

  The following additional notes are disclosed with respect to the above-described embodiments.

(Supplementary Note 1) In a transmission apparatus that synchronizes a clock of the other transmission apparatus with a clock of the own apparatus by transmitting a frame including time information based on the clock of the own apparatus to another transmission apparatus.
The frame transmitted by the own device, which is returned by the other transmission device before being latched by the reference clock of the other transmission device before the frame is latched by the reference clock of the own device. A receiving unit for receiving information;
A determination unit for determining a phase difference between the frame latched by the reception unit and the reference clock of the own device based on a plurality of clocks generated by delaying the reference clock of the own device;
Based on the time when the time information was received by the receiving unit, the time information received by the receiving unit, and the phase difference determined by the determining unit, the own device and the other transmission device A calculation unit for calculating a transmission delay amount of the frame during
A correction unit that corrects the time indicated by the time information included in the frame transmitted from the own device to the other transmission device based on the transmission delay amount calculated by the calculation unit;
A transmission apparatus comprising:

(Additional remark 2) The said determination part determines the said phase difference by comparing each latch result of the said flame | frame by these several clocks, and the predetermined pattern contained in the said flame | frame. Transmission equipment.

(Additional remark 3) The said calculation part is the said position determined by the said determination part to the difference of the time which the said time information was received by the said reception part, and the time which the said time information received by the said reception part shows. The transmission apparatus according to appendix 1 or 2, wherein the transmission delay amount is calculated by calculating a half value of a value obtained by adding a phase difference.

(Additional remark 4) The said correction | amendment part is added to the said frame which the own apparatus transmits to the said other transmission apparatus so that the time delayed by the said transmission delay amount may be shown from the time which the said time information based on the time clock of the said apparatus shows. The transmission apparatus according to any one of appendices 1 to 3, wherein the time indicated by the time information included is corrected.

(Supplementary Note 5) A frame including time information based on the clock of the other transmission device transmitted from the other transmission device and before being latched by the reference clock of the own device is returned to the other transmission device. A return part to
Latching the frame transmitted from the other transmission device including the time information indicating the time corrected by the other transmission device based on the frame returned by the return unit with the reference clock of the own device. A receiving unit for receiving the time information by:
A determination unit for determining a phase difference between the frame latched by the reception unit and the reference clock of the own device based on a plurality of clocks generated by delaying the reference clock of the own device;
A synchronization unit that synchronizes the clock of the own device with the clock of the other transmission device based on the time information received by the reception unit and the phase difference determined by the determination unit;
A transmission apparatus comprising:

(Supplementary Note 6) The first transmission device transmits a frame including time information based on the clock of the first transmission device to the second transmission device,
The second transmission device returns the frame transmitted by the first transmission device before being latched by the reference clock of the second transmission device to the first transmission device;
The first transmission device receives the time information by latching the frame returned by the second transmission device with a reference clock of the first transmission device;
Based on a plurality of clocks generated by the first transmission device delaying a reference clock of the first transmission device, the frame latched by the first transmission device and a reference clock of the first transmission device Determine the phase difference between
The frame between the first transmission device and the second transmission device based on the time when the first transmission device received the time information, the received time information, and the determined phase difference. Calculate the transmission delay amount of
The first transmission device corrects the time indicated by the time information included in the frame transmitted to the second transmission device based on the calculated transmission delay amount,
The second transmission device receives the time information by latching the frame transmitted by the first transmission device with a reference clock of the second transmission device;
Based on a plurality of clocks generated by the second transmission device delaying the reference clock of the second transmission device, the frame latched by the second transmission device and the reference clock of the second transmission device Determine the phase difference between
The second transmission device synchronizes the clock of the second transmission device with the clock of the first transmission device based on the received time information and the determined phase difference;
A synchronization method characterized by the above.

100 synchronization system 110 first board 111, 122 reference clock generation circuit 112, 125 counter 113 correction circuit 114, 123, 501 clock shift circuit 115, 124, 502 reception timing measurement circuit 116 addition unit 117 difference calculation unit 118 division unit 120 first 2-board 121 return unit 119, 126 buffer 300, 430, 440, 450 time frame 310, 541-556 frame detection unit 320 time information 401 round-trip transmission delay amount 402, 801 phase difference 410, 910 time 420, 810 reference clock 510 time Information receiving circuit 521 to 536 Eight stage shift register 560 Phase determination unit 571 to 578 Flip-flop 601 to 616 Shift register value 620 Phase determination timing 700 Table 1000 Device System 1010, 1020 Device 1011, 1021 Master Processing Card 1011a, 1012d PKT Processing Unit 1011b, 1012c PTP Processing Unit 1011c, 1012b Internal Clock 1011d, 1012a Correction Processing Unit 1012, 1022 Slave Processing Card

Claims (5)

In the transmission apparatus that synchronizes the clock of the other transmission apparatus with the clock of the own apparatus by transmitting a frame including time information based on the clock of the own apparatus to the other transmission apparatus.
The frame transmitted by the own device, which is returned by the other transmission device before being latched by the reference clock of the other transmission device before the frame is latched by the reference clock of the own device. A receiving unit for receiving information;
A determination unit for determining a phase difference between the frame latched by the reception unit and the reference clock of the own device based on a plurality of clocks generated by delaying the reference clock of the own device;
Based on the time when the time information was received by the receiving unit, the time information received by the receiving unit, and the phase difference determined by the determining unit, the own device and the other transmission device A calculation unit for calculating a transmission delay amount of the frame during
A correction unit that corrects the time indicated by the time information included in the frame transmitted from the own device to the other transmission device based on the transmission delay amount calculated by the calculation unit;
A transmission apparatus comprising:   The transmission apparatus according to claim 1, wherein the determination unit determines the phase difference by comparing each latch result of the frame based on the plurality of clocks with a predetermined pattern included in the frame.   The calculation unit adds the phase difference determined by the determination unit to a difference between the time when the time information is received by the reception unit and the time indicated by the time information received by the reception unit. The transmission apparatus according to claim 1, wherein the transmission delay amount is calculated by calculating a half value. A frame that includes time information based on the clock of the other transmission device, transmitted from the other transmission device, and returns a frame before latching with the reference clock of the own device to the other transmission device; ,
Latching the frame transmitted from the other transmission device including the time information indicating the time corrected by the other transmission device based on the frame returned by the return unit with the reference clock of the own device. A receiving unit for receiving the time information by:
A determination unit for determining a phase difference between the frame latched by the reception unit and the reference clock of the own device based on a plurality of clocks generated by delaying the reference clock of the own device;
A synchronization unit that synchronizes the clock of the own device with the clock of the other transmission device based on the time information received by the reception unit and the phase difference determined by the determination unit;
A transmission apparatus comprising: The first transmission device transmits a frame including time information based on the clock of the first transmission device to the second transmission device;
The second transmission device returns the frame transmitted by the first transmission device before being latched by the reference clock of the second transmission device to the first transmission device;
The first transmission device receives the time information by latching the frame returned by the second transmission device with a reference clock of the first transmission device;
Based on a plurality of clocks generated by the first transmission device delaying a reference clock of the first transmission device, the frame latched by the first transmission device and a reference clock of the first transmission device Determine the phase difference between
The frame between the first transmission device and the second transmission device based on the time when the first transmission device received the time information, the received time information, and the determined phase difference. Calculate the transmission delay amount of
The first transmission device corrects the time indicated by the time information included in the frame transmitted to the second transmission device based on the calculated transmission delay amount,
The second transmission device receives the time information by latching the frame transmitted by the first transmission device with a reference clock of the second transmission device;
Based on a plurality of clocks generated by the second transmission device delaying the reference clock of the second transmission device, the frame latched by the second transmission device and the reference clock of the second transmission device Determine the phase difference between
The second transmission device synchronizes the clock of the second transmission device with the clock of the first transmission device based on the received time information and the determined phase difference;
A synchronization method characterized by the above.

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