CN111027108B - Sequential logic safety detection method and device for low-speed synchronous serial bus - Google Patents
Sequential logic safety detection method and device for low-speed synchronous serial bus Download PDFInfo
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- CN111027108B CN111027108B CN201910742737.3A CN201910742737A CN111027108B CN 111027108 B CN111027108 B CN 111027108B CN 201910742737 A CN201910742737 A CN 201910742737A CN 111027108 B CN111027108 B CN 111027108B
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- 238000005859 coupling reaction Methods 0.000 claims abstract description 30
- 238000004891 communication Methods 0.000 claims abstract description 25
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/82—Protecting input, output or interconnection devices
- G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
- G06F11/327—Alarm or error message display
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F21/577—Assessing vulnerabilities and evaluating computer system security
Abstract
The embodiment of the invention provides a sequential logic safety detection method and device for a low-speed synchronous serial bus, which are used for solving the problem that the prior art cannot detect sequential logic loopholes or even hardware Trojan in a bus transceiver. The method comprises the following steps: coupling the simulated low-speed synchronous serial bus transceiver with the low-speed synchronous serial bus, simulating the communication of the low-speed synchronous serial bus, and obtaining all synchronous time sequence signals of the bus communication; coupling the simulated low-speed synchronous serial bus transceiver with the bus transceiver, and receiving a synchronous time sequence signal of the bus transceiver; comparing all synchronous time sequence signals of the bus communication with synchronous time sequence signals of the bus transceiver, and if the state of the received synchronous time sequence signals of the bus transceiver is abnormal, the bus transceiver has a time sequence logic loophole or a hardware Trojan horse.
Description
Technical Field
The present invention relates to the field of computer hardware security, and in particular, to a method and apparatus for detecting sequential logic security of a low-speed synchronous serial bus.
Background
At present, the low-speed synchronous serial bus has the advantages of less signal lines, strong anti-interference capability, higher data transmission rate than an asynchronous serial bus and the like, and is widely applied to Central Processing Units (CPU), micro Control Units (MCU) or peripheral connection. In general, a chip bus transceiver connected to a bus belongs to a synchronous sequential logic circuit, and if a sequential logic hole exists in the chip bus transceiver, even if a hardware Trojan is preset, the chip bus transceiver is possibly activated under the triggering of a specific condition, so that the whole bus communication is seriously affected, and the chip bus transceiver becomes a serious hardware safety hidden trouble.
Disclosure of Invention
The embodiment of the invention provides a sequential logic safety detection method and device for a low-speed synchronous serial bus, which are used for solving the problem that the prior art cannot detect sequential logic loopholes or even hardware Trojan in a bus transceiver.
Based on the above-mentioned problems, the method for detecting sequential logic security of a low-speed synchronous serial bus according to the embodiment of the present invention includes:
coupling the simulated low-speed synchronous serial bus transceiver with the low-speed synchronous serial bus, simulating the communication of the low-speed synchronous serial bus, and obtaining all synchronous time sequence signals of the bus communication; coupling the simulated low-speed synchronous serial bus transceiver with the bus transceiver, and receiving a synchronous time sequence signal of the bus transceiver; comparing all synchronous time sequence signals of the bus communication with synchronous time sequence signals of the bus transceiver, and if the state of the received synchronous time sequence signals of the bus transceiver is abnormal, the bus transceiver has a time sequence logic loophole or a hardware Trojan horse.
Furthermore, the simulation low-speed synchronous serial bus transceiver can realize synchronous time sequence signal simulation through a singlechip or a programmable logic device.
Further, the simulation low-speed synchronous serial bus transceiver realizes synchronous time sequence signal simulation through a singlechip, and specifically comprises the following steps: the universal parallel I/O interface pin of the singlechip is coupled with the low-speed synchronous serial bus, and the synchronous timing sequence signal of the synchronous low-speed serial bus is simulated through the singlechip software;
the simulation low-speed synchronous serial bus transceiver realizes synchronous time sequence signal simulation through a programmable logic device, and specifically comprises the following steps: the programmable logic device I/O interface pins are coupled to the low-speed synchronous serial bus, simulate synchronous low-speed serial bus synchronous time sequence signals through hardware description language, and allocate the I/O pins correspondingly coupled to the low-speed synchronous serial bus as simulated transceiver hardware I/O.
Further, the low-speed synchronous serial bus includes a two-wire serial bus or a full duplex synchronous serial bus.
Further, if the low-speed synchronous serial bus is a two-wire serial bus, the specific way of simulating the coupling between the low-speed synchronous serial bus transceiver and the bus transceiver is as follows: the method comprises the steps of coupling a simulated low-speed synchronous serial bus transceiver serial data line signal with a serial data line pin of a two-wire serial bus transceiver, coupling a simulated low-speed synchronous serial bus transceiver serial clock line signal with a pin of a serial clock line of the two-wire serial bus transceiver, and adding a pull resistor on the two-wire serial bus.
Further, if the low-speed synchronous serial bus is a full duplex synchronous serial bus, the simulated low-speed synchronous serial bus transceiver is coupled with the full duplex synchronous serial bus transceiver, specifically:
the simulated low speed synchronous serial bus transceiver input signal is coupled to the output pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver output signal is coupled to the input pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver timing signal is coupled to the timing signal pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver enable signal is coupled to the enable signal pin of the full duplex synchronous serial bus transceiver, and is grounded.
Further, if the state of the received synchronous time sequence signal of the bus transceiver is abnormal, an alarm is sent out, and detailed information of the time sequence signal is output; wherein the state exception comprises: all of the synchronization timing signals of the bus communication do not include the synchronization timing signals of the bus transceiver, the synchronization timing signals of the bus transceiver being advanced or shifted backward.
The embodiment of the invention provides a sequential logic safety detection device of a low-speed synchronous serial bus, which comprises the following components: a simulated low-speed synchronous serial bus transceiver coupled to the low-speed synchronous serial bus and coupled to the bus transceiver; the simulation low-speed synchronous serial bus transceiver can realize synchronous time sequence signal simulation through a singlechip or a programmable logic device, and specifically comprises the following steps: the universal parallel I/O interface pin of the singlechip is coupled with the low-speed synchronous serial bus, and the synchronous timing sequence signal of the synchronous low-speed serial bus is simulated through the singlechip software; alternatively, the programmable logic device I/O interface pins are coupled to the low-speed synchronous serial bus, and simulate the synchronous timing signals of the synchronous low-speed serial bus through the hardware description language, and the I/O pins correspondingly coupled to the low-speed synchronous serial bus are distributed as the simulated transceiver hardware I/O.
Further, the low-speed synchronous serial bus comprises a two-wire serial bus or a full duplex synchronous serial bus, and the specific connection mode of the simulated low-speed synchronous serial bus transceiver and the bus transceiver is as follows:
coupling the serial data line signal of the simulated low-speed synchronous serial bus transceiver with the serial data line pin of the two-wire serial bus transceiver, coupling the serial clock line signal of the simulated low-speed synchronous serial bus transceiver with the pin of the serial clock line of the two-wire serial bus transceiver, and grounding, and adding a pull resistor on the two-wire serial bus;
or, the simulated low speed synchronous serial bus transceiver input signal is coupled with the output pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver output signal is coupled with the input pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver timing signal is coupled with the timing signal pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver enable signal is coupled with the enable signal pin of the full duplex synchronous serial bus transceiver, and is grounded.
Further, the device also comprises an alarm module: and the system is used for sending out an alarm when the state of the received synchronous time sequence signal of the bus transceiver is abnormal and outputting detailed information of the time sequence signal.
Compared with the prior art, the sequential logic safety detection method and device for the low-speed synchronous serial bus provided by the embodiment of the invention have the advantages that at least the following effects are realized:
by coupling the simulated low-speed synchronous serial bus transceiver with the low-speed synchronous serial bus, simulating the communication of the low-speed synchronous serial bus, and obtaining all synchronous time sequence signals of the bus communication; coupling the simulated low-speed synchronous serial bus transceiver with the bus transceiver, and receiving a synchronous time sequence signal of the bus transceiver; comparing all synchronous time sequence signals of the bus communication with synchronous time sequence signals of the bus transceiver, and if the state of the received synchronous time sequence signals of the bus transceiver is abnormal, the bus transceiver has a time sequence logic loophole or a hardware Trojan horse. According to the embodiment of the invention, the simulation low-speed synchronous serial bus transceiver is connected with the peripheral pins of the chip, and the chip is not required to be disassembled, so that the possible sequential logic loopholes in the bus transceiver and even hardware Trojan can be effectively detected, and the cost of the chip-based computer hardware security detection is reduced.
Drawings
FIG. 1 is a flow chart of a method for detecting sequential logic security of a low-speed synchronous serial bus according to an embodiment of the present invention;
FIG. 2 is a flowchart of another method for detecting sequential logic security of a low-speed synchronous serial bus according to an embodiment of the present invention;
fig. 3 is a block diagram of another sequential logic security detection device for a low-speed synchronous serial bus according to an embodiment of the present invention.
Detailed Description
At present, in a computer system or an embedded computer system, a widely applied low-speed synchronous serial bus is connected with some medium-low-speed peripherals, some important configuration information is often stored or some important communication is carried out, if a sequential logic loophole or even a hardware trojan exists in a chip bus transceiver, once the sequential logic loophole or even the hardware trojan is activated, the potential safety hazard is invisible, and therefore, the embodiment of the invention provides a sequential logic safety detection method of the low-speed synchronous serial bus.
The following describes a specific implementation manner of a sequential logic security detection method and device for a low-speed synchronous serial bus according to an embodiment of the present invention with reference to the accompanying drawings.
The embodiment of the invention provides a sequential logic safety detection method of a low-speed synchronous serial bus, as shown in fig. 1, which specifically comprises the following steps:
s101, coupling a simulation low-speed synchronous serial bus transceiver with a low-speed synchronous serial bus, simulating communication of the low-speed synchronous serial bus, and obtaining all synchronous time sequence signals of bus communication;
the simulated low-speed synchronous serial bus transceiver can be realized based on a single chip Microcomputer (MCU) or a low-density programmable logic device, but the simulated low-speed synchronous serial bus transceiver cannot use a hardware transceiver which is self-contained on the MCU or the programmable logic device; wherein the low-density programmable logic device may be a Complex Programmable Logic Device (CPLD) or a small-scale Field Programmable Gate Array (FPGA).
S102, coupling the simulated low-speed synchronous serial bus transceiver with a bus transceiver, and receiving a synchronous time sequence signal of the bus transceiver;
wherein the bus transceiver must be properly connected to the bus and there is both a transmitter and a receiver, security detection is difficult to perform effectively if the transceiver itself is not functioning properly.
S103, comparing all synchronous time sequence signals of the bus communication with synchronous time sequence signals of the bus transceiver, and if the state of the synchronous time sequence signals of the received bus transceiver is abnormal, timing logic loopholes or hardware trojans exist in the bus transceiver.
According to the embodiment of the invention, the simulation low-speed synchronous serial bus transceiver is connected with the peripheral pins of the chip, and the chip is not required to be disassembled, so that the possible sequential logic loopholes in the bus transceiver and even hardware Trojan can be effectively detected, and the cost of the chip-based computer hardware security detection is reduced.
The embodiment of the invention also provides a sequential logic safety detection method of the low-speed synchronous serial bus, as shown in fig. 2, which specifically comprises the following steps:
s201, coupling a simulation low-speed synchronous serial bus transceiver with a low-speed synchronous serial bus, simulating communication of the low-speed synchronous serial bus, and obtaining all synchronous time sequence signals of bus communication;
the simulation low-speed synchronous serial bus transceiver can realize synchronous time sequence signal simulation through a singlechip or a programmable logic device, and specifically comprises the following steps: the universal parallel I/O interface pin of the singlechip is coupled with the low-speed synchronous serial bus, and the synchronous timing sequence signal of the synchronous low-speed serial bus is simulated through the singlechip software; or the programmable logic device I/O interface pin is coupled with the low-speed synchronous serial bus, and simulates synchronous time sequence signals of the synchronous low-speed serial bus through hardware description language, and distributes the I/O pin correspondingly coupled with the low-speed synchronous serial bus as simulated transceiver hardware I/O, wherein the hardware description language comprises: very high speed integrated circuit hardware description language (VHDL), verilog HDL.
S202, coupling the simulated low-speed synchronous serial bus transceiver with a bus transceiver, and receiving a synchronous time sequence signal of the bus transceiver;
wherein the low speed synchronous serial bus comprises a two-wire serial bus (I 2 C) Or full duplex synchronous serial bus (SPI). If the low-speed synchronous serial bus is a two-wire serial bus, the specific way of coupling the simulated low-speed synchronous serial bus transceiver and the bus transceiver is as follows: the method comprises the steps of coupling a simulated low-speed synchronous serial bus transceiver serial data line signal with a serial data line pin of a two-wire serial bus transceiver, coupling a simulated low-speed synchronous serial bus transceiver serial clock line signal with a pin of a serial clock line of the two-wire serial bus transceiver, and adding a pull resistor on the two-wire serial bus.
If the low-speed synchronous serial bus is a full duplex synchronous serial bus, the simulated low-speed synchronous serial bus transceiver is coupled with the full duplex synchronous serial bus transceiver, specifically: the simulated low speed synchronous serial bus transceiver input signal is coupled to the output pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver output signal is coupled to the input pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver timing signal is coupled to the timing signal pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver enable signal is coupled to the enable signal pin of the full duplex synchronous serial bus transceiver, and is grounded.
S203, judging whether the state of the received synchronous time sequence signal of the bus transceiver is abnormal; if yes, go to step 204; otherwise, the bus transceiver is secure;
the state exception includes: all of the synchronization timing signals of the bus communication do not include the synchronization timing signals of the bus transceiver, the synchronization timing signals of the bus transceiver being advanced or shifted backward.
S204, giving an alarm and outputting detailed information of the time sequence signal.
The simulation low-speed synchronous serial bus transceiver adopted by the embodiment of the invention can realize synchronous time sequence signal simulation through a singlechip or a programmable logic device, and has the advantages of simple method and low cost; meanwhile, the simulation low-speed synchronous serial bus transceiver is connected with the peripheral pins of the chip, and the chip is not required to be disassembled, so that sequential logic loopholes and even hardware trojans possibly existing in the bus transceiver can be effectively detected, and the cost and the operation difficulty of the chip-based computer hardware security detection are reduced.
The embodiment of the invention also provides a sequential logic safety detection device of the low-speed synchronous serial bus, as shown in fig. 3, comprising:
a simulated low speed synchronous serial bus transceiver 31 coupled to the low speed synchronous serial bus and coupled to the bus transceiver; the simulation low-speed synchronous serial bus transceiver can realize synchronous time sequence signal simulation through a singlechip or a programmable logic device, and the specific connection mode is as follows: the universal parallel I/O interface pin of the singlechip is coupled with the low-speed synchronous serial bus, and the synchronous timing sequence signal of the synchronous low-speed serial bus is simulated through the singlechip software; alternatively, the programmable logic device I/O interface pins are coupled to the low-speed synchronous serial bus, and simulate the synchronous timing signals of the synchronous low-speed serial bus through the hardware description language, and the I/O pins correspondingly coupled to the low-speed synchronous serial bus are distributed as the simulated transceiver hardware I/O.
The low-speed synchronous serial bus comprises a two-wire serial bus or a full duplex synchronous serial bus, and the specific connection mode of the simulation low-speed synchronous serial bus transceiver and the bus transceiver is as follows: coupling the serial data line signal of the simulated low-speed synchronous serial bus transceiver with the serial data line pin of the two-wire serial bus transceiver, coupling the serial clock line signal of the simulated low-speed synchronous serial bus transceiver with the pin of the serial clock line of the two-wire serial bus transceiver, and grounding, and adding a pull resistor on the two-wire serial bus; or, the simulated low speed synchronous serial bus transceiver input signal is coupled with the output pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver output signal is coupled with the input pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver timing signal is coupled with the timing signal pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver enable signal is coupled with the enable signal pin of the full duplex synchronous serial bus transceiver, and is grounded.
The device further comprises an alarm module 311: and the system is used for sending out an alarm when the state of the received synchronous time sequence signal of the bus transceiver is abnormal and outputting detailed information of the time sequence signal.
Those skilled in the art will appreciate that the drawing is merely a schematic representation of one preferred embodiment and that the modules or processes in the drawing are not necessarily required to practice the invention.
Those skilled in the art will appreciate that modules in an apparatus of an embodiment may be distributed in an apparatus of an embodiment as described in the embodiments, and that corresponding changes may be made in one or more apparatuses different from the present embodiment. The modules of the above embodiments may be combined into one module, or may be further split into a plurality of sub-modules.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. A sequential logic security detection method for a low-speed synchronous serial bus, comprising:
coupling the simulated low-speed synchronous serial bus transceiver with the low-speed synchronous serial bus, simulating the communication of the low-speed synchronous serial bus, and obtaining all synchronous time sequence signals of the bus communication;
coupling the simulated low-speed synchronous serial bus transceiver with the bus transceiver, and receiving a synchronous time sequence signal of the bus transceiver;
comparing all synchronous time sequence signals of the bus communication with synchronous time sequence signals of the bus transceiver, and if the state of the synchronous time sequence signals of the received bus transceiver is abnormal, timing logic loopholes or hardware trojans exist in the bus transceiver;
the simulation low-speed synchronous serial bus transceiver can realize synchronous time sequence signal simulation through a singlechip or a programmable logic device;
the simulation low-speed synchronous serial bus transceiver realizes synchronous time sequence signal simulation through a singlechip, and specifically comprises the following steps:
the universal parallel I/O interface pin of the singlechip is coupled with the low-speed synchronous serial bus, and the synchronous timing sequence signal of the synchronous low-speed serial bus is simulated through the singlechip software;
the simulation low-speed synchronous serial bus transceiver realizes synchronous time sequence signal simulation through a programmable logic device, and specifically comprises the following steps:
the programmable logic device I/O interface pins are coupled to the low-speed synchronous serial bus, simulate synchronous low-speed serial bus synchronous time sequence signals through hardware description language, and allocate the I/O pins correspondingly coupled to the low-speed synchronous serial bus as simulated transceiver hardware I/O.
2. The method of claim 1, wherein the low speed synchronous serial bus comprises a two-wire serial bus or a full duplex synchronous serial bus.
3. The method of claim 2, wherein if the low speed synchronous serial bus is a two-wire serial bus, the specific manner of coupling the emulated low speed synchronous serial bus transceiver to the bus transceiver is:
the method comprises the steps of coupling a simulated low-speed synchronous serial bus transceiver serial data line signal with a serial data line pin of a two-wire serial bus transceiver, coupling a simulated low-speed synchronous serial bus transceiver serial clock line signal with a pin of a serial clock line of the two-wire serial bus transceiver, and adding a pull resistor on the two-wire serial bus.
4. The method of claim 2, wherein if the low speed synchronous serial bus is a full duplex synchronous serial bus, emulating the coupling of the low speed synchronous serial bus transceiver with the full duplex synchronous serial bus transceiver is performed by:
the simulated low speed synchronous serial bus transceiver input signal is coupled to the output pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver output signal is coupled to the input pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver timing signal is coupled to the timing signal pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver enable signal is coupled to the enable signal pin of the full duplex synchronous serial bus transceiver, and is grounded.
5. The method of claim 1, wherein if the state of the received synchronous timing signal of the bus transceiver is abnormal, an alarm is issued and detailed information of the timing signal is outputted;
wherein the state exception comprises: all of the synchronization timing signals of the bus communication do not include the synchronization timing signals of the bus transceiver, the synchronization timing signals of the bus transceiver being advanced or shifted backward.
6. A sequential logic safety detection device of a low-speed synchronous serial bus is characterized by comprising
A simulated low-speed synchronous serial bus transceiver coupled to the low-speed synchronous serial bus and coupled to the bus transceiver;
the simulation low-speed synchronous serial bus transceiver can realize synchronous time sequence signal simulation through a singlechip or a programmable logic device, and the specific connection mode is as follows:
the universal parallel I/O interface pin of the singlechip is coupled with the low-speed synchronous serial bus, and the synchronous timing sequence signal of the synchronous low-speed serial bus is simulated through the singlechip software;
or, the programmable logic device I/O interface pin is coupled with the low-speed synchronous serial bus, and simulates synchronous timing signals of the synchronous low-speed serial bus through the hardware description language, and distributes the I/O pin correspondingly coupled with the low-speed synchronous serial bus as the hardware I/O of the simulation transceiver;
the device is specifically used for executing the following steps:
coupling the simulated low-speed synchronous serial bus transceiver with the low-speed synchronous serial bus, simulating the communication of the low-speed synchronous serial bus, and obtaining all synchronous time sequence signals of the bus communication;
coupling the simulated low-speed synchronous serial bus transceiver with the bus transceiver, and receiving a synchronous time sequence signal of the bus transceiver;
comparing all synchronous time sequence signals of the bus communication with synchronous time sequence signals of the bus transceiver, and if the state of the synchronous time sequence signals of the received bus transceiver is abnormal, timing logic loopholes or hardware trojans exist in the bus transceiver;
the simulation low-speed synchronous serial bus transceiver can realize synchronous time sequence signal simulation through a singlechip or a programmable logic device;
the simulation low-speed synchronous serial bus transceiver realizes synchronous time sequence signal simulation through a singlechip, and specifically comprises the following steps:
the universal parallel I/O interface pin of the singlechip is coupled with the low-speed synchronous serial bus, and the synchronous timing sequence signal of the synchronous low-speed serial bus is simulated through the singlechip software;
the simulation low-speed synchronous serial bus transceiver realizes synchronous time sequence signal simulation through a programmable logic device, and specifically comprises the following steps:
the programmable logic device I/O interface pins are coupled to the low-speed synchronous serial bus, simulate synchronous low-speed serial bus synchronous time sequence signals through hardware description language, and allocate the I/O pins correspondingly coupled to the low-speed synchronous serial bus as simulated transceiver hardware I/O.
7. The apparatus of claim 6, wherein: the low-speed synchronous serial bus comprises a two-wire serial bus or a full duplex synchronous serial bus, and the specific connection mode of the simulation low-speed synchronous serial bus transceiver and the bus transceiver is as follows:
coupling the serial data line signal of the simulated low-speed synchronous serial bus transceiver with the serial data line pin of the two-wire serial bus transceiver, coupling the serial clock line signal of the simulated low-speed synchronous serial bus transceiver with the pin of the serial clock line of the two-wire serial bus transceiver, and grounding, and adding a pull resistor on the two-wire serial bus;
or, the simulated low speed synchronous serial bus transceiver input signal is coupled with the output pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver output signal is coupled with the input pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver timing signal is coupled with the timing signal pin of the full duplex synchronous serial bus transceiver, the simulated low speed synchronous serial bus transceiver enable signal is coupled with the enable signal pin of the full duplex synchronous serial bus transceiver, and is grounded.
8. The apparatus of claim 6, further comprising an alarm module: and the system is used for sending out an alarm when the state of the received synchronous time sequence signal of the bus transceiver is abnormal and outputting detailed information of the time sequence signal.
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