CN200997135Y - Micro-controller structure of universal built-in synchronizing/asynchronizing transceiver - Google Patents
Micro-controller structure of universal built-in synchronizing/asynchronizing transceiver Download PDFInfo
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- CN200997135Y CN200997135Y CN 200620047703 CN200620047703U CN200997135Y CN 200997135 Y CN200997135 Y CN 200997135Y CN 200620047703 CN200620047703 CN 200620047703 CN 200620047703 U CN200620047703 U CN 200620047703U CN 200997135 Y CN200997135 Y CN 200997135Y
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Abstract
An embedded universal synchronous/asynchronous transceiver micro-control structure comprises an internal core, a peripheral device and a special function element respectively connected with a bus, which is characterized in that: The internal core is composed of a clock generator, a logic reset circuit, a memory and logic computing unit, all of which are respectively connected with a central processing unit and a bus. Wherein, the peripheral device is composed of an I/O terminal and an 8-bit 6-way analog/digital converter connected with the bus, a one-way capture module, a three-way timer, a comparison and pulse width modulation module and a universal synchronous/asynchronous transceiver jointly connected with the bus through a shared pin data cable. In addition, the special function element is composed of an element configuration position, a plate-based power-on reset circuit, an under-voltage resetting logic circuit, a watchdog timer and a dormancy mode, all of which respectively connected with the bus.
Description
Affiliated technical field
The utility model belongs to integrated circuit fields, especially relates to a kind of microcontroller architecture of built-in general-purpose synchronous asynchronous transceiver.
Background technology
With seeing deep-submicron CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor (CMOS)) the continuous progress of integrated circuit production technology, can be integrated in the microcontroller of complexity (MCU) kernel on the chip piece at present, leave enough silicon area simultaneously and be used to realize complicated storer and peripheral hardware logic.The method for designing and the structure that are used for high-end 32 and 64 bit CPUs in the past can effectively be used for 8 8-digit microcontroller systems at a low price now.Utilize these powerful and cheap microcontrollers to make the integrated level of system improve constantly, also strengthened the ability that microprocessor data is handled and flow process is controlled simultaneously greatly.Abundant peripheral hardware makes single-chip microcomputer to get in touch with the outside more easily, and can carry out internal task.
In recent years, increasing microcontroller applies to the every field of social life, and development and national economy has been played requisite facilitation.And reliability, anti-interference, dirigibility, the compatibility of microcontroller also had more and more higher requirement, at present for 8 OTP (One-TimeProgrammable on the market, disposable programmable) microcontroller exists following deficiency: (1) is for the four sections flowing structures in the two poles of the earth, each intermodule can't back up mutually, rely on mutually, more can not carry out pre-service and processing, have a strong impact on the antijamming capability of this structure data; (2) lack complete peripheral hardware, thereby limited chip and outside getting in touch, for subsequent design is made troubles.(3) system reliability, dirigibility remain further raising and reduce cost simultaneously.
Therefore just need a kind of novel microcontroller architecture and improve present system architecture, increase and adjustment peripherals and special functional module, make the weak point of traditional controller MCU make moderate progress.
Summary of the invention
The purpose of this utility model is to solve the deficiencies in the prior art, provides that a kind of antijamming capability is strong, the microcontroller architecture of low system cost, high reliability, flexible design.
The technical solution of the utility model is for providing a kind of microcontroller architecture of built-in general-purpose synchronous asynchronous transceiver, comprise the kernel, peripheral hardware and the special feature that link to each other with bus respectively separately, described kernel comprises: clock generator, reseting logic circuit, storer, ALU are connected with CPU (central processing unit) respectively, and above-mentioned device is connected with bus respectively again; Described peripheral hardware comprises: the input/output port that links to each other with bus, 86 road mould/number (A/D) converters, and one tunnel seizure, No. three timers, comparison are connected with bus by the common pin data line respectively with pulse width modulation module, Universal Synchronous Asynchronous Receiver Transmitter; Described special feature comprises: the time-delay reset that powers in cell configuration position, the sheet, under-voltage reset logic, WatchDog Timer, park mode, above device is connected with bus respectively.
Wherein, described storer comprises the data register of 2K * 16 a disposable programmable program storage and 224 * 8bit, data-carrier store is divided into two parts, specified register and general-purpose register, wherein specified register is 96 * 8bit, general-purpose register 128 * 8bit, the conventional data memory adopts single port, and asynchronous low-power consumption SRAM is realized.
Another technical scheme of the present utility model is for providing a kind of microcontroller architecture of built-in general-purpose synchronous asynchronous transceiver, comprise the kernel that links to each other with bus respectively separately, peripheral hardware and special feature, it is characterized in that: described kernel comprises the data random access memory, ALU, programmable counter links to each other with bus respectively, storehouse, interrupt handler links to each other with programmable counter respectively, the output terminal of programmable counter successively with program storage, order register, command decoder links to each other, the output terminal of command decoder connects the data random access memory respectively, ALU, reseting logic circuit, the output terminal of data random access memory is connected with ALU, work register links to each other with ALU, and oscillator links to each other with reseting logic circuit; Described peripheral hardware comprises: the input/output port that links to each other with bus, 86 road mould/number (A/D) converters, and one tunnel seizure, No. three timers, comparison are connected with bus by the common pin data line respectively with pulse width modulation module, Universal Synchronous Asynchronous Receiver Transmitter; Described special feature comprises: the time-delay reset that powers in cell configuration position, the sheet, under-voltage reset logic, WatchDog Timer, park mode, above device is connected with bus respectively.
Wherein, described storer comprises the data register of 2K * 16 a disposable programmable program storage and 224 * 8bit, data-carrier store is divided into two parts, specified register and general-purpose register, wherein specified register is 96 * 8bit, general-purpose register 128 * 8bit, the conventional data memory adopts single port, and asynchronous low-power consumption SRAM is realized.
Advantage of the present utility model is: 1, a kind of 8 novel digit RISC micro controllers are provided, so that instruction is not only complete, and can back up mutually, rely on mutually, data are carried out pre-service, thereby improve the antijamming capability of total.2, at some compact electric apparatus, adopted the low capacity reservoir, greatly reduce cost 3, more complete peripheral hardware is provided, so that single-chip microcomputer can get in touch with the outside more easily, and can carry out internal task.4, provide a large amount of special features,, improve system reliability, increase design flexibility so that reduce system cost.
Description of drawings
Fig. 1 is the structured flowchart of the utility model kernel inside;
Fig. 2 is the structured flowchart that the utility model kernel is connected with peripheral hardware.
Embodiment
Below in conjunction with accompanying drawing and specific embodiments, the utility model is further described.
The utility model can be divided into kernel, peripheral hardware, special feature three parts according to device.
Kernel comprises that the storer of clock generator, reseting logic, CPU (CPU (central processing unit)), ALU (ALU), device constitutes.
Above-mentioned CPU (central processing unit) adopts four sections streamlines of two-stage, Harvard's type structure, 16 program storage buses and 8 s' data bus is separated independent operating, by an instruction cycle is divided into 4 parts, produce four nonoverlapping orthogonal clocks (Q1, Q2, Q3, Q4) and be implemented in and promptly carry out last instruction in the instruction cycle and take out present instruction again, getting of an instruction referred to and and the execution of another instruction in the same cycle, finish.It is characterized in that: realize instruction decode mutually at Q1, the programmable counter backup, binary cycle instruction pre-service, interrupt vector is handled, and external interrupt and port change the interruption pretreatment operation; Q2 realizes receiving addressing operation number and the data content after the decoding mutually, and finishes the reading of function register or data register, and finishes the pretreatment operation that the scan operation of interrupting the request flag position and external interrupt are activated park mode simultaneously; Q3 realizes receiving the arithmetic type operational code of decoding back output, the data content of reception data fetch device output mutually, and the pretreatment operation of finishing the arithmetic logical operation of arithmetic logical operation device (ALU), finishing port variation terminal processes and park mode is activated simultaneously, read next bar instruction simultaneously; Q4 realizes mutually that the operand addressing is partly done after operation result with ALU is according to instruction decode and writes back operations, comprise finish that the ALU data write back, internal interrupt and storehouse handle, finish programmable counter simultaneously and handle, programmable counter is handled and is comprised that programmable counter adds 1, programmable counter is popped, the programmable counter redirect.
Above-mentioned clock generator is used to above-mentioned four clock signal is provided mutually, produces four sections required synchronizing clock signals of pipeline organization of described secondary simultaneously.It is characterized in that and to select different mode of operations according to practical application, comprise low frequency (low-power consumption) pattern, general mode, high frequency mode, non-essential resistance/capacitive.
Above-mentioned reseting logic comprises that WatchDog Timer overflows reseting logic, under-voltage reset (BOR) logic under external reset logic under electrification reset (POR) logic, the normal operating conditions, the external reset logic under the dormant state, the normal operating conditions.
Above-mentioned reservoir comprises program storage and data storage, it is characterized in that data register comprises specified register and general-purpose register, utilize the map addresses circuit the physical address map that is distributed in the specified register of different districts and data space and general-purpose register to continuous physical address.
As improving jumbo 2K * 16 otp memory of this chip program reservoir for adopting, so that chip can adapt to the needs of the increasing trend of current application program, thus the usable range of raising chip; Data-carrier store is divided into two parts, specified register and general-purpose register, and totally 224 * 8bit, wherein specified register is 96 * 8bit, general-purpose register 128 * 8bit, the conventional data memory adopts single port, and asynchronous low-power consumption SRAM is realized.
Above-mentioned interrupt operation pattern is that interrupt module is accepted to judge whether this request is satisfied the interruption permission simultaneously and interrupted effective the permission after the interrupt request, if, converting interrupt request to interrupt response, system enters interruption, otherwise, do not produce interrupt response.
Peripheral hardware comprises input/output port (I/O), No. three timers, one tunnel seizure, comparison and width modulation (CCP) module, Universal Synchronous Asynchronous Receiver Transmitter USART (SCI), 86 road mould/number (A/D) converters.
Input/output port comprises port A (PORTA), port B (PORTB), auspicious mouthful of C (PORTC).It is characterized in that port A is 6 latchs, all PORTA ports have TTL SMT enter drive, and PORTA4 has the CMOS output driver, and other PORTA mouth has the TTL output driver; Port B is eight bidirectional ports, all PORTB ports have TTL SMT input and full TTL output driver and all have and innerly draw on weak, its feature of PORTB mouth is that also PORTB0 can be used as the external interrupt mouth that can select to interrupt the edge, and high six of PORTB mouth can be used as fracture in the variation, and outside change in voltage is made interrupt response; Port C is one 8 a bidirectional port, and all PORTC ports have TTL SMT enter drive and CMOS output driver.
Above-mentioned timer comprises TIMER0, TIMER1, TIMER2, it is characterized in that TIMER0 is 8 bit timings/counter, CPU can carry out read-write operation to it, can select internal clocking and external clock reference for use, when selecting external clock, the clock edge that carries out able to programme is selected, and overflows to produce to overflow interruption, and TIMER0 stops counting under the sleep pattern; TIMER1 is 16 bit timings/counter, CPU can carry out read-write operation to it, and 3 pre-dividers able to programme can be selected internal clocking and external clock reference for use, when selecting external clock, external clock negative edge counting, and can be made as synchronous mode count mode or asynchronous mode, can do the time base of seizure, comparison module, counting overflows to produce and overflows interruption, if be set to the external asynchronous count mode, continue counting under the sleep pattern, overflow interruption and can wake CPU up; TIMER2 is 8 bit timing devices, and CPU can carry out read-write operation to it, 4 pre-dividers able to programme, 4 back able to programme frequency dividers, has only internal clock source, clock source frequency Fosc/4 can do the time base counter of pulse width modulation module, and counting overflows to produce and overflow interruption.
Above-mentioned seizure, comparison, the common multiplexing pins of pulse width modulation module, can select different mode by setting related register, it is characterized in that capture function can catch following four kinds of situations on pin: when per 4 rising edges take place when each rising edge takes place when each negative edge takes place in the signal, in the signal, in the signal, in the signal during per 16 rising edges generation; Comparing function can trigger following incident when the incident of relatively coincideing takes place: to export this pin state be high level, export this pin state is low level, export that this pin state remains unchanged, special event triggers; The width modulation function can produce on pin that one-period is adjustable, the width modulation of 10 bit resolutions of EDM Generator of Adjustable Duty Ratio output.
Above-mentioned Universal Synchronous Asynchronous Receiver Transmitter USART is characterized in that having following several mode of operation: full duplex asynchronous pattern, the synchronous master mode of half-duplex, the synchronous follower mode of half-duplex.
Above-mentioned analog to digital converter is characterized in that clock can have following selection: Fosc, Fosc/2, Fosc/8, Fosc/16, an analog signal conversion can be become corresponding 8 position digital signals, and this chip has 6 road analog input ends.
Special feature comprises the time-delay reset (POR) that powers in cell configuration position, the sheet, under-voltage reset (BOR) logic, WatchDog Timer, park mode.
Whether are the mode of operation of above-mentioned cell configuration position decision device and the utilization of partial function, as the time-delay that powers on, under-voltage reset, WatchDog Timer.
Powering in above-mentioned can produce a reset signal when time-delay reset refers to chip power, if the time-delay that powers on enables, and the time-delay that then begins to power on, and finish back activation starting of oscillation timer chip in time-delay and start working.
Above-mentioned under-voltage reset logic is characterized in that and can select power-off reset voltage, can carry out following selection to the filtering circuit clock: 32KHzRC clock, Fosc/4, have 8 pre-dividers, and can produce power-fail interrupt.
Above-mentioned WatchDog Timer (WDT) is characterized in that having 8 pre-dividers, adopts the 32KRC oscillator as counting clock, can produce to overflow to reset, and can wake CPU up under park mode.
Above-mentioned park mode is characterized in that entering the blocking of oscillator of park mode device, the I/O port keeps original level, can wake CPU up by following incident: device resets, WatchDog Timer wakes (if WDT is enabled) up, external interrupt comprises level variation, A/D, Timer1, seizure on INT pin, the high-order pin of PORTB port.
With reference to figure 1, Fig. 1 is the chip core structured flowchart, and at first clock generator provides system clock for chip, takes out instruction according to the value of 13 programmable counters from program storage, and delivers in the order register and store, and deciphers accordingly then.Code translator is controlled whole microcontroller duty, and the microcode of code translator output is divided into three major types with instruction: the instruction of byte manipulation class, bit manipulation instruction, number operation immediately and the instruction of control operation class.Make corresponding processing according to different instructions afterwards, if the byte class is instructed the value in the corresponding register in the first reading of data random access memory, again with work register in value import ALU together and carry out related operation, according to instruction the result is put into afterwards and specifies register (data random access memory or work register); If the content of corresponding register in the bit manipulation instruction elder generation reading of data random register is handled the position that requires according to instruction then, at last the result is write back the appointment register; In instruction, required operand is directly given a constant value if count the class instruction immediately, give ALU together with the value in the work register and carry out related operation, the constant value that this directly inserts operand, be exactly so-called " immediately count " (Literal).Since be that constant value and work register come computing, therefore the result of computing is put among the work register, the problem that does not have the select target register, has only an operand so count operational order immediately, be exactly this constant value, this constant value also must be in 8 scopes that can represent certainly; If control class instruction, because the flow process of program is to carry out one by one according to the order code in the program storage under general situation, steering order then is to be used in the program jump action that differs from general flow, these jump actions have mainly comprised unconditional jump, calling of subroutine, returning of subroutine and returning of interruption subroutine, this class instruction is carried out and is needed two cycles, first cycle is carried out decoding and deal with data, second period is carried out a dummy instruction, another kind of steering order then is to specific function in the single-chip microcomputer but the project that can't control from register, directly start its function with instruction, the startup of picture park mode and the removing of house dog register, this class instruction are directly by the control code of decoding acquisition to the specific function operation.After finishing an instruction cycle, programmable counter adds one automatically, takes out next bar instruction, and so constantly circulation forms pipelining.When taking place to interrupt, handle by interrupt handler, at first, select the value of interrupt vector as programmable counter, the programmable counter processor is imported stack processor with current program counter and is done the pop down processing simultaneously; Entering interrupt routine afterwards handles, when taking place to interrupt returning, stack processor is done the processing of popping, and exports the data in the stack to the programmable counter processor, and the programmable counter processor is the data of the popping value as programmable counter, takes out corresponding code and continues master routine and handle.The programmable counter processor is except above-mentioned functions, also comprise when microcontroller is carried out jump instruction, code translator is done skip operation with the jump address assignment to programmable counter, and be the anti-interference programmable counter backup operation that designs, the variation of each programmable counter all backups last program counter value, can do some corrective operations when being disturbed in order to programmable counter.
Because it is that the utility model is comparatively outstanding that chip operation pattern and port are handled,, handle so arrange Q3 to finish idle pulley so whether microcontroller real-time detection microcontroller in water operation needs to enter the idle pulley of low-power consumption; And being the part ports of detection chip, port pre-service and port aftertreatment whether change, finish pre-service and Q3 finishes whole processing by Q1, judge to guarantee that microcontroller is made accurately the variation of external signal, avoid chip to be interfered after, the phenomenon that can't correctly judge takes place.
See also Fig. 2, Fig. 2 is the structured flowchart that the utility model kernel is connected with peripheral hardware, and kernel is for each peripheral hardware provides clock signal, has when resetting kernel according to reset types each peripheral hardware to be carried out respective settings.Special function register provides all kinds of registers for each peripheral hardware, the operation by the setting of related register being controlled each peripheral hardware, selects the pattern of each peripheral hardware and preserves the required data of each peripheral hardware.
Claims (4)
1, a kind of microcontroller architecture of built-in general-purpose synchronous asynchronous transceiver comprises the kernel, peripheral hardware and the special feature that link to each other with bus respectively separately, it is characterized in that:
Described kernel comprises: clock generator, reseting logic circuit, storer, ALU are connected with CPU (central processing unit) respectively, and above-mentioned device is connected with bus respectively again;
Described peripheral hardware comprises: the input/output port that links to each other with bus, 86 road A/D converters, and one tunnel seizure, No. three timers, comparison are connected with bus by the common pin data line respectively with pulse width modulation module, Universal Synchronous Asynchronous Receiver Transmitter;
Described special feature comprises: the time-delay reset that powers in cell configuration position, the sheet, under-voltage reset logic, WatchDog Timer, park mode, above device is connected with bus respectively.
2, microcontroller architecture as claimed in claim 1, it is characterized in that described storer comprises the data register of 2K * 16 a disposable programmable program storage and 224 * 8bit, data-carrier store is divided into two parts, specified register and general-purpose register, wherein specified register is 96 * 8bit, general-purpose register 128 * 8bit, the conventional data memory adopts single port, and asynchronous low-power consumption SRAM is realized.
3, a kind of microcontroller architecture of built-in general-purpose synchronous asynchronous transceiver comprises the kernel, peripheral hardware and the special feature that link to each other with bus respectively separately, it is characterized in that:
Described kernel comprises that data random access memory, ALU, programmable counter link to each other with bus respectively, storehouse, interrupt handler link to each other with programmable counter respectively, the output terminal of programmable counter links to each other with program storage, order register, command decoder successively, the output terminal of command decoder connects data random access memory, ALU, reseting logic circuit respectively, the output terminal of data random access memory is connected with ALU, work register links to each other with ALU, and oscillator links to each other with reseting logic circuit;
Described peripheral hardware comprises: the input/output port that links to each other with bus, 86 road A/D converters, and one tunnel seizure, No. three timers, comparison are connected with bus by the common pin data line respectively with pulse width modulation module, Universal Synchronous Asynchronous Receiver Transmitter;
Described special feature comprises: the time-delay reset that powers in cell configuration position, the sheet, under-voltage reset logic, WatchDog Timer, park mode, above device is connected with bus respectively.
4, microcontroller architecture as claimed in claim 3, it is characterized in that described storer comprises the data register of 2K * 16 a disposable programmable program storage and 224 * 8bit, data-carrier store is divided into two parts, specified register and general-purpose register, wherein specified register is 96 * 8bit, general-purpose register 128 * 8bit, the conventional data memory adopts single port, and asynchronous low-power consumption SRAM is realized.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105024674A (en) * | 2015-03-13 | 2015-11-04 | 苏州迈瑞微电子有限公司 | Asynchronous resetting device |
| CN110119133A (en) * | 2016-03-14 | 2019-08-13 | 赛普拉斯半导体公司 | Method for the transceiver of communication and for controlling communication |
| CN111027108A (en) * | 2019-08-13 | 2020-04-17 | 哈尔滨安天科技集团股份有限公司 | Sequential logic safety detection method and device of low-speed synchronous serial bus |
-
2006
- 2006-11-10 CN CN 200620047703 patent/CN200997135Y/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105024674A (en) * | 2015-03-13 | 2015-11-04 | 苏州迈瑞微电子有限公司 | Asynchronous resetting device |
| CN105024674B (en) * | 2015-03-13 | 2018-06-12 | 苏州迈瑞微电子有限公司 | A kind of asynchronous reset |
| CN110119133A (en) * | 2016-03-14 | 2019-08-13 | 赛普拉斯半导体公司 | Method for the transceiver of communication and for controlling communication |
| CN110119133B (en) * | 2016-03-14 | 2022-04-01 | 赛普拉斯半导体公司 | Transceiver for communication and method for controlling communication |
| CN111027108A (en) * | 2019-08-13 | 2020-04-17 | 哈尔滨安天科技集团股份有限公司 | Sequential logic safety detection method and device of low-speed synchronous serial bus |
| CN111027108B (en) * | 2019-08-13 | 2024-02-13 | 安天科技集团股份有限公司 | Sequential logic safety detection method and device for low-speed synchronous serial bus |
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