JPH0734559B2 - Digital transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is used in the field of digital transmission.

The present invention relates to a digital transmission system, and more particularly to an optical digital transmission system provided with a repeater which uses an nBmB code for a transmission line signal and sends a predetermined fixed pattern signal (hereinafter referred to as an AIS signal) when an input signal is cut off. .

〔Overview〕

The present invention, in a digital transmission method using an nBmB code as a transmission path signal, transmits a repetition of a block composed of arbitrary m bits as an AIS signal when an input signal to a repeater is disconnected. This makes it possible to satisfy the nBmB coding rule with a simple configuration.

[Prior Art] Conventionally, in the optical digital transmission system, this AIS signal has been sent out as "1" as a transmission signal to the transmission line when the input of the low order group signal is cut off.

FIG. 2 is a block diagram showing a main part of an example of a conventional optical digital transmission system, and shows a transmitter of one repeater and a receiver of another repeater connected to the repeater via a transmission line. Show.

The input data signal 1 and the input clock signal 2 are input to the transmission unit 10, and are converted into five parallel signals 3 by the serial-parallel conversion circuit 11. The parallel signal 3 is converted into six parallel signals 4 by the 5B6B conversion circuit 12, further converted into serial signals 5 by the parallel-serial conversion circuit 13, and sent out to the transmission line 30. on the other hand,
The speed of the input clock signal 2 is converted 1.2 times by the speed conversion circuit 14.

Serial signal 5 sent to the receiving unit 20 through the transmission line 30
Are converted into 6 parallel signals 6 by the serial-parallel conversion circuit 21, further converted into 5 parallel signals 7 by the 6B5B conversion circuit 22, and converted into serial signals 8 by the parallel-serial conversion circuit 23. The speed conversion circuit 24 converts the speed by 0.83 times.

When the input disconnection detection circuit 15 detects the input disconnection of the input data signal 1 and the input clock signal 2, the input disconnection detection circuit 15 outputs the control signal 9 to the 5B6B conversion circuit 12. The 5B6B conversion circuit 12 sends out as an AIS signal by the control signal 9 so that all "1", that is, "110101" and "001010" are alternated.

[Problems to be solved by the invention]

However, when the input clock signal 2 is cut off, the disparity of the input data signal 1 cannot be detected.
B code rule cannot be satisfied. Therefore, in order to satisfy the 5B6B coding rule, it is necessary to externally provide the oscillator 16 to perform the mismatch detection, and there is a drawback that the circuit scale and power consumption increase.

An object of the present invention is to provide a digital transmission system that can satisfy the 5B6B coding rule with a simple configuration by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention relates to a serial-parallel conversion circuit for converting and outputting an input data signal into a plurality of n parallel signals, an nBmB conversion circuit for converting and outputting the n parallel signals into a plurality of m parallel signals, and the input data signal. An input disconnection detection circuit that detects disconnection and outputs a control signal to the nBmB circuit, and the nBmB conversion circuit includes a fixed pattern signal transmission unit that transmits a predetermined fixed pattern signal when the control signal is input. In the digital transmission system including a repeater including the fixed pattern signal sending means, the fixed pattern signal sending means is means for sending a repetition of a block of the same code composed of arbitrary m bits as the fixed pattern signal. To do.

[Action]

The fixed pattern signal transmission means repeats a block composed of arbitrary M bits as an AIS signal, for example,
In the case of the 5B6B coding rule, a repeated signal of "101001" is transmitted as an AIS signal.

Therefore, the discrepancy becomes 0, the discrepancy detection on the nB side (for example, 5B rule) is not necessary, the external oscillator is not required unlike the conventional case, the circuit scale is reduced, and even if the input clock signal is cut off, nBmB It becomes possible to satisfy the coding rule (for example, 5B6B).

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention, showing a transmitter of one repeater and a receiver of another repeater connected to the repeater via a transmission line.

In this embodiment, a serial-parallel conversion circuit 11 for converting and outputting an input data signal 1 into five parallel signals 3 and five parallel signals 3 are used.
The 5B6B conversion circuit 12 includes a 5B6B conversion circuit 12 that converts and outputs the individual parallel signals 4, and an input disconnection detection circuit 15 that detects the input data signal disconnection and outputs the control signal 9 to the 5B6B conversion circuit 12.
Is a digital transmission system equipped with a repeater including a fixed pattern signal transmitting means (not shown) for transmitting a predetermined AIS signal when a control signal 9 is input. The block of the same code composed of
It has means (not shown) for transmitting as an AIS signal.

In FIG. 1, 13 is a parallel-serial converter that converts 6 parallel signals into serial signals 5 and sends them to the transmission line 30, and 14 is a speed conversion circuit that converts the speed of the input clock signal 2 to 1.2 times. The serial / parallel conversion circuit 11, the 5B6B conversion circuit 12, the parallel / serial conversion circuit 13, the speed conversion circuit 14, and the input disconnection detection circuit 15 are included in the transmission unit 10 of one repeater.

Reference numeral 20 denotes a receiver of another repeater, which includes a parallel-serial conversion circuit 21 that converts the serial signal 5 input from the transmission line 30 into six parallel signals 6, and the parallel signal 6 into five parallel signals 7. 6B5B conversion circuit 22 for converting to parallel signal 7, parallel-serial conversion circuit 23 for converting and outputting parallel signal 7 to serial signal 8, and speed conversion circuit 24 for converting line speed to 0.83 times.

The feature of the present invention is that in FIG. 1, the oscillator 16 in the conventional example shown in FIG.
This is because a fixed pattern signal transmitting means (not shown) for transmitting a repetitive signal of a block composed of arbitrary m bits as the S signal is provided.

Next, the operation of this embodiment will be described.

The input data signal 1 and the input clock signal 2 are input to the transmission unit 10, and are converted into five parallel signals 3 by the serial-parallel conversion circuit 11. The parallel signal 3 is converted into 6 parallel signals 4 by the 5B6B conversion circuit 12, converted into the serial signal 5 by the parallel-serial conversion circuit 13, and sent to the transmission line 30. Also, the input signal disconnection detection circuit 15 monitors the input data signal 1 and the input clock signal 2, and when the input is disconnected, the control signal 9 is sent to the 5B6B conversion circuit 12 and the AIS signal is sent to the transmission line 30. In the receiving unit 20, the serial signal 5 sent thereto is converted into 6 parallel signals 6 by the serial-parallel conversion circuit 21, and converted into 5 parallel signals 6 by the 6B5B conversion circuit 22, and the parallel-serial conversion circuit 23
Results in a serial signal 8.

Then, as the AIS signal, for example, a repeating signal of the block of "101001" is output.

Therefore, the mismatch becomes 0, the mismatch detection on the 5B side becomes unnecessary, and the 5B6B coding rule is satisfied.

As the AIS signal, an arbitrary m-bit fixed pattern other than the above example is used, and any pattern may be used as long as it is predetermined.

Although the 5B6B coding rule is used as the nBmB coding rule in the above description, the present invention is generally applied to the nBmB coding rule.

〔The invention's effect〕

As described above, the present invention has the effects that the mismatch detection is unnecessary, the circuit scale is small, and the nBmB coding rule can be satisfied even if the input clock signal is interrupted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention. FIG. 2 is a block diagram showing a main part of a conventional example. 1 ... Input data signal, 2 ... Input clock signal, 3, 4,
6, 7 ... Parallel signal, 5, 8 ... Serial signal, 9 ... Control signal,
10 ... Transmission unit, 11, 21 ... Serial-parallel conversion circuit, 12 ... 5B6B conversion circuit, 13, 23 ... Parallel-serial conversion circuit, 14, 24 ... Speed conversion circuit,
15 ... Input disconnection detection circuit, 16 ... Oscillator, 20 ... Receiver, 22 ... 6B
5B conversion circuit, 30 ... Transmission line.

Claims (1)

[Claims] 1. A serial-parallel conversion circuit (11) for converting and outputting an input data signal into a plurality of n parallel signals, and an nBmB conversion circuit (12) for converting and outputting the n parallel signals into a plurality of m parallel signals. ) And an input disconnection detection circuit (15) for detecting the input data signal disconnection and outputting a control signal to the nBmB conversion circuit.
Wherein the nBmB conversion circuit is a digital transmission system including a repeater including a fixed pattern signal sending means for sending an alarm signal of a predetermined fixed pattern when the control signal is input, wherein the fixed pattern signal sending means Is a means for sending out a repetition of a block of an arbitrary same code composed of m bits as the alarm signal of the fixed pattern.