SU1374215A1

SU1374215A1 - Adder-accumulator

Info

Publication number: SU1374215A1
Application number: SU864067750A
Authority: SU
Inventors: Александр Викторович Паленков
Original assignee: А.В.Паленков
Priority date: 1986-04-04
Filing date: 1986-04-04
Publication date: 1988-02-15

Abstract

Изобретение относитс к области автоматики и радиотехники. Цель изобретени - повышение быстродействи . Накапливающий сумматор содержит три сумматора 1,2,3, мультиплексор 4, регистр 5, блок элементов НЕ 6, триггер 7, первый и второй информационные входы 8,9, тактовый вход 10 сумматора , выход 11 результата, выход 12 переполнени .The invention relates to the field of automation and radio engineering. The purpose of the invention is to increase speed. The accumulating adder contains three adders 1,2,3, multiplexer 4, register 5, block of elements NOT 6, trigger 7, first and second information inputs 8.9, clock input 10 of the adder, output 11 of the result, output 12 of overflow.

Description

Изобретение относитс к автоматике и радиотехники и может быть использовано в синтезаторах частот.The invention relates to automation and radio engineering and can be used in frequency synthesizers.

Цель изобретени - повышение быстродействи .The purpose of the invention is to increase speed.

На чертеже представлена функциональна схема накапливающего сумматора .The drawing shows a functional diagram of the accumulating adder.

Накапливающий сумматор содержит три комбинационных сумматора 1, 2 и 3, мультиплексор 4, регистр 5, блок 6 элементов НЕ, триггер 7, первый и второй информационные входы 8 и 9 сумматора, тактовый вход 10 сумматора , выход 11 результата сумматора , выход 12 переполнени сумматора.Accumulating adder contains three combinational adders 1, 2 and 3, multiplexer 4, register 5, block 6 elements NOT, trigger 7, first and second information inputs 8 and 9 of the adder, clock input 10 of the adder, output 11 of the adder, output 12 overflow of the adder .

Накапливающий сумматор работает следующим образом.Accumulating adder works as follows.

рой вход сумматора 3 поступает накапливаема сумма a(t), значение которой возрастает на число а при поступлении тактового импульса. Очевидно, что при возрастании a(t) наступит момент, когда сумматор 3 переполнитс . Момент переполнени будет зависеть отThe accumulator input of the adder 3 enters the accumulative sum a (t), the value of which increases by the number a when the clock pulse arrives. Obviously, as a (t) increases, a moment will come when adder 3 overflows. The moment of overflow will depend on

числа а наступитthe numbers will come

; чем больше ао, переполнение.; the more ao, overflow.

тем раньшеthe earlier

Claims

Invention Formula

Accumulating adder containing two combinational adders, register, multiplexer, trigger, block of elements is NOT, the first information input of accumulating adder is connected to the input of the first operand

The input of the adder 1 receives the number of the first 20 combinational adder.

lo from the first input of the device, which is also fed to one of the inputs of the adder

2. The other input of adder 2 receives the number q-b-1 (inverse code of the number b) from the output of the inverter unit, the input of which is the second input of the device. The transfer input of the adder 2 is supplied 1. At the output of the adder 2, the number a6 q-b + a is formed, which goes to one of the inputs of the adder 3, to the other input of which the number a (t) is fed from the output of the register 5. At the output register 5 of the number a (t), greater (b-a), the adder 3 overflows and the overflow signal enters the information input of the trigger 7 and the control input of the multiplexer 4 connecting the information inputs of the register 5 to the output of the adder 3, where the remainder q- b + a + a (t) -qa (t) -b + a. The next clock pulse writes the remainder to the register, and an overflow pulse appears at the output of the trigger.

The overflow signal of the adder 3 is generated under the condition that the sum of the numbers a (t) and a is greater than the capacity of the adder, i.e. a (t) + ao q q, tde n is the number of bits of the adder. The number a, which is formed at the output of the adder 2, is fed to one of the inputs of the adder 3 and does not depend on the arrival of the clock pulses at the input of the accumulating adder, but depends only on the numbers a and b. On wto

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the second information input of which is connected to the output of a block of elements NOT, the input of which is connected to the second information input of the accumulating

5 adder, the input of the logical unit of the accumulating adder is connected to the transfer input of the first combination adder, the clock input of the accumulating adder is connected to the clock inputs of the register and trigger, the trigger output is connected to the overflow output of the accumulating adder, the information input of the trigger is connected to the overflow output of the second combiner an operand of which is connected to the output of the register and the output of the result of the accumulating adder, characterized in that

0 speed, the third combiner adder is entered into it, the inputs of the first and second operands of which are connected respectively to the first information input of the accumulating adder and the output of the register, whose information input is connected to the output of the multiplexer, the control input of which is connected to the overflow output of the second combiner adder, the output of the sum which is connected to the first information input of the multiplexer, the second information input of which is connected to the output of the sum of the third adder, movement of the second operand of the second adder connected to the output of the first adder sums.

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