RU2029355C1 - Device for determining code combinations - Google Patents

Abstract

FIELD: computer technology. SUBSTANCE: device has triggers 1-4, modulo 2 adders 7-9, OR-NOT gates 13, 14, NOT gates 15, 16. EFFECT: reduced error of result of selecting code combinations. 1 dwg

Description

 The invention relates to techniques for processing digital data and can find application in the transmission of digital information to extract from it the given code combinations.

 A device for determining code combinations containing registers, triggers, OR elements and AND elements NOT included between the input and output buses [1].

 A disadvantage of the known device for determining code combinations is the significant complexity of its design.

 The closest in technical essence to the proposed device for determining code combinations is a device for determining code combinations containing triggers connected by zero setting inputs and synchronization inputs, respectively, to the input reset bus and input bus of the clock signal, modulo two adders [2].

 The disadvantage of this device is the significant error in the determination of code combinations. The known device also does not allow for a sufficiently high speed with a sufficiently low energy consumption and has significant design complexity.

 The technical result that can be obtained by carrying out the invention is expressed in reducing the error of the result of the allocation of code combinations.

 A comparative analysis of the set of essential features characterizing the claimed technical solution showed that the claimed technical solution is new, since it is not known from the prior art.

 Comparison of the claimed technical solution not only with the prototype, but also with other technical solutions in the same technical field did not reveal the features that distinguish it from the prototype, which allows us to conclude that the claimed technical solution has an inventive step, since it explicitly does not follow from the prior art.

 The drawing shows one of the possible variants of the proposed device for determining code combinations.

 The device contains the first and fourth triggers 1-4, reset input 5, clock input 6, adders 7, 8 and 9 modulo two, information input 10, input 11 for setting the operating mode, output 12 of the device, items OR NOT 13 and 14 , items NOT 15 and 16.

 Triggers ("Instructions for the development of microcircuits, Minsk, NPO Integral, 1988, p. 13), are made with direct and inverse synchronization inputs, which reduces energy consumption by using one element NOT connected between the clock input bus and the inverse synchronization inputs All triggers included in the device Adders 7, 8 and 9 modulo two can be made as adders modulo two / described in the book Instructions for the development of microcircuits, Minsk, NPO Integral, 1988, p.12.

 The proposed device for determining code combinations works as follows.

The input binary signal input to input 10 is gated at the moments of a positive voltage drop at input 6 of the clock signal and fits into the first trigger 1. Under the action of clock pulses at input 6 of the clock signal, the information received at input 10 passes through the first, second, third and fourth triggers 1, 2, 3, and 4 operating in a shift register mode. At the direct outputs of the first, second, third, and fourth triggers 1, 2, 3, and 4, after the nth pulse arrives, the values of S _n , S _n-1 , S _n-2 , S _n-3, respectively, act on the input bus 6 of the clock signal , where S _n is the value of the signal at input 10 at the time of the n-th positive voltage drop at the input 6 of the clock signal, and S _n-1 , S _n-2 , S _n-3 are the values of the same signal at previous times. If the values of S _n and S _n-1 coincide, the output of the first adder 7 modulo two is the logical level “0”. Similarly, the outputs of adders 8 and 9 modulo two have a logic level of "0" with the coincidence of the signals S _n-1 and S _n-2 and the signals S _n-2 and S _n-3, respectively.

 The signals from the outputs of the adders 7 and 8 are fed to the inputs of the element OR NOT 14 directly. The signal from the output of the adder 9 modulo two through the element HE 16 and the element OR NOT 13 is fed to the third input of the second element OR NOT 14 without inversion in the case of a logic level of "0" on the input bus 11 of the operating mode. If there is a logical level of "1" at the input 11 of the job mode, the third level of the second element OR-NOT 14 is supplied with a logic level of "0" regardless of the value of the output of the adder 9 modulo two. If all three inputs of the OR-NOT 14 element have a logical "0" level, output 12 sets the logical "1" level. Otherwise, the output level 12 is a logical level "0".

 Thus, output 12 sets the logic level to “1” upon receipt of a single value of logical “0” or logical “1” at input 10 at three or four consecutive moments of a positive signal drop at input 6 of the clock signal at the level of logical “1” and logical "0" at input 11, respectively. In other words, a combination of 000 or 111 is allocated at a logical level of “1” at input 11 of the operating mode setting and a combination of 0000 or 1111 at a logical level of “0” at input 11 of the operating mode setting.

Claims (1)

 DEVICE FOR DETERMINING CODE COMBINATIONS, containing modulo two adders and triggers, the zero-setting inputs of which are connected to the device reset input, and the direct synchronization inputs are connected to the device clock signal, characterized in that two OR-NOT elements and two elements are inserted into it NOT, and the input of the device clock signal through the first element is NOT connected to the inverse synchronization inputs of all triggers, the information input of the device is connected to the information input of the first trigger, the direct output of which is connected is connected with the first input of the first adder modulo two and the information input of the second trigger, the direct output of which is connected to the second input of the first adder modulo two, with the first input of the second adder modulo two and with the information input of the third trigger, the direct output of which is connected to the second input the second adder modulo two, to the first input of the third adder modulo two and to the information input of the fourth trigger, the output of which is connected to the second input of the third adder modulo two, the output of which is through the second the first element is NOT connected to the first input of the first OR-NOT element, the second input of which is connected to the input of the job mode, device, and the output to the first input of the second OR-NOT element, the second and third inputs of which are connected to the outputs of the first and second adders modulo two, and the output is the output of the device.