RU2029357C1 - Digital integrator - Google Patents

Abstract

FIELD: digital data processing technique. SUBSTANCE: digital integrator has (2n+1) adders, three NOR gates, and NOT gate. EFFECT: improved accuracy of integration results. 2 dwg

Description

 The invention relates to techniques for processing digital data and may find application for summation-subtraction with accumulation.

 Known digital integrator containing adders, registers, counters, an integral calculation unit and an element And included between the input and output buses [1].

 A disadvantage of the known digital integrator is the significant complexity of its design.

 A digital integrator is also known, containing n + 1 adders (n is the width of the integer part of the number) and the element is NOT [2].

 The disadvantage of such a digital integrator is the significant error of the integration result.

 The technical result that can be obtained by carrying out the invention is expressed in increasing the accuracy of the integration result.

 To obtain this technical result, a digital integrator containing n + 1 adders (n is the bit depth of the integer part of the number) and the element NOT, introduces three elements OR-NOT and n adders, the integrator common bus connected to the input of the first adder, the transfer output i- the adder (i = 1, ..., n-1) is connected to the transfer input of the (i + 1) adder, the carry output of the (n + 1) adder is connected to the carry input (n + i + 1) - adder, the transfer output of the nth adder is connected to the first input of the first OR-NOT element and the transfer input of the (2n + 1) adder, the transfer output to It is connected to the first input of the second OR-NOT element, the output of which is connected to the first input of the third OR-NOT element, the second input of which is connected to the output of the first OR-NOT element, and the output to the transfer input of the (n + 1) -th adder, the first information output of the (n + j) adder is connected to the information input of the jth adder (j = 1, ..., n), the information inputs of adders from (n + 2) to 2nth are connected to the information input integrator, the output of the j-th discharge of which is connected to the second information output of the (n + j) -th adder, the input of the choice of the counting mode integr the torus is connected to the second input of the second OR-NOT element and through the NOT element to the second input of the first OR-NOT element, the information inputs of the (n + 1) -th and (2n + 1) -th adders are connected to the power input of the integrator, the reset output of which connected to the reset inputs of all 2n + 1 adders, the direct and inverse synchronization inputs of which are connected respectively to the first and second clock inputs of the integrator.

 In FIG. 1 shows one of the possible options for a digital integrator; figure 2 is one of the possible options for its adder.

 The digital integrator (Fig. 2) contains the first to eighth adders 1-8 (the number of which n = 8 is the bit capacity of the integer part of the number), as well as the ninth to sixteenth adders 9-16 (the number of which is also n) and the seventeenth adder 17 ( in the general case, the ordinal number of this adder is 2n + 1). In addition, the digital integrator contains the first, second and third elements OR 18, 19 and 20 and the element NOT 21. The integrator common bus 22 is connected to the transfer input of the first adder 1, and the transfer outputs of the first to seventh adders 1-7 are connected to the inputs transfer, respectively, of the second to eighth adders 2-8. The transfer outputs of the ninth to fifteenth adders 9-15 are connected to the transfer inputs, respectively, of the tenth to sixteenth adders 10-16. The transfer output of the eighth adder 8 is connected to the first input of the first OR-NOT 18 element and to the transfer input of the seventeenth adder 17, the transfer output of which is connected to the first input of the second OR-NOT 19. The output of the second OR-NOT 19. The output of the second OR- NOT 19 is connected to the first input of the third element OR-NOT 20, the second input of which is connected to the output of the first element OR-NOT 18, and the output to the transfer input of the ninth adder 9. The first information inputs of the ninth to sixteenth adders 9-16 are connected to information inputs with Responsibly the first to eighth adders 1-8. The information inputs of the tenth to sixteenth adders 10-16 are connected to the information input 23 of the integrator. The outputs 24 of the first to eighth bits of the integrator are connected to the second information outputs, respectively, of the ninth to sixteenth adders 9-16. An integrator account mode selection input 25 is connected to the second input of the second OR-NOT 19 element and through the element 21 to the second input of the first OR-NOT 18. The information inputs of the ninth and seventeenth adders 9 and 17 are connected to the integrator power input 26. The reset input 27 of the integrator is connected to the reset inputs of the first to seventeenth adders 1-17, in which the direct synchronization inputs are connected to the first clock input 28 of the integrator and the inverse synchronization inputs are connected to the second clock input 29 of the integrator.

 The adder of the digital integrator (figure 2) contains the elements 2I-OR-NOT 30 and 31, the trigger 32, the element AND 33, and the adder 34 modulo two. The first input of the AND-OR-NOT 30 element coincides with the adder transfer input connected to the first input of the AND-NOT element 33. The output of the AND-NOT element 33 is connected to the second and third inputs of the element 2AND-NOT-30 and to the first input of the element 2I -OR-NOT 31. The output of the element AND-OR-NOT 31 matches the transfer output of the adder, and the output of the element 2-OR-NOT 30 is connected to the information input of the trigger 32, the inverse output of which coincides with the first information output of the adder. The direct and inverse synchronization inputs and the zero-setting input of the trigger 32 coincide with the direct and inverse synchronization inputs and the reset input of the adder, respectively. The output of the adder 34 modulo two is connected to the second input of the AND-NOT 33 element, to the fourth input of the 2AND-NOT-30 element and to the second input of the 2AND-NOT-31 element, the third input of which coincides with the information input of the adder connected to the first the input of the adder 34 modulo two. The second input of the adder 34 modulo two is connected to the direct output of the trigger 32, coinciding with the second information output of the adder and connected to the fourth input of the element 2 AND-OR-NOT 31.

 The digital integrator works as follows.

 When a logic level “1” is applied to the integrator reset input 27, the first to seventeenth adders 1-17 are set to a state in which there is a logic level “0” at the transfer outputs, a logic level “1” at the first information inputs, and logic information “1” at the second outputs - logical level "0". To simplify the description, the operation of the digital integrator is considered in the presence of a logic level of "0" at the input 27 of the reset integrator. Moreover, the clock signal at the second clock input 29 of the integrator is inverse relative to the clock signal at the first clock input 28 of the integrator.

 When a logic level “0” is applied to the integrator information input 23 at the transfer output of the tenth adder 10, the logic level is “1”, and under the influence of a positive signal level difference at the first clock input 28 of the integrator, the logic level “0” is set at the first information output of the tenth adder 10 "(at the second information input, the logical level is set to" 1 "). At the outputs of the transfer of the eleventh to sixteenth adders 11-16 remains the level of the logical "0", and at their first information outputs - the level of the logical "1".

 The output levels at the outputs 24 of the first to eighth bits of the integrator form an eight-bit binary number, the least significant bit of which is determined by the state of the second information output of the ninth adder 9, and the highest bit by the state of the second information output of the sixteenth adder 16. After the logic level “0” acts on the information input 23 integrator during the first clock pulse at the outputs 24 of the first to eighth bits of the integrator sets the binary number.

 The second information outputs of the first to seventeenth adders 1-17 form a binary number, the bit capacity of which is seventeen if there are logical levels of "0" at the input 25 of the integrator account mode selection and sixteen if there is a logical "1" level on it. The binary number can be considered as consisting of an eight-bit part and a nine- or eight-bit fractional part.

 With each new arrival of the logic level “0” at the information input 23 of the integrator at the moments of a positive signal drop at the first clock input 28 of the integrator, its content is increased by two. Upon receipt of the level of logical "1" at the information input 23 of the integrator at the moments of a positive signal drop at the first clock input 28 of the integrator, its content does not increase.

 As a result of the connection of the first information outputs of the ninth to sixteenth adders 9-16 (adders of the senior group) with the information inputs of the first to eighth adders (adders of the younger group), the senior part is shifted from the contents of the digital integrator, shifted by eight or nine bits at a logic signal level "1" or logical "0", respectively, at the input 25 of the integrator account mode selection.

 Thus, the increase in the contents of the digital integrator occurs under the influence of a logical “0” level coming from the information input 23 from the outside, and its decrease is due to internal connections. The content of the digital integrator changes at the moment of positive changes in the signal at the first clock input 28 of the integrator, and the content is reset to zero asynchronously under the action of the logic level “1” at the input 27 of the integrator reset.

Claims (1)

 A DIGITAL INTEGRATOR containing n + 1 adders (n is the bit depth of the integer part of the number) and an element NOT, characterized in that three elements OR-NOT and n adders are inserted into it, a common integrator bus is connected to the transfer input of the first adder, the transfer output is i- the adder (i = 1, ..., n-1) is connected to the transfer input of the (i + 1) adder, the transfer output of the (n + i) adder to the transfer input (n + i + 1) is adder, the transfer output of the nth adder is with the first input of the first OR-NOT element and the transfer input of the (2n + 1) adder, the transfer output of which is connected to the first input of the second of the OR-NOT element, the output of which is connected to the first input of the third OR-NOT element, the second input of which is connected to the output of the first OR-NOT element, and the output - with the transfer input of the (n + 1) adder, the first information output (n + j) -th adder is connected to the information input of the j-th adder (j = 1, ..., n), information inputs of adders from (n + 2) -th to 2n-th are connected to the information input of the integrator, output j- the first discharge of which is connected to the second information output of the (n + j) adder, the input of the integrator account mode selection is connected to the second input of the second of the OR-NOT element and through the NOT element with the second input of the first OR-NOT element, the information inputs of the (n + 1) -th and (2n + 1) -th adders are connected to the integrator power input, the reset input of which is connected to the reset inputs of all 2n + 1 adders, the direct and inverse synchronization inputs of which are connected respectively to the first and second clock inputs of the integrator.

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