RU181022U1 - MULTI-INPUT DIGITAL PULSE FLOW SUMMER - Google Patents

Abstract

The invention relates to the field of computer technology, namely to a multi-input digital pulse stream adder, which includes a digital input stream adder, the output of which is converted to a pulse stream using a first-order digital sigma-delta modulator, which includes a digital negative adder connected to a digital integrator adder, which is connected to a memory element, the resolution input of which is connected to a truth table connected to the two upper bits of the output of the memory element ti and the high bit of the result of a digital negative adder, and the output of the memory element is connected to a digital quantizer, the output of which is the output of a multi-input digital adder of pulse flows, and also connected to a digital negative adder. The utility model provides increased accuracy in the formation of the resulting signal at the output of the adder when adding three or more pulse flows.

Description

The utility model relates to the field of computer technology and can be used in various fields of science and industry to create control devices and digital signal processing.

From the current level of technology, a two-input digital pulse adder is known [Ng C.W. et al. Bit-stream adders and multipliers for tri-level sigma-delta modulators / IEEE Transactions on Circuits and Systems II: Express Briefs, 2007, V. 54, N. 12, pp. 1082-1086]. Such a device contains three three-input single-bit adders and a single-bit memory element.

The disadvantages of this device is the low accuracy when adding three or more pulse flows using a cascade of several adders. This disadvantage is associated with the small amount of memory in the adder, which does not allow storing the transfer if it occurs on two consecutive clock cycles of addition of pulse flows.

The proposed utility model is aimed at solving the technical problem of eliminating this drawback.

The technical result achieved in this case is to increase the accuracy of the formation of the resulting signal at the output of the adder when three or more pulse flows are added.

The technical result is achieved in that the multi-input digital pulse adder includes a digital input adder, the output of which is converted into a pulse stream using a first-order digital sigma-delta modulator, which includes a digital negative adder connected to an integrator digital adder, which is connected with a memory element whose resolution input is connected to a truth table connected to the two most significant bits of the integrator's digital adder and the highest bit of the result of the digital negative adder, and the output of the memory element is connected to a digital quantizer, the output of which is the output of a multi-input digital adder of pulse flows, and also connected to a digital negative adder.

These features of the utility model are significant and the combination of these features is sufficient to obtain the desired technical result.

The utility model is illustrated by drawings.

In FIG. 1 shows a block diagram of the claimed utility model. It contains a digital input adder 1, a digital negative adder 2, a digital integrator adder 3, a memory element with write enable 4, a digital quantizer 5, and a truth table 6.

The device operates as follows. At its input, K pulse streams are encoded so that a pulse with an amplitude of -1 corresponds to a two-bit code 11, a pulse with an amplitude of 1 corresponds to a two-bit code 01, and the absence of a pulse corresponds to a code 00. The codes of the input pulse streams go to the digital adder of the input streams 1, where they add up without loss of accuracy, forming the output N-bit pulse-code modulated signal, where N≥ (log ₂ K + 1). The result of the digital input adder 1 is input to the N-bit digital negative adder 2, where the output of the multi-input digital impulse adder obtained from the previous calculation step and supplemented with N-2 signed bits to the size of N-bits is subtracted from it. The lower N-bits of the output of the digital negative adder 2 are fed to the first input of the digital adder of the integrator 3, to the second input of which the output of the memory element 4 is connected. The output of the digital adder of the integrator 3 is written to the memory element 4 in the presence of a write enable signal. The write enable signal is generated using the truth table 6, the input of which receives the two most significant bits of the output of the memory element 4 and the most significant bit of the output of the digital negative adder 2. The output of the truth table 6 is generated according to table 1. The output of the memory element 4 is fed to a symmetric digital quantizer 5 , which on its basis forms a two-bit code corresponding to the amplitude value of the next pulse of the output stream. The dependence of the output of quantizer 5 on its input is shown in FIG. 2. Elements 1-5 change their outputs synchronously along the edge of the common clock signal.

Performance was tested on the layout, which clearly demonstrated the receipt of the required technical result. The proposed device was implemented in the form of a three-input adder of pulsed flows with N = 4. Also, for comparison, an analogue was simulated based on a cascade of two well-known two-input pulse flow adders [Ng C.W. et al. Bit-stream adders and multipliers for tri-level sigma-delta modulators / IEEE Transactions on Circuits and Systems II: Express Briefs, 2007, V. 54, N. 12, pp. 1082-1086]. The formation of the input pulse flows was carried out using digital sigma-delta modulators of the first order, operating at a frequency of 100 MHz. Demodulation of the input pulse flows and the resulting pulse adder flow was carried out using an averaging filter with a window of 65535 measurements with a period of 10 ns. All layout elements were implemented on the basis of the Xilinx XC7A100T-1CSG324C FPGA chip, which was clocked by a generator with a frequency of 100 MHz.

In FIG. Figure 3 shows the dependence of the error of the output result of the utility model and the cascade of known adders, reduced to the maximum amplitude of the pulses in the pulse flows from the reference value of the result obtained in the course of 100,000 experiments. As can be seen from FIG. 3, the maximum error of adding three pulsed flows in the proposed utility model is 2 orders of magnitude lower than in the cascade of known two-input adders of pulsed flows, which indicates its operability and the achievement of the claimed technical result.

Claims (1)

A multi-input digital pulse stream adder, including a digital input stream adder, the output of which is converted to a pulse stream using a first-order digital sigma-delta modulator, which includes a digital negative adder connected to an integrator digital adder that is connected to the memory element, input whose resolution is connected to the truth table connected to the two most significant bits of the output of the memory element and the most significant bit of the result of the digital negative adder, and the output is The memory element is connected to a digital quantizer, the output of which is the output of a multi-input digital adder of pulse flows, and is also connected to a digital negative adder.

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