SU1267431A1 - Device for executing fast fourier transform - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in systems for processing discrete information, radio and sonar, medical and other equipment using digital filtering and spectral analysis. The purpose of the invention is to increase speed. The goal is achieved by the fact that the device includes two coefficient registers, three input registers, two registers of products, a trigger, a clock generator, a totalizer-subtractor, c (two multipliers with corresponding connections between the nodes of the device, (L 2 silt

Description

The invention relates to computing and can be used in systems for processing discrete information, radio and sonar, medical and other equipment that use digital filtering and spectral analysis. The aim of the invention is to increase speed. FIG. 1 shows a functional diagram of a device for performing a fast Fourier transform; Fig. 2 shows time diagrams explaining the operation of the device. The device (Fig. 1) contains the first coefficient register, the first input register 2, the first multiplier 3, the first register 4 of the product, the second register 5 of the coefficient, the second input register 6, the second multiplier 7, the second register 8 of the product, the generator 9 clock pulses, trigger 10, the third input register 11, adder-subtractor 12. The device for performing the fast Fourier transform works as follows. The arithmetic operations performed during the basic operation, including multiplication by the turning factor W, can be written in real form as follows: ReC (ReC., ImW,), (1) ReAi HReA. + (ReC; ReW-ImC-. ImW; ), (2) ImC; (ReCi ImW + ImC- ReV,), (3) ImA ImA.-f (ReCi ImW- + ImCf ReW.), (4) where A;, C are input complex operatives; A, C - output complex operands; Vi is the complex coefficient; Re is the real part of the complex number; Im is the imaginary part of a complex number. For the sake of simplicity, the invention assumes that writing data to registers 1, 2, 4, 5, 6, 8. 11 and switching trigger 10 takes place in infinitely small time, and the delay introduced by multipliers 3 and 7 and adder-subtractor 12, does not exceed the duration of the clock pulse at the output of the generator. 9 clock pulses. 1 In the proposed device, adder-subtractor 12 functions in accordance with the table, where the high level of the signal is designated as 1, anisky - O, B, the initial moment to the synchronization input of the device receives a high signal. This signal prohibits the operation of the generator 9 clock pulses and the trigger 10. At the same time, a low level signal is set at the generator output 9 clock pulses and the forward output of the trigger 10. When the first operand (ReCo) arrives at the input of the device operand, a low level signal is set at the synchronization input of the device, thereby allowing the generator to operate 9 clock pulses and a trigger: GO. The frequency of the 9-clock pulse generator is such that one of the operands ReC-,, ImC-, ReA, ImA., Is fed to the input of the device operand setting for half the clock pulse period, and each of the coefficients ReW- ,, ImW ;, one pa-. Clock cycle. The mutual arrangement of such pulses, operands and coefficients is shown in FIG. 2. Before proceeding with the conversion of the entire array of input operands, the device operates as follows. At the time of arrival of the ReC operand; on the input, the operand of the device, the trigger 10 of the under-action, the negative edge of the clock pulse coming from the generator output 9 of the clock pulses is set to the zero state, i.e. the inverse output of the trigger 10 is set to a state of logical one.

Registers 1, 2, 4, 5, 6, 8, 11 record data arriving at their D inputs on a positive edge at the C inputs. Therefore, when the ReC operand is fed to the device input and the trigger 10 is switched to the zero state, at the output of register 2, the value of ReC is established (Figs. 1 and 2).

At the time of formation of a logical unit by the generator of 9 clock pulses, the input of the real part receives the coefficient ReV, to the input of the imaginary part 1t1, to the input of the operand's job - ImA-, which are recorded in registers 1, 5 and P, respectively, on the positive edge of the clock generator 9 clock pulses.

The negative edge of the clock pulse switches the trigger 10 to one state, i.e. at the direct output of the trigger 10 a logical unit is formed. A positive differential on the non-inverse output of the trigger 10 writes into the register 6 the ImC operand, which arrives at this moment at the input of the device.

At the moment of generation of the second clock pulse by the generator 9, the record of the ReA operand is swept down the input of the device. It also records the ReVJ-j and ImC.- ImW works that had been formed by this time in registers 4–8, respectively.

In the first cycle, the adder-subtractor performs actions according to the ratio of the SP, in the second cycle - according to the ratio (.). As a result of this, new ReCI and ReA values are formed at the output of the device. . At that moment when the adder-subtractor generates the values of ReC | and ReA | Registers 1 and 5 accept ImV coefficients. and ReV, respectively. The outputs of the multipliers 3 and 7 are the products of ReC, - ImW and ImCj ReW; (Fig. 1 and 2).

At this point, the adder-subtractor ends the formation of the ReC; and ReA and on the positive edge of the clock pulse of the product ReC ImW and ImC-ReW; recorded in register67431

4 and 8, respectively. And in the register 1 1, the operand ImA is written on the same signal. arriving at the input of the device. As a result of this, on the third cycle, the adder forms an ImC value at the output of the device. , on the fourth cycle IiTiAi.

The operation of the device is then repeated and the following values of ReC, ReA., ImC, and ImAj 4 are calculated (Fig. 2).

Claims (1)

Invention Formula A device for performing the Fourier transform containing the first coefficient register, the output of which is connected to the first input of the first multiplier, output - which is connected to the information input of the first work register, the output of which is connected to the first input of the adder-subtractor, the output to-cost is the information output of the device, the inputs of the real and imaginary parts of the coefficient of which are the information inputs of the first and second registers, respectively the second input of the first multiplier is connected 30 to the output of the first input register, the information input of which is combined with the information inputs of the second and third input registers and is the input of the operand job 35 devices, a clock pulse generator, a second register of products, characterized in that, in order to maintain speed, a trigger and a second multiplier are entered into it, the output of which is connected to the information input of the second register of products, the output of which is connected to the second input of the adder-subtractor, third entrance 5 of which is connected to the output of the third input register, the clock input of which is combined with the clock inputs of the first and second coefficient registers, the first and second registers of the works, the clock input of the trigger, the first control input of the adder-subtractor and connected to the output of the clock generator, the start input of which is connected to the trigger input and is the device sync input, the inverse trigger output is connected to the second control the adder-downstream input and the clock input of the first input register; the forward trigger output is connected to the clock input of the second input 267431ft register, the output of which is connected to the first input of the second multiplier, the second input of which is connected to the output of the second register of the coefficient. ffxffd7 & O. block e output and block W of the subunit w In the course of G Input2 VlodZ Howl SitOKo 2 Out. block B Out blocks out block 7 Out. L / d block. block 8 Out block 11 boixod