SU1156090A1 - Adamard transform device for digital sequences - Google Patents

Abstract

CONSTRUCTING ADAMAR FOR DIGITAL SEQUENCES CONTAINING, containing a clock generator, registers, AND groups, an adder, characterized in that, to simplify the device, it contains two counters, a conversion unit to the add-on code and a modulator two, and the clock generator output is connected to the first inputs of the elements of the first group and to the synchronizing input of the first register, sequentially the information input of the first register is connected to the source of a single signal, and the installation input of the first register - to the output of the first element And the first group, the output (wi-l) -ro bit of the first register (t-digit processed numbers) is connected to the second input of the first element And the first group, the inverse output of the first digit of the first register connected to the second input of the second element AND of the first group, to the control input of the second register and the counting input of the first counter, the outputs of which are from the first by n (and the number of Walsh functions in the basic system) are connected to the first inputs of the corresponding elements And the second groups in the stroke of the P-th bit of the first counter is connected to the counting input of the second counter, the outputs of which are ranked from first to second, are connected to the second inputs of the corresponding elements AND of the second group, whose outputs are connected to the inputs of modulo two, the output of adder modulo two under (L is key to the control of the input of the conversion unit to the additional code, the output of which is connected to the first input of the adder, the second input of the adder is the information input of the device, and the output of the adder is bitwise connected to the informat The input of the first group of m bits of the second register, the shift input of which is connected to p; the output of the second element AND of the first group, the output of the first group of m bits of the second register is connected to the info input of the conversion unit to the additional code, the output of the group of hectares The second register is the output of the device.

Description

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The invention relates to automation and computing and can be used in audio and video signal processing equipment, for digital filtering, etc.

The aim of the invention is to simplify the device.

Functional diagram of the device shown in the drawing.

Skem contains clock generator 1, shift register 2, block 3 conversion into an additional code. the adder 4 J register 5 shift, the elements And 6 and 7, the counter 8, the modulo two 9, the counter 10, the elements And 11.

The device works as follows.

The input elements F (k) of the input signal (K 1-2, K1 is the order of conversion), represented by the t-bit binary numbers, are sequentially received at the input of elements And 11. The values of the argument (K number of samples) are counted by the counter 10. D When the value of the argument is sequenced, the values of all 2 Walsh functions are received, which are fed to the control input of the conversion unit 3 to the additional code. The formation of the Walsh functions involves a counter 8, a group of elements And 7, and a modulo-two adder. 9. The intermediate transformed results are accumulated in the m2-shift register 5 of the shift. Each transform coefficient corresponds to a group of m bits of register 5. A subsequent intermediate value

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Ck + 1 of the coefficient is obtained as a result of the operation F (k) + Ck, performed using the conversion into an additional code 3 and adder 4, and the sign of the operation1- (and is determined by the value of the Walsh function. Control of the register 5 when reading intermediate results and writing the new pulses produced by the shift register 2 together with the elements of AND 6. The operation cycle of blocks 2 and 6 is m cycles, during which the register 2 is filled with units, and then reset to zero at the setting input R. At the beginning of each The cycle synchronizes the reception of the result of the summation on the adder 4 to the first group of m bits of register 5, then the information from each previous group of m bits to the next group is shifted for a long time. The conversion results after processing the 2nd input sample are stored mc in register 5 and can be sequentially output through the last group of m bits.

The proposed device is much easier known. So, for processing an input matrix of 256 X 256 size in a known device, 65536 adders are required, for a matrix of 1024 x 1024 - 1048576 adders, etc. ., while the proposed solution makes it possible to dispense with one adder regardless of the dimension of the matrix.

Claims (1)

ADAMAR TRANSFORMATION DEVICE FOR DIGITAL SEQUENCES, containing a clock generator, registers, groups of elements AND, an adder, characterized in that, in order to simplify the device, it contains two counters, a conversion unit to an additional code and an adder modulo two, and the output of the clock generator is connected to the first inputs of the AND elements of the first group and to the synchronizing input of the first register, the serial information input of the first register is connected to the source of a single signal, and the installation input of the first reg Istra - to the output of the first element AND of the first group, the output (wi-l) -ro of the discharge of the first register (t is the bit capacity of the processed numbers) is connected to the second input of the first element And of the first group, the inverse output of the n'th discharge of the first register is connected to the second the input of the second AND element of the first group, to the control input of the second register record and the counting input of the first counter, the outputs of the digits of which from the first to the ηth (2 "is the number of Walsh functions in the base system) are connected to the first inputs of the corresponding elements of the second group, output Pth bit Yes, the first counter is connected to the counting input of the second counter, the discharge outputs of which from the first through the Ith are connected to the second inputs of the corresponding elements of the second group, the outputs of which are connected to the inputs of the adder modulo two, the output of the adder modulo two is connected to the control input of the unit conversion into an additional code, the output of which is connected to the first input of the adder, the second input of the adder is the information input of the device, and the output of the adder is bitwise connected to the information inputs of the first group of w bits of the second register, the biasing input is connected to the output of the second AND gate of the first group, the output of the first group of m bits of the second register is connected to the data input of the conversion unit in the additional code output 2 ⁿ -th group of ni bits of the second register is an output device.