SU1672441A1 - Multiplying unit - Google Patents

Abstract

The invention relates to digital computing and is intended to multiply and shift the numbers represented in the binary number system, and can be used in high-performance computers and systems. The purpose of the invention is to extend the functionality by performing a shift operation by introducing a shift parameter generating unit, two code rotation blocks, a switch, a counter, and changing links. 6 Il.

Description

The invention relates to digital computing and is intended to multiply and shift the numbers represented in the binary number system, and can be used as an operating unit in high-performance computers and systems.

The aim of the invention is to expand the functionality of the device by performing a shift operation. . In the device operands are positive

P

the numbers are represented as A ai2.

i 1

ai Ј. {Oh, 1}, where A ai32 ... an is a binary n-bit code of the number A. The execution of the multiplication operation in the proposed device, as well as in the known one, is based on the table-algorithmic multiplication method, one Unlike in the proposed device, the multiplication process is pipelined by combining in time the production of elementary products and accumulating the sum of partial products.

pp

Let X Јх | 2 and Y V y, 2 multiplicative

i 1i 1

and a factor, respectively, where x :, yi is the value of the 1-bit codes of the factors. Then, a 2n-bit binary code is required to represent the exact result of Z X-Y.

The process of calculating the product Z is written as

p / p p / p Z Z (Y, 2Xi (2p) W

eleven

i 1

(one)

(L

WITH

about

vj

Yu

t

where% xi XH-I ... XI + P-I is a 1-digit coded code of a multiplicable code in the canonical positional number system with base q 2P;

Y) is binary-coded and the digit of the multiplier code

Thus, the multiplication process consists of repetitive cycles of the same type. During the next j-ro cycle j-e

etc

partial product YI X | 2 rg you 1

is numbered on - multipliers that perform the operation of multiplying the p-bit binary code Y by the p-bit binary code Xi to form a product of 2p and create the binary code of the partial product X-Yj by adder.

The presence of the register of partial products with appropriate control allows organizing a pipeline when calculating Z, when at the same moment of time a partial product of XYj is formed on one adder, and the sum of partial products Zj Zj-i 2 p + XYj is formed on another adder moreover, Z0 О, Z Zk.

The execution of the shift operation in the device is based on the fact that the shift operation to the left is similar to multiplying the shifted binary code by the corresponding power of 2.

Let d be the number of shifts (i.e., the number of bits by which the binary code must be shifted). Then the shift to the left will be similar to multiplying the shifted code by the number 2. With a large d, multiplication is not profitable due to the large number of cycles of multiplication. Therefore, the binary code of the number of shifts is decrypted and the resulting unitary code is divided into groups of p bits. Let the r-th group of p bits

(g, - closest to a integer,

such that aa, C is the bit width of the number of shifts d) is I (we call this group of p bits the shift parameter C), then multiply by the rth group of p bits using the multiplier equipment and g-1 (this number is we call the shift parameter M, M g- 1) the hardware shift by p bits.

The number of shifts M per p bits is monitored with a counter and executed on a shift register, which can be implemented, for example, with an oblique transfer.

Shift to the right is similar to the shift to the left of the rotated code. Rotate the code to call the following transformation. Let the binary n-bit code of B have the form B bib2 ... bn, then after the rotation it has the form ... b2 bi.

Therefore, when shifting to the right, the shifted code needs to be rotated,

0

five

0

five

0

five

0

five

0

five

shift left and rotate the resulting code again.

Figure 1 shows the block diagram of the computing device; nafig, 2 — example of implementation of a code rotation block: in FIG. 3 — an example of realization of a shift parameters generating block: in FIGS. 4-6, relative time diagrams of signals at the outputs of the microprogram control unit during device operation

The device contains (see Fig. 1) the registers of multiplicable 1 and multiplier 2. multipliers Зг-Зк, adder 4 elementary products, adder 5 partial products, unit 6 for forming shift parameters, unit 7 for microprogram result, counter 8, second unit 9 for code rotation , switch 10, registers 11 and 12 of the partial product and result, respectively, the first block 13 of rotation of the code, the outputs 14-24 of block 7, the inputs 25 of the address of the first microcommand, the clock input 26 and the input 27 of the end of operation of block 7, the input 28 of the number of device shifts.

Block rotation code 9 (13) contains (see Fig.2) contains the first 29 and second 30 groups of elements And the group of elements OR 31.

The shift parameter generating unit 6 (see FIG. 3) contains a decoder 32, a first 33 and a second 34 groups of OR elements, an encoder 35.

Counter 8 is designed to count the performed shifts per pits of bits and cycles of multiplication and issue a signal of the completion of operations.

Block 9 of rotation of the code is designed to transfer to the register multiplicand 1 multiparame

go or shifted code x x) in nor 1

or with rotation depending on the direction of shear.

The switch 10 is designed to transmit to the register multiplier 2 multiplier or parameter shift C.

The multiplier 1 register is for storing the multiplicable or shiftable code X.

The register of the multiplier 2 is shift, p-razdrny, and the shift is carried out in the direction of the younger ones by p bits. Designed to store the multiplier Y or the shift parameter C.

The multipliers 3m. 3. 3c are designed to calculate the next elementary product XiYj, i 1К, have two p-bit inputs and a 2p-bit output.

The adder of 4 elementary products, two-input, n-bit, is intended to form the highest n bits of the partial products Y | X, j - 1. 2K.

The n + p-bit register of partial products 11 is intended for storing partial products of YjX, whose n bits come from adder A and the lower p bits from multiplier 3i.

The adder of 5 partial products is two-input, p p-bit. designed to add two terms

The result register 12 is n + p-bit shift, with the shift being towards the higher bits. Designed to store the results of multiplication or scaling.

The code turning unit 13 is designed to output the result of performing a multiply and shift operation coolly and normally, or with rotation if the shift is to the right.

When performing the multiplication opposition, the device works as a slice,

In the initial state, the registers 1,2. 11, 12 are zeroed (reset and power are not shown in figure 1; According to signals from block 7 (at outputs 16, 17, 13, 24. 18) the multiplicand X is received by block 9 of rotation of the code to the register of multiplicand 1, the multiplier Y through the switch 10 is received by the register of multiplier 2 and from block 7 to counter 8 is received the number multiplication cycles

In each cycle of multiplying X by successive p-bits, hook signals are received to the control inputs, as shown in Fig. 4. The number of cyclic multiplications is K; etc.

In the first (j t 1) cycle, the K elementary products XiYr, i - 1, 2, ... K, are formed by the output 21 of the block 7 at the multipliers 3b..3k, and by the signal at the output 20 of the block 7 they are collected on adder 4 and the partial product is written to register 11, at the same time there is a shift of the multiplier by p bits in the register multiplying .- / -; 2

In subsequent cycles, X is multiplied by successive r bits of Y with simultaneous addition of a partial product with the contents of register 12. shifted by p bits in the low-order bit by using oblique transmission on the adder 5 according to the signal at the output 21 of the control unit, then assembling the next partial product on the adder 4 and receiving it on the register 1 1 with a simultaneous shift by p bits, the contents of register 2, and then receiving the lower p bits of the register 2 lower p bits of the register 12 according to the signal at the output 19 of the control unit.

In kahdom cycle. At the output 21 of block 7, the signals multiplied simultaneously with cm-cash at the output of 15 counts the cycles on the counter.

After completion of the addition, on the accumulator 5 n of the last cycle (j: K) on register 12, the master digits of the product code appear on register 2 n-p of the lower bits of the product code.

The end of the multiply operation is signaled by a counter.

When performing a shift to the left, the device operates as follows.

In the initial state, registers 1,2, 11, 12 are reset. The control inputs receive signals like this. as. this is shown in figure 5.

According to the signals of block 7 at the outputs (16, 17.18, 23, 24), the shifted code through the code rotation block 9 in the normal form is received on the register 1. On the register 2 through the switch 10, the shift parameter C is received and in the counter 8 - the shift parameter M.

Then, the signal at the output 21 of the control unit 7 on the multipliers S1 ... 3k leads to the formation of K elementary products Xj C. i 1. 2K. and on signal to

output 20 of block 7, they are collected on adder 4, and the partial product is stored on register 1 1. Then, by a signal on output 2 1, the partial product is added to zero and the result is stored on register 12.

The signals at output 15 produce the required number of shifts to the left by p bits, with simultaneous feeding of signals to the counting input of the counter according to the signals at output 22 of block 7. At the end of the shift, the result is in the lower bits of register 12.

When the right shift operation is performed, hook signals are sent to the control inputs. as shown in Fig.6. The difference from the shift to the left is that according to the signals (17. 17. 23, 24. 18) (the shifted code through the block 9 of the rotation of the code with rotation is taken into register 1

The process then repeats in a manner similar to a left shift.

At the end of the shift operation, the result is removed from the register 12 through the block 13 reversal of the code and with the rotation of the code.

Claims (2)

Invention Formula A multiplier device containing multiplier and multiplier registers. To multipliers (K p / p, where n is the width of operands, p is the number of simultaneously processed operand bits), adder of elementary, products, register of partial products, adder of partial products, register of product and unit of microprogram result, and the input of the first factor of each multiplier connected to the output of the corresponding p bits of the register of the multiplicand, and the input of the second factor to the output of the lower bits of the register of the multiplier, the inputs of the bits of the first term of the adder elementary produced It is connected respectively to the outputs of the higher order bits of each multiplier, the outputs of the lower order bits j-ro multiplier Q 2 .... K) are connected respectively to the inputs (pj - p) -x of the bits of the second term of the adder of elementary products, the outputs p of the lower bits of the first multiplier are connected respectively with the inputs of the lower bits of the register of partial products, the inputs of the subsequent bits of connected to the outputs of the corresponding bits of the adder of elementary products, and the output is connected to the input of the first term of the adder of partial products, the input of the second term of which is connected to the output of the result register, information input cat The op is connected to the output of the partial product adder, the summation resolution input of which is connected to the result register recording input, the control input K to the multipliers, and the first output of the microprogram control unit, the second output of which is connected to the register input of the multiplicand and the first input of the multiplier register, whose shift input connected to the input of the register of partial products, the resolution of the summation of the adder of elementary products and the third output of the microprogram control unit The fourth output of which is connected to the shift register input of the result, characterized in that, in order to expand the functionality by performing a shift operation, a shift parameter generation unit, first and second code rotation blocks, a switch and counter, the installation input of which is connected to the fifth output of the microprogram control unit and the first output of the shift parameters generating unit, the second output of which is connected to the first information input of the switch, the second information input of which is connected to the input of the device multiplier, and the output to the first the information input of the register multiplier, the second information input which is connected to the output p of the lower bits of the result register, and the second recording input is connected to the sixth output of the firmware control block, the second output of which is connected to the information input of the counter, the counting input and output of which are connected respectively to the seventh output and the input of the end of the operation of the firmware control block, the eighth and ninth outputs of which are connected respectively, with the first and second control inputs of the switch, the output of the result register is connected to the information input of the first rotation unit of the code, the output of which is connected to the output of the device, and the first and second control inputs, respectively, with the tenth and eleventh outputs of the firmware control unit and the first and second control inputs of the second code rotation unit, whose information input is connected to the input of the multiplicand device, and the output to the information input of the multiplicable register, operation code input and the control input of the device are connected respectively with the input of the address of the first microcommand and the clock input of the microprogram control unit, the input of the unit for forming the shift parameters is connected to the input of the number of device shifts. Automatic Time Auto Roll Fig 5 LKtomatichsko (brep t -aff