SU1357948A1 - Device for reducing polynominals by movduli of cyclotomic polynominals - Google Patents

Abstract

The invention relates to computing and is intended 32 for use in digital signal processing systems. The device implements an iterative algorithm for calculating polynomial residues modulo irreducible polynomials. In order to reduce hardware costs to a device containing registers 5-7, counters 1-3, elements OR 21–23, groups of elements AND 9–11, delay element 25, comparison element 27, adder 17, group of elements OR 19, element NOT 24 and trigger 28, entered register 4, element OR 20, group of elements AND 8, element 26 of comparison, subtractor 29, group of elements 18 of delay, memory blocks 15, 16, multiplexers 13, 14 and demultiplexor 12. 2 Il. i (L SLE SP with 4 00 ful I

Description

The invention relates to computing and is intended for use in digital signal processing systems.

The purpose of the invention is to reduce the cost of equipment.

. FIG. 1 shows a functional diagram of the device; on. 2 - the cyclogram of his work.

The device contains counters 1-3, register 4-7, groups of 8-11 elements And, demultiplexer 12, multiplexers 13 and 14, blocks 15 and 16 of memory, adder 17, group 18 elements for 1357948 2

In the first stage (their number N / 2), are used for a similar procedure in the second stage: a, a

W o

 m- {n /)

INlt)

   N + i 1 (H / 4Ul

 0 "/ -b N (N; I) + I The resulting differences are the coefficients (BO (HM1-I iNM) -i with variables z, z,

.,., z, z ° of the polynomial X (z) mod (z +1)

five

   m.

The device operates as follows: reset to the initial state of counters 1-3 and registers 5-7. Then, the input 31 receives a code that corresponds numerically to half of the input array, i.e. N / 2, and is written to the shift register z. After that, the input array fx is processed; (. The input words are pavah x- are coefficients of poly t / N-1 nome X (.z; x z +,

+ X

and the amounts (their number is N / 4) are used in the next step, etc. Thus, at each stage the sums and differences of numbers taken in pairs in a certain order are formed, and at the first stage the number of sum-holdings, a group of 19 OR elements, items and subtractions is N / 2, then the elements OR 2P- 23, element 24, element is halved from stage to stage 25 delay, elements 26 and stage 27. The total number of stages, log ,, N comparison, trigger 28, -calculator 29, inputs 30-33 reset, initial data, synchronization and informational 20 times. . and output 34 of the device. Before starting the calculation, modulation of irreducible polynomials is the first step in implementing a convolution (or correlation) algorithm based on polynomial transformations. For this purpose, the input sequence is fx ;, where i O, 1 , ..., N-1, must be represented as a polynomial of degree

N-1 variable z, and the input is 30 parallel codes to the input 33. So

as the counter 2 is in the zero state, the control input of the multiplexer 12 through the element OR 21 receives a zero signal, which switches the information input to the first input of the first multiplexer 13, the control input of which has a zero potential, switching to the output The first input of this multiplexer is 40. Thus, the input words x are fed to the information input of the first memory block 15. To the address inputs of memory blocks 15 and 16, information comes from output 45 of register 4, and not to: go from output

counter 1, having a length of the discharge grid, log, 2 (N / 2). In order to eliminate races, the recording in memory blocks 15 and 16 is synchronized on input 32. Information that records the entire second memory block 16 is indifferent at the first N / 2 clock cycles. 3, this percode accumulates the first half of the samples in the first memory block 15.

On the trailing edge of the (N / 2) -synchronous pulse, counter 1 is reset to the zero state, and counter 2 changes to a state equal to one. The transfer function H (z) + ... + + h, z + hp is similar. The output polynomial Y (z) is calculated as the product of X (z) and H (Z) modulo some polynomial P (z): Y (z) X (z) H (z) mod P (z) ... + y , z + Od. The recovery of the polynomial Y (Z) by the Chinese theorem on residues for polynomials results in the output sequence YU where O, 1, ..., N-1.

The device implements the following method for calculating the polynomial residues modulo irreducible polynomials z-1, z + 1, z2 + 1 ,, .., 1. At the first stage, the sums and differences of the input data of the array are calculated.

W:

I-

0 + Hc, 2,

a ,, x,

+ x

lN | i) (N (2) - N (2) - bJ-i

N (Z

(z

(N (2) 41 X, - X

a

L) / 2 +1} f

Differences on. (/ g) - N-1

The following steps are not used and are coefficients for the variables, r (, ..., z, z ° of the polynomial X (z) mod (1). Sums, semi55

In the first stage (their number N / 2), are used for a similar procedure in the second stage: a, a

W o

 m- {n /)

INlt)

   N + i 1 (H / 4Ul

 0 "/ -b N (N; I) + I The resulting differences are the coefficients (BO (HM1-I iNM) -i with variables z, z,

.,., z, z ° of the polynomial X (z) mod (z +1)

   m.

The device works as follows, and the deductions are N / 2, g, then it is halved from stage to stage. The total number of stages log ,, N time. . Before the start of the calculation, produ 5

It is reset to the initial state of counters 1-3 and registers 5-7. Then, the input 31 receives a code that corresponds numerically to half of the input array, i.e. N / 2, and is written to the shift register z. After that, the input array fx is processed; (. Input words are received by parallel codes to input 33. So

never mind The single signal from the low-order counter 2, passes through the OR 21 element, switches the demultiplexer 12, the first multiplexer 13, and also allows you to receive data in registers 5 and 6 and read the counter 3. The output signal from the low-discharge counter 2 connects the output the second multiplexer 14 to its first input. Input counts X; starting with (N / 2) -ro, through the demultiplexer 12 and the second multiplexer 14 are sent to register 6, at the same time the register from the memory block 15 recorded at the zero address enters the register 5. From the outputs of the registers 15 and 16, information is fed to the adder 17 and the subtractor 29. Thus, a simultaneous calculation is also performed on (N / 2) -M

 X,

respect

Hn1g and

 k / g

 x „- X

N (2Raz n / g x and goes to the output

34 devices through a group of 19 elements OR. The sum a Xd + goes to the first inputs of groups 8 and 10 of the elements I. At the inverse output of the trigger 28 there is a unit potential that opens a group of 8 elements And and closes a group of 10 elements I. Therefore, N / 4 sums x; + x, (i O, 1, ..., (N / 4) - 1) is recorded in memory block 15 at addresses O, 1, ..., (N / 4), - 1 (old data x, x ,, ..., are no longer required).

Starting from the second iteration, the operation of counter 3. When it reaches the value of N / 4, a single signal appears at the output of the comparison element 27, which flips trigger 28 into one state, resulting in a sum from the output of adder 17 starting from (M / 4) th on the memory block 16.

On the trailing edge of the (N − 1) th clock pulse, counter 1 is reset to the zero state. The counter 3 with a single signal from the output of the comparison element 27 is reset to zero. When the counter reaches 3 N / 4, trigger 28 is reset to zero. Counter 2 enters a state equal to two, thereby opening the group 11 of the elements AND, and keeping the state of the multiplexer 13 the same. In this case, the multiplexer 14 is switched by a zero signal from the output of the lower bit of the counter 2. When the counter 2 changes to a state equal to two, the single signal

- s

Sh

15

20

thirty

35

40

25

t

45

50

55

from its high-order, opens a group of 11 AND elements, and the contents of register 7 goes to comparison element 26. Therefore, at the second iteration, when the contents of the first counter 1 reach the value N / 4, a single signal appears at the output of the comparison element 26, resetting the first counter 1 to the zero state and shifting the contents of register 7 by one bit to the lower bits, t. e. its value becomes N / 8. The process then repeats until the mth iteration (ha), where the last sums and the difference between the adder 17 and the subtractor 29 are calculated. The single signal from the low bit of register 7 opens a group of 9 AND elements and the last sum goes to the output 34 of the device.

Thus, in the first stage, the remainder X (z) is obtained modulo

N (2N / 4

Z + 1, in the second modulo z + 1, ..., at the last m-th stage, two residues XOz) mod (z + 1) and X (z) raod (z-1) are obtained,

Claims (1)

 Invention Formula A device for converting polynomials modulo cyclotomic polynomials, containing three registers, three counters, three OR elements, three AND groups, a delay element, the first comparison element, an adder, a group of OR elements, a NOT element, and a trigger whose direct output is connected to the first input of the first group of elements I, the input data of the device is connected to the information input of the first register, the output of which is connected to the first input of the first comparison element, the output of which is connected to the counting trigger input, input sat the device wasp is connected to the reset inputs of the first, second and | third registers and the first inputs of the first and second OR elements, the output of the second OR element is connected to the reset input of the first counter, the output of which is connected to the second input of the first comparison element, The second counter is connected to the first and second inputs of the third OR element, the output of which is connected to the recording resolution inputs of the second and third registers, which is topics five what, 1357948 for the purpose of scraro hardware costs., it contains the fourth register, the fourth element OR, the fourth group of elements AND, the second element of comparison, the subtractor, the group of elements of the delay,  two memory blocks, two multiplexers and a demultiplexer, whose information input is the information input of the device, the sync input. which is connected to the synchronization inputs of the first and third counters, the second, third and fourth registers and through the element NOT to the recording resolution inputs of the first and second memory blocks, address  the inputs of which are connected to the output of the fourth register, the information input of which is connected to the first input of the second comparison element and the output of the first counter, the transfer output of which is connected to the counting input of the second counter, the higher bit output of which is connected to the device, the reset input of which is connected to the second input of the fourth element OR, the output of which is connected to the reset input of the third counter, 5, the first output of the demultiplexer is connected to the first information input of the first multiplexer, the output of which is connected to the information input of the first memory block, the output of which 10. Connected to the information input  the second register, the output of which is dinane with the inputs of the decrement and the first term of the subtractor and the sum of the torus, respectively, the output of sum f5 pa is connected to the first inputs of elements AND of the fourth group and the second inputs of elements AND of the first and third groups, the outputs of elements AND of the first group are connected to informational 20 inputs of the second memory block, the output of which is connected to the first information input of the second multiplexer, the output of which is connected to the information input of the third register the primary inputs of the elements and the second group whose output is connected to the inputs The output of which is connected to the second input of the second comparison element, the output of which is connected to the first input of the fourth OR element and through the delay element to the shift control input of the first register, the output of the senior bit of which is connected to the second input of the first OR element, the output of which is connected to the input reset the second counter, the output of the younger digit of the first register is connected to the first inputs of the elements AND of the third group, the outputs of which are connected to the inputs of the corresponding elements of the delay group, the outputs of which are connected Nena element to the first inputs, cops OR group, the outputs of which form the information output apparatus is reset input connected to a second input of the fourth OR gate, whose output is connected to the reset input of the third counter, The first output of the demultiplexer is connected to the first information input of the first multiplexer, the output of which is connected to the information input of the first memory block, the output of which connected to information input  The second register, the output of which is connected to the inputs of the decremented and first term subtractor and adder, respectively, the output of the adder is connected to the first inputs of the elements of the fourth group and the second inputs of the elements of the first and third groups, the outputs of the elements of the first group are connected to information the inputs of the second memory block, the output of which is connected to the first information input of the second multiplexer, the output of which is connected to the information input of the third register. the subtractor and the second term of the subtractor and the adder, respectively, the subtractor's outputs are connected to the second inputs of the elements of the OR group, the inverse trigger output is connected to the second inputs of the elements of the fourth group, whose outputs are connected to the second information inputs of the first multiplexer, the control input of which is connected to the output the third element OR, the resolution enable input of the first counter and the control input of the demultiplexer, the second output of which is connected to the information input of the second multiplexer The control input of which is connected to the low-voltage output of the second counter.