RU2007036C1 - Device which produces members of multiplicative groups of galois fields gf(p) - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has multiplication unit 1, multiplexer 2, three OR gates 3, 4, 5, two registers 6, 7, memory unit 8, switches unit 9, adder 10, subtraction unit 11, two comparison circuits 12 and 13 and delay gate 14. EFFECT: increased speed. 1 dwg

Description

 The invention relates to computer technology and can be used in digital computing devices for generating code recursive sequences, the construction of which is based on the theory of finite fields.

 A device is known for generating a remainder modulo an arbitrary number, containing a memory unit, an adder, a multiplexer, two registers, a subtractor, an AND block, two comparison circuits, OR elements with corresponding functional relationships [1].

 This device has narrow functionality.

 The closest in technical essence to the proposed one is a device for forming elements of multiplicative groups of Galois fields GF (P), containing a multiplication block, three OR elements, a register, an adder and a delay element with corresponding functional relationships [2].

 The disadvantage of this device is its low speed.

 The aim of the invention is to improve the performance of the device.

 The goal is achieved in that in a device for forming elements of multiplicative groups of Galois fields GF (P) containing a multiplication unit, first, second and third elements OR, a first register, adder and delay element, and the input of the value of the antiderivative element of the device is connected to the input of the multiplier register multiplication unit, the zero input of which is connected to the installation input of the device, the input of writing the value of "unity" of which is connected to the least significant bit of the register of the multiplicable multiplication unit, and the output of the device is connected to the input the register of the multiplier block of the multiplication, the multiplexer, the second register, the memory block, the key block, the first and second comparison circuits and the subtracter are introduced, while the device start input is connected to the multiplication enable input of the multiplication block, the outputs of which are connected to the inputs of the first group of the multiplexer, the outputs of which are connected respectively, with the information inputs of the first and second registers, the output of the second register is connected to the output of the device, the task input of the module of which is connected respectively to the address inputs of the memory unit, by the moves of the first group of the subtractor and the inputs of the first groups of the first and second comparison circuits, the outputs of the memory block are connected to the inputs of the first group of the key block, the inputs of the second group of which are connected to the outputs of the first register, the outputs of the key block are connected to the information inputs of the adder, the outputs of which are connected respectively to the inputs the second groups of the first comparison circuit, the subtractor and the multiplexer, the inputs of the third group of which are connected respectively to the inputs of the second group of the second comparison circuit and the outputs of the subtractor, output " more than the first comparison circuit is connected to the control input of the second comparison circuit, the output of which is “less” is connected to the first inputs of the first and second elements of OR, the output of the end of the multiplication of the multiplication unit is connected to the first input of the third element of OR, the second input of which is connected to the second input of the second element OR and an output “greater than” the second comparison circuit, the output “less” of the first comparison circuit is connected to the first control input of the multiplexer and to the second input of the first OR element, the output of which is connected to the permission input the second register is the output of the read permission of the device, the output of the second OR element is connected to the second control input of the multiplexer, the output of the third element is connected to the control input of the memory block, the write enable input of the first register and the input of the delay element, the output of which is connected to the control input of the first comparison schemes.

 Functional diagram of a device for forming elements of multiplicative groups of Galois fields GF (P) is shown in the drawing.

 The device comprises a multiplication unit 1, a multiplexer 2, first, second and third elements OR 3, 4 and 5, first and second registers 6 and 7, a memory unit 8, a key unit 9, an adder 10, a subtractor 11, the first and second circuits 12 and 13 comparison, the delay element 14, the installation input 15, the input resolution enable entry 16, the entry value 17, the input 18 of the antiderivative element value, the module input 19, the information output 20 and the read permission output 21 of the device with corresponding functional relationships.

 A device for forming elements of multiplicative groups of Galois fields GF (P) works as follows.

, где k - максимальная разрядность произведения, по модулям p_j, с которыми предлагается работа устройства. Перед началом работы на вход 15 поступает импульс, который обнуляет регистры множимого и множителя блока 1, на входы 19 подается код модуля, который поступает на информационные входы блока 8 памяти и вторые входы вычитателя 11 и схем 12, 13 сравнения, в регистр множителя блока 1 подается с входа 18 двоичный код числа первообразного элемента θ_i , в регистр множимого блока 1 по входу 16 записывается "единичный" элемент. При подаче импульса на вход 17 устройство начинает выполнять операцию умножения. Блок 1 умножения умножает единицу на θ_i и выдает результат умножения на свои выходы, который через третьи входы мультиплексора 2 поступает на информационные входы регистров 6 и 7. Сигнал окончания умножения с выхода блока 1 умножения через первый вход элемента ИЛИ 5 поступает на вход разрешения считывания блока 8 памяти, на вход разрешения записи регистра 6 и на вход элемента 14 задержки. При этом в регистр 6 через мультиплексор 2 происходит запись кода произведения, а на выходах блока 8 памяти появляются остатки от чисел 2ⁱ, i =

, по модулю p

блок 8 памяти имеет k групп выходов, каждая из которых состоит из l разрядов, необходимых для представления остатков чисел 2ⁱ по модулю p_i.In the initial state, registers 6 and 7 are reset. In block 8 of the memory pre-computed previously calculated residues from the numbers 2 ⁱ , i =

, where k is the maximum capacity of the product, by the modules p _j , with which the device is proposed to work. Before starting work, an impulse arrives at input 15, which resets the multiplier and multiplier registers of block 1, the module code is received at inputs 19, which is fed to the information inputs of memory block 8 and the second inputs of subtractor 11 and comparison circuits 12, 13, into the multiplier register of block 1 a binary code of the number of the antiderivative element θ _i is supplied from input 18, a “unit” element is written to the register of the multiplied block 1 at input 16. When applying a pulse to input 17, the device starts to perform the multiplication operation. The multiplication unit 1 multiplies the unit by θ _i and outputs the result of the multiplication to its outputs, which through the third inputs of the multiplexer 2 goes to the information inputs of the registers 6 and 7. The signal for the end of the multiplication from the output of the multiplication unit 1 through the first input of the OR element 5 goes to the read permission input block 8 of the memory, the input enable recording register 6 and the input element 14 of the delay. In this case, the product code is recorded in register 6 through the multiplexer 2, and the residues from the numbers 2 ⁱ , i =

modulo p

the memory unit 8 has k groups of outputs, each of which consists of l bits necessary to represent the remnants of the numbers 2 ⁱ modulo p _i .

, для тех i, для которых коэффициент a_i = 1 в представлении записанного в регистр 6 кода произведения в позиционной системе счисления. Сумматор 10 осуществляет суммирование чисел, поступающих на его входы, и эта сумма в двоичном параллельном коде оказывается на его выходах. При этом на первые входы схемы 12 сравнения воздействует код модуля pj, а на вторые входы - код вычисленной суммы с выхода сумматора 10. К этому моменту времени на выходе элемента 14 задержки появляется импульс, который, поступая на управляющий вход схемы 12 сравнения, разрешает сравнение кодов чисел, воздействующих на ее входы. Если в результате сравнения оказывается, что код числа, воздействующий на первые входы схемы сравнения, меньше кода модуля, то на выходе "меньше" схемы 12 сравнения появляется импульс, который поступает на первый управляющий вход мультиплексора 2 и через элемент ИЛИ 3 на вход разрешения записи регистра 7. В результате мультиплексор 2 коммутирует на выходы свои первые входы и в регистр 7 при этом записывается с выходов сумматора 10 код остатка, а на выходе 21 разрешения считывания устройства появляется импульс, свидетельствующий о том, что разрешено считывание очередного элемента поля с выходов 20, а также (на чертеже не показано) на вход 17 запуска (после считывания) блока 1 умножения, где по этому импульсу в регистр множимого записывается код числа с выходов регистра 7 и блок 1 начинает умножать первообразный элемент на это число.Block 9 keys is a group of k l-input keys. Depending on which of the control inputs of the keys receives a logical "1", that of the keys of block 9 is open and commutates the input signals to its outputs. As a result, the corresponding inputs of the adder 10 receive the remainder of the numbers 2 ⁱ , i =

, for those i for which the coefficient a _i = 1 in the representation of the product code written in register 6 in the positional number system. The adder 10 sums the numbers arriving at its inputs, and this sum in binary parallel code is at its outputs. In this case, the module pj code acts on the first inputs of the comparison circuit 12, and the calculated sum code from the output of the adder 10 acts on the second inputs. At this point in time, a pulse appears at the output of the delay element 14, which, upon entering the control input of the comparison circuit 12, allows comparison codes of numbers affecting its inputs. If, as a result of the comparison, it turns out that the code of the number acting on the first inputs of the comparison circuit is less than the module code, then the output is “less” of the comparison circuit 12 and an impulse appears, which arrives at the first control input of the multiplexer 2 and through the OR element 3 to the write enable input register 7. As a result, the multiplexer 2 switches its first inputs to the outputs and in register 7, the remainder code is written from the outputs of the adder 10, and an impulse appears at the output 21 of the read permission of the device, indicating that the resolution but the reading of the next element of the field from the outputs 20, and also (not shown in the drawing) to the input 17 of the start (after reading) of the multiplication unit 1, where, according to this pulse, the code of the number from the outputs of the register 7 is written into the register of multiplicand and block 1 starts to multiply the primitive on that number.

If the pulse appears at the output of "more" of the comparison circuit 12, then this indicates that the formation of the remainder is not completed. The pulse from the output "more" of the comparison circuit 12 is supplied to the control input of the comparison circuit 13, allowing comparison of the codes of numbers acting on its inputs. At the same time, the module code p _j acts on its second inputs, and the code of the number from the output of the subtractor 11, numerically equal to the difference of the product code from the output of the adder 10 and the module code, acts on the first inputs. If, as a result of the operation of the comparison circuit 13, the pulse appears at the output “less”, then this indicates that the formation of the residue is completed. This pulse through the OR element 4 is fed to the second control input of the multiplexer 2 and through the OR element 3 to the input enable the register 7. As a result, the outputs of the multiplexer 2 are switched with its second inputs and the number code from the outputs of the subtractor 11 is written to the register 7. at the output 21, a signal appears indicating that it is allowed to read the next element of the field from the outputs 20.

 If the pulse appears at the output "more" of the comparison circuit 13, then this indicates that the formation of the remainder is not yet completed. This pulse enters through the element OR 4 to the second control input of the multiplexer 2, switching its outputs with its second inputs, as well as to the second input of the element OR 5. In this case, the operation of the device is repeated, but in the register 6 is written the code of the number from the outputs of the subtractor 11, acting to the information inputs of the register 6 through the multiplexer 2. The process of forming the remainder modulo of the number continues until at the outputs of the adder 10 or subtractor 11 there is a number less than the module. In this case, the device gives the code of the field element to the outputs 20, and to the output 21, a read permission pulse of this element. (56) Copyright certificate of the USSR N 1633495, cl. H 03 M 7/18, 1989.

 USSR author's certificate N 1236497, cl. G 06 F 15/20, 1984.

Claims (1)

 DEVICE FOR FORMING ELEMENTS OF MULTIPLICATIVE GROUPS OF GALOIS FIELDS GF (P), containing a multiplication unit, first, second and third elements OR, a first register, adder and delay element, the input of the value of the antiderivative element of the device connected to the input of the register of the multiplier of the multiplication unit, the installation input to "0" of which is connected to the installation input of the device, the input of the unit value record is connected to the least significant bit of the register of the multiplicable multiplication block, and the output of the device is connected to the register input of the multiplicable block intelligently A method, characterized in that, in order to increase the speed of the device, a multiplexer, a second register, a memory block, a key block, a first and second comparison circuit and a subtractor are introduced into it, and the device start input is connected to the multiplication resolution input of the multiplication block, the outputs of which are connected with the inputs of the first group of the multiplexer, the outputs of which are connected respectively to the information inputs of the first and second registers, the output of the second register is connected to the output of the device, the task input of the module of which is connected respectively With the address inputs of the memory block, the inputs of the first group of the subtractor and the inputs of the first groups of the first and second comparison circuits, the outputs of the memory block are connected to the inputs of the first group of the key block, the inputs of the second group of which are connected to the outputs of the first register, the outputs of the key block are connected to the information inputs of the adder the outputs of which are connected respectively to the inputs of the second groups of the first comparison circuit, the subtractor and the multiplexer, the inputs of the third group of which are connected respectively to the inputs of the second group of the second circuit we are comparing it with subtractor outputs, the output “More” of the first comparison circuit is connected to the control input of the second comparison circuit, the output “Less” of which is connected to the first inputs of the first and second OR elements, the output of the end of the multiplication of the multiplication block is connected to the first input of the third OR element, the second the input of which is connected to the second input of the second OR element and the output “More” of the second comparison circuit, the output “Less” of the first comparison circuit is connected to the first control input of the multiplexer and the second input of the first OR element, output which is connected to the write enable permission input of the second register and is the read permission output of the device, the output of the second OR element is connected to the second control input of the multiplexer, the output of the third OR element is connected to the control input of the memory block, the write enable input of the first register and the input of the delay element, the output of which connected to the control input of the first comparison circuit.