RU2024925C1 - Device for convolution by arbitrary modulus - Google Patents

Abstract

FIELD: computing equipment. SUBSTANCE: to convolute by arbitrary modulus P, constants are formed under the following law: A_k-const 1, ..., A_k-const n, and then remainders of the numbers are determined A_k. If the value of any remainder is equal to zero, then the number A_k-const i is divided by modulus P evenly and remainder is equal to zero. If the value of remainder is not equal to zero, then the least positive remainder, value of which falls within the limits 1≅ a $\genfrac{}{}{0ex}{}{\text{1}}{\text{k}}$ ≅ 2P-1 is selected among all remainders A_k-const(i)-const1, ..., (A_к-const i)-const n. New remainders a_к are formed from the above least remainder and from them the value, which falls within the limits 1≅ a_к≅ P-1 is selected. EFFECT: decreased time of convolution by introduction of extra comparator, NOR gate, NOT gate. 1 dwg

Description

 The invention relates to computer technology and can be used in digital computing devices.

 The aim of the invention is to reduce the time of convolution.

A_max/2P

, а число констант, необходимых для нормального функционирования, определяется выражением n = n₁ + 1. Константы формируются по следующему закону
const1 = P; const2 = 2P; const3 = 4P;...; const i = (i-1) ˙2P;...; const n = n₁ 2P (1)
Вычитатели формирует остатки чисел A_k - const1; A_k - const 2... A_k- constn. Если величина любого остатка равна нулю, то число A_k делится на модуль Р нацело и остаток равен нулю. Если величина остатка не равна нулю, то из всех остатков A_k - const i выбирают меньший, значение которого лежит в пределах 1≅ a_k ≅ 2P-1,
и уже от него формируют новые остатки (A_k - consti) - const1; (A_k - consti) - const2;...; (A_k - consti - constn, из которых выбирают значение a_k, которое лежит в пределах 1 ≅ ≅ a_k ≅ P-1.The essence of the invention lies in the fact that the number of elements that make up the device is determined by the expression n =

A _max / 2P

, and the number of constants necessary for normal functioning is determined by the expression n = n ₁ + 1. Constants are formed according to the following law
const1 = P; const2 = 2P; const3 = 4P; ...; const i = (i-1) ˙2P; ...; const n = n ₁ 2P (1)
Subtractors form the remainder of the numbers A _k - const1; A _k - const 2 ... A _k - constn. If the value of any remainder is zero, then the number A _k is divisible by the module P completely and the remainder is zero. If the remainder is not equal to zero, then of all the residues A _k - const i choose the smaller one, the value of which lies within 1 лежит a _k ≅ 2P-1,
and already new residues are formed from it (A _k - consti) - const1; (A _k - consti) - const2; ...; (A _k - consti - constn, from which a _k, which lies in the range 1 ≅ ≅ a _k ≅ P-1, is selected.

 The invention is realized through the introduction of a new set of design features that determine its compliance with the criterion of "Novelty."

 The introduction of the OR-NOT element provides the determination of the moments at which the first register is reset to zero, and the issuance of control signals to lock the "prohibition" element.

 The introduction of the element "prohibition" ensures the exclusion of a signal on the end of the process of forming the remainder in the event that there is no information in the first register.

The introduction of an additional comparison block ensures that a _k , 0 ≅ a _k ≅ P-1 is found and written to the output register.

 Salient features of the present invention is the introduced element OR-NOT, the element "prohibition" and an additional comparison unit, providing a reduction in convolution time and expanding the functionality of the device.

 These signs are significant, because, firstly, the listed elements and the corresponding connections are absent in the prototype, and, secondly, this gives the device the following new technical property - a new convolution principle, which reduces the time of forming a residue and expands the functionality of the device .

 The drawing shows a functional diagram of a device for convolution by an arbitrary module.

 The device contains the first 1 and second 2 registers, a group of subtractors 3, a group of comparison units 4, a group of I5 elements, a group of switches 6, an additional switch 7, the first 8 and second 9 OR elements, a delay element 10, an additional comparison unit 11, an OR- NOT 12 and prohibition element 13.

 The device operates as follows.

In the initial state to the inputs of task constants device in accordance with (1) takes the values of constants, which are applied to first inputs of subtractors group 3. Significance const1 = P _i is also fed to the second inputs of the comparison group 4 and the second inputs of the additional comparator units 11. Registers 1 and 2 are zeroed, therefore, at the combined inputs of the group of subtractors 3, the information inputs of register 2, the inputs of the OR-NOT 12 element and the first inputs of the additional comparison unit 11, there is no information, at the outputs of the subtractors 3 are present in inverse to These are the values of the constants (O - consti = - consti), therefore, at the outputs of the comparison blocks 4 there are signals (-consti <P) that do not pass to the output of any of the elements AND of the group, therefore, the switches of group 6 are open, the output is less "an additional block of comparison 11, the signal to the output of the device is not received, since the element" prohibition "13 is closed by the signal from the output of the element OR NOT 12, since register 1 is reset.

The binary code of the number A _k , from which it is necessary to form a remainder for a given module P _i , is fed to the information input of the device. At the same time, a control signal is received at the device startup output, which opens the additional switch 7 and, through the OR 8 and delay 10 elements, acts on the recording input of the first register 1, the information inputs of which from the output of the additional switch 7 receive the code number A _k , as a result of which the code of the last is recorded in register 1. The code of the number from the output of register 1 is supplied to the inputs of the second operands of the group of subtractors 3, to the first inputs of the comparison unit 11, the inputs of the OR-NOT 12 element, and to the information inputs of the second register 2 As a result, difference codes A _k - const1, A _k - const2, ... A _k - constn are formed at the outputs of the subtractors, and a logical zero signal appears at the output of the OR-NOT 12 element, which opens the "inhibit" element 13. There, where the difference codes are less than the values of the constants, at the output “less” of the comparison units 4, control signals appear, and where these difference codes are more than the values of the constants, the control signals appear at the outputs “more”. Since the values of the constants are calculated by formulas (1), the difference code can either be zero or fall into the gap between adjacent constants. If the difference code is equal to zero, then the signal from the output of the corresponding comparison unit 4 groups through the elements "prohibition" 13 and OR 9 goes to the output of the device, signaling that the remainder r = AkmodP _i = 0 is formed on its information output, and also sets register 1 to zero. In this case, the element "prohibition" 13 is locked by the signal coming from the output of the element OR NOT 12.

If the difference code is not equal to zero, then in the interval between adjacent constants the comparison block 4 _{j + 1} will give a signal “more”, and the comparison block 4 _{j + 1} will give a signal “less”, therefore, the element And 5 _{j + 1} will work, the signal from the output of which the switch 6 _{j + 1} will turn _on , and through the OR element 8 and delay 10 it will ensure that the code A _k - constj is written to register 1. Since the recorded difference value lies in the range from 1 to 2P _i-1 , then if the result is greater than the value module, the signals appear on the output "more" of the comparison unit 11 and the output is "less" of the first comparison unit 4, element And 5 opens and the code A _k - constj - const1 = a _k is written to register 1. Therefore, the signal appears at the output "less" of the comparison unit 11. This signal, through the element "ban" 13, will be sent to the input of register 2, providing writing the remainder code from the output of register 1 to register 2, and, arriving at the control output of the device through the OR element 9, signals the end of the process of forming the remainder, and also zeroes the contents of register 1, thereby locking the element "ban" 13. If A _k - constj = a _k <P _i , then writing the remainder to register 2 occurs em after the first subtraction cycle. The remainder code remains on the information outputs of the device until the next number A _{k + 1} arrives at the information inputs, from which it is necessary to form a remainder, and a trigger signal to the control input. In this case, the operation of the device is carried out similarly to that described above.

Claims (1)

Arbitrary convolution device containing a group of subtractors, a group of comparison blocks, a group of AND elements, a group of switches, first and second registers, the first and second OR elements, an additional switch and a delay element, the inputs of the first operand of the group subtractors being connected to the corresponding inputs of the job device subtraction constants, the information input of the device through an additional switch is connected to the information input of the first register, the information output of which is connected to the inputs of of the next operand of the group subtracters, the outputs of the result of the group subtractors are connected to the first information inputs of the corresponding group comparison units and to the information inputs of the corresponding group switches, the information outputs of which are combined according to the INSTALL OR circuit and connected to the information input of the first register, the output is “Less” of each i-th group comparison unit is connected to the first input of the i-th element of the group
1 ≅ i ≅ n,
where n =

A _max / 2P

+ 1;
A _max is the largest controlled number;
P is the value of the convolution modulus;

- the integer part of number,
the output of which is connected to the control input of the i-th switch of the group and to the i-th input of the first OR element, the output of which through the delay element is connected to the write input of the first register, the output "More" of each i-th block of the group comparison, except for the last, is connected with the second input of the (i + 1) th AND element of the group, the outputs of the “Equally” group comparing units are connected to the inputs of the second OR element, the output of which is connected to the zero input of the first OR element, the output of which is connected to the zero input of the first register and is the end output For the operation of the device, the input of the beginning of the calculation of the device is connected to the control input of the additional switch, the (n + 1) -th input of the first OR element and the input of resetting the second register, the output of which is the output of the convolution of the device, characterized in that, in order to reduce the convolution time , an OR element is entered into the device - NOT, a PROHIBIT element and an additional comparison unit, the first information input of which is connected to the information input of the second register and with the information output of the first register, the second inform The input input of the additional comparison unit is combined with the second information inputs of the group comparison units and connected to the input of the device constant setting, the outputs “Equal” and “More” of the additional comparison unit are connected respectively to the (n + 1) -th input of the second OR element and the second input of the first element AND groups, the output “Less” of the additional comparison unit is connected to the first input of the FORBID element, the output of which is connected to the input of the second register and the (n + 2) -th input of the second OR element, the second input of the FORBID element ene yield element or - whose input is connected to the output of the first register.

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