SU1008732A1 - Multiplication device - Google Patents

Abstract

A DEVICE FOR MULTIPLICATION, containing two shift registers, the element And, the counter and the synchronization unit, the outputs of the shift registers are connected to the inputs of the element And whose output is connected to the counting input of the counter, the first output of the synchronization block is connected to the shift control inputs of the first and second shift registers, the information inputs of the shift registers are connected to their outputs, respectively, the second code of the synchronization unit is connected to the control input i by shifting the counter, characterized in that, in order to expand the functionality by accumulating the sum of paired products, the output of the low-order counter is connected to §. the input of the higher bit of the counter. (ABOUT

Description

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to technology and can be used in digital computing devices to multiply binary numbers. A device for multiplying is known, which contains three registers, an adder, a rounding block, a sign block, a control block, triggers, and logic elements 1. The disadvantage of this multiplication device is the difficulty of implementation. It is also known a device for smart tuning, containing a shift register, two counter-registers, and a pulse generator. triggers and elements AND 2. The disadvantages of the known device due to the low speed and complexity of implementation. Closest to the proposed technical essence is the arrangement

A multiplication unit containing two shift registers, an element, a counter and a synchronization unit, the outputs of the shift registers are connected to the inputs of an element whose output is connected to the counting input of the counter, the first output of the synchronization unit is connected to the shift control inputs of the first and second shift registers, the information inputs of the shift registers are connected to their outputs, respectively, the second output of the synchronization unit is connected to the shift control input of the counter H. However, this device for the mind is characterized by This functionality does not allow to form the sum of the pairwise products. The purpose of the invention is to expand the functionality of the device by accumulating the sum of paired products. The goal is achieved by the fact that in a multiplying device containing two shift registers, an element, a counter and a synchronization unit, the outputs of the shift registers are connected to the inputs of an element And whose output is connected to the counting input of the counter, the first output of the synchronization unit is connected to the shift control inputs of the first and second shift registers; the information inputs of the shift registers are connected to their outputs, respectively; the second output of the synchronization unit is connected to the shift control input; azr yes counter

in the following way.

Shift register 1 contains 2p bits. Counter 3 has 2 c bits. The lower c bits of shift register 1 contain zero codes, and at t1 the highest bits of shift register 1, the binary code of the first factor is located so that the lower bit of the counters factor. The drawing shows a block diagram of a multiplier. The multiplying device contains two shift registers 1 and 2, a counter 3, an AND 4 element and a synchronization unit 5. The outputs of the shift registers 1 and 2 are connected to the inputs of the element 4, the output of which is connected to the counting input of the counter 3. The first output of the synchronization unit 5 is connected to the shift control inputs of the registers 1 and 2. The information inputs of shift registers 1 and 2 are connected to their outputs, respectively. The second output of synchronization unit 5 is connected to the input of the shift control of counter 3. The output of the lower digit of counter 3 is connected to the input of the higher bit of counter 3. The multiplying device works false at 2 Pth digit of shift register 1, and the most significant fn is and of The factor is located in the (2P-m) th digit of the shift register 1, and m determines the range of representation of the factors OiX. 2, m n. In the lower and lower bits of shift register 2, the binary code of the second factor is written, which in the first digit of the shift register 2 contains the lower bit of the second factor, the m and bit of which is located in the m th digit of the shift register 2. The initial state of the counter is zero. The synchronization unit 5 generates at the first output a sequence of clock pulses of frequency i, which} arriving at the shift control inputs of shift registers 1 and 2, shifts the binary codes from the output of registers 1 and 2 to the inputs of element 4. The synchronization unit 5 also generates the second output pulses of frequency i / 2 n - t, the period of which determines the duration of one cyclical computation, equal to 2 n -1 cycles. Since shift register 2 contains one bit less than register 1, each cycle of computations temporarily shifts the binary code of the factor of register 2 to the binary code of register 1. In the first cycle of computation, the output of the And 4 element is the signal of the lower bit of the product, which is recorded in the lower bit of counter 3. After the end of the first computation cycle, the signal of the second output of the synchronization unit 5 is input to the counter shift control input 3- and shifts the code of the lower bit Yes counter 3 in its most significant bit In the second and all subsequent calculation cycles, the multiplier works in a similar way. At the same time, in the second cycle of calculations, at the inputs of the AND 4 element, the codes of the first and second bits of the shift register 1 shift coincide with the second and the first bits of register factor 2, respectively, in the third cycle, the first and second bits of the register 1 match the shift with the third, second and first bits of the register factor 2, respectively, and so on. At the output of the element AND 4, in each i-th calculation cycle, a sequence of single product signals is generated, the weight of which corresponds to the product discharge, coinciding with this lower-order calculation cycle with the lower bit of counter 3. Counter 3 accumulates a sequence of single signals acting on Registers 1 and 2

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At the end of the computation cycle, the i and the bit of the product, which is shifted from the low bit of counter 3 to its high bit, by the signal of the second output of the block 5, is formed at the end of the computation cycle. Dov binary code product of two numbers. In the course of further calculations, the multiplier generates in the estimator 3 the sum of the pair products 1,. 51 X: X p where K is the number of cycles. } - multiply. After the first multiplication cycle, the state of the counter 3 will be determined by the binary code of the product of two numbers 2. . 51 H; -Hp; which in the second cycle of G J multiplication is added again the product of two numbers .E. Xjj etc The per bits 1 and 2 of the shift and the counter 3, determined through the parameter || 1, must be selected from the representation range of the factors 0 X 2 and the presentation range of the result, so that the condition is met: where; Example. Formation of the sum of two products Z.. where 30111, aX IT.

Bill counter

Technical and economic advantages of the proposed device in comparison with the known one are in expansion

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functionality by accumulating the sum of paired products &

Claims (1)

A device for multiplication, comprising two shift registers, an AND element, a counter and a synchronization unit, the outputs of the shift registers being connected to the inputs of an And element, the output of which is connected to the counter input of the counter, the first output of the synchronization unit is connected to the inputs of the shift control of the first and second shift registers , the information inputs of the shift registers are connected with their outputs, respectively, the second output of the synchronization unit is connected to the control input • counter shift, characterized in that, in order to expand the functional possibilities by accumulating the sum of paired products, the output of the lowest level of the counter is connected to the input of the highest level of the counter.