SU1746372A1 - Discrete function system generator - Google Patents

Abstract

The invention relates to automation and computing and can be used for spectral analysis of signals when they are decomposed into systems of functions. The purpose of the invention is to expand the functionality of the generator by forming 2M (N / P ™ + - / systems of discrete basis functions, where M is the number of values accepted by the functions; N 2n is the dimension of the system of functions. The generator contains switches 1-3, node 4 sign detection, counter 5, switch 6,

Description

The invention relates to automation and computing and can be used for spectral analysis of signals when they are decomposed into systems of functions.

The purpose of the invention is to expand the functionality of the generator for

n .. + N / 4 + ...- Hi

formation account 2M (t}

systems of discrete basis functions, where M is the number of values accepted by the functions; N 2n-dimensionality of the system of functions.

The drawing shows the functional diagram of the generator (N 8).

The generator contains switches 1-3, node 4 of the sign definition, counter 5, switch 6, counter 7, adder 8 modulo M / 2. shaper 9 time intervals

catcher, 10 clock pulse selector, shift registers 11 and 12, blocks 13 and 14 elements I, inputs 15-18 of the function system, input 19 clock pulses, output 20 functions, output 21 for the end of function period, function number 22, blocks 29 and 30 elements OR.

The generator forms the class 2MN / 2 (HN / 24 + Y systems of discrete basis functions that accept M values.

The generator implements a method of forming systems of discrete basis functions by specifying the matrix G (2n) of the discrete transformation in the form of Kronecker; in the product of factors. In accordance with this method, the matrix G (8) is defined as follows.

AC

w-w

I -W: W

 -,

a "r 1 Y" M

i w

where W - e, M

accepted by ei function

2 - number of values, 2

M

Bottom of the interval (0.2 tg), D OM / 2-1, k is an arbitrary integer.

The operation of multiplying the matrix factors in (1) follows the Crocker product rule, the product of the degrees and the formation of the values of the basis functions in the generator is performed according to the rule:

)) mOClM 2

AC

-w

: W

 -,)

"G

a "r 1 Y" M

D | UЈ

where si and S2 are the signs of the degrees W, W:

). if the sign of the degree W is positive; 1 if the sign of the degree W is negative.

p-transfer formed during the operation of the addition of the exponents of

Oh, if the selection of the whole M / 2 occurred an even number of times,

1, if the selection of the integer M / 2 occurred an odd number of times.

Thus, in accordance with (1), for selected M.K., N, by iteration, to form MN / 2 (+ N / 4 + - + J systems of complex functions (or class 2MN / 2 (MN / 2 + N (+ +) systems of real basic functions), specifying N / 2 -x generating matrices G2 as multipliers of the first iteration and

L (L Ј N / 2. I 2, p) of the coefficients in i

as factors of the i-th iteration.

The generator works as follows.

The elements of the generators of matrices G (2) and iterative factors A serve: the first elements of each first row of matrices G (2), respectively, to a group of 18 inputs of a system of functions; the second elements of each first row of matrices G (2) respectively to a group of 15 inputs of a task of a system of functions : elements of the multipliers of the second iteration, respectively, on a group of 16 inputs of the task of the system of functions; multiplier of the third iteration per group of 17 inputs of the task of the system of functions. The elements of the second row of matrix multipliers and their unit elements are automatically generated by the generator in accordance with (1). Counter 5 counts the clock pulses arriving at its input and forms the period of the function T N g, where t is the period of the clock pulses.

The overflow pulses of the counter 5 synchronize the operation of the generator according to the following algorithm.

The front of the overflow pulse adds +1 to counter 7: the switch 6 is readable for the duration of the overflow pulse, the information is received in the shift register 11, the sign definition unit 4 is inhibited.

The values of the basis functions in accordance with (2) form the adder 8 modulo M / 2, the first input of which receives the values of the first elements of the generator matrices, from the output of the switch 6 or the values of the functions formed in previous iterations, from the outputs of blocks 13 and 14. The second input of the adder 8 modulo M / 2 receives the values of the second elements of the generator matrices from the output of switch 1 or the iteration factors from the outputs of switches 2 and 3.

The incoming clock edge generated values of the basis functions are written to the shift register 12 and output to the generator function output 20.

Claims (1)

Invention Formula The generator of systems of discrete functions containing two counters, two registers shift, n - 1 blocks of elements And (2P N is the size of the system of functions, modulo M / 2 adder (M is the number of function values), the counting input of the first counter is the clock input of the generator, the overflow output of the first counter is the end of period output function of the generator and connected to the counting input of the second counter, the output of the second counter is the output of the number of the generator function, characterized in that, in order to expand the functionality of the generator by forming 2MN / 2 (MN / 2 + / 4 + - + H systems of basic functions he soda laughs n + 1 switches, clock selector, time interval generator, logical computing node, two blocks of OR elements, 2P (Mp) of the information inputs of the i-ro switch are the i-th group of inputs for setting the functions of the generator, IM The (2) information inputs of the (n + 1) switch are the (n + 1) -th group of inputs of the generator function set system, the i and address switch K-ro of the switch (ki 1, n - k); 1, n - one; connected to the (k +) -th bit output of the second counter, k-th address input of the (n + 1) -th switch connected to the (k + 1) -th bit output of the second counter, output of the i-ro switch connected to i input of the first block of OR elements, information and symbolic. The outputs of the first block of OR elements are connected respectively to the input of the first operand of the modulo M / 2 adder and the first information input of the logical computing node, the output of which is connected to the sign input of the first operand of the modulo adder M / 2, the output of the adder modulo M / 2 connection n with a serial information input of the first shift register, the first bit output of the first shift register is the output of the generator functions, the bit output of the first shift register is connected to the information input of the k-ro element block, the output of which is connected to the kth input of the second block of elements OR, the output (n + 1) of the switch is connected to the n-input of the second block of elements OR, the output of the second block of elements of the ILU is connected to the input of the second operand of the modulo M / 2 adder, the information output of the first counter is connected to the inputs clock selector and time interval generator and 1st and (k + 1) -th time interval generator outputs are connected respectively to the read input of the i-ro switch and the control input of the k-ro block I, the output of the second counter connect 17463728 It has a parallel information input of the generator, a synchronization input of the second shift register, a shift sequence of the second shift register, a connecting information input which is identical with the output of the clock selector connected to the source of the zero level re-pulses, the output of the overflow of the first nerator, the n-th bit output of the second re-5 counter is connected to the synchronization input the shift horn is connected to the second record of the second shift register, the input by the information input of the logical (n + 1) switch and the input of the prohibition calculating the sign, synchronization input of the logical node calculating the sign, shifting the first register is connected to the clock