SU1115060A1 - Device for implementing fast transforms in digital orthogonal function bases - Google Patents

Abstract

The DEVICE FOR IMPLEMENTING FAST TRANSFORMATIONS IN THE BASIS OF DISCRETE OUR ALCO-FUNCTIONS, containing an arithmetic unit, an operative and permanent memory blocks, a group of switches, an iteration register, and an operand counter, and an information block of an active face, a group of switches, an area, and a face to you, and you will also have a simple way to get into your application. an arithmetic unit, the information output of which is connected to the information input of the random access memory block, the address input of which is connected to the output of the switches uppa, the parallel output of the register of iterations is connected respectively to the control inputs of the switches of the group, the information inputs of the switches of the group, except for the output of the second bit, to the parallel output of the operand counter, the output of the second discharge of which is connected to the control input of the write-read memory block, t.ch. to expand the functionality of the device by calculating the conversion factors in the basis of Fourier, Walsh, and Haar functions and complex rectangular functions, a switch, an iteration counter, a group of elements And, a shift register and a driver of control signals, with the parallel output of the operand counter, the outputs of the first and second bits are connected to the information inputs of the switch and the shift register, the switch output is connected to (L clock input of the iteration register with and counting in One iteration counter, the parallel output of which is connected one at a time to the first inputs of the corresponding PSU elements of the group and the control input of the shift register, the outputs of the AND group elements are connected respectively to the bits of the control input of the switch, the parallel parallel output of the shift register is connected, except for the senior d, Od to the address; the input of the block of permanent memory, the second inputs of the elements AND groups are combined and are the first input of the device mode setting, and the driver of the control signals contains ent STI-NO, first and second AND-NO elements, first, second, third and fourth AND gates, a clock generator, a counter and pulse generator, wherein first inputs of first AND gates, and NOR and inverted input vto

Description

the primary element of the NAND is connected to the higher bit of the parallel output of the shift register, the output of the element ILINE is connected to the second inputs of the first and second elements of the NAND and to the inverse of the fourth element AND whose output is connected to the control input of the forcing device and the pulses, the first output which is connected to the second inputs of the second and third elements And, the first inputs of which are connected to the outputs of the first and second elements AND, respectively, the output of the clock generator is connected to the counting input of the counter, parallel to the th output of which is connected to the address input of the pulse former, the third inputs of the first element

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The NAND and the third element AND and the second input of the first element AND are connected to the shift control input of the iteration register and are the second input of the device mode setting, the direct input of the fourth AND element is the third input of the device mode setting, the counter overflow output is connected to the counting input the operand counter, the second and third outputs of the pulse former and the outputs of the first, second, third and fourth elements of AND are connected to the synchronization input of the arithmetic unit, the input of the OR element is connected to the parallel input Odom excluding significant bit, the shift register.

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The invention relates to digital computing and can be used in solving problems of filtering and identifying signals.

A device for computing generalized discrete functions is known, comprising an address generation unit, a main and additional memory blocks, an arithmetic unit, a switch, a slide line, an address counter, and a generalized discrete function calculation unit, the address generation unit contains the modulo counter P, a trigger, the modulo-DB counter is the unit multiplying by the module P, the module's schematic diagram, two adders, the microstep counter, the modulo-I counter and the module for calculating the module S SP.

The disadvantages of this device are the large hardware costs and limited functionality, which in calculating only the Fourier-Walsh transform coefficients and the discrete Fourier transform coefficients.

The closest in technical essence to the present invention is a device for realizing a fast Fourier transform containing an arithmetic random access memory.

block, fixed memory and control unit, the first and second outputs of which are connected to the address inputs, respectively, of the operational and fixed memory, the outputs of which are connected respectively to the inputs of operands and coefficients of the arithmetic unit, the third output of the control unit is connected to the synchronization input an arithmetic unit whose output is connected to an information block of a random-access memory block, the control block containing an operand counter, a storage register, and an L21 code inversion circuit.

A disadvantage of the known device is the limited functionality of calculating only the Fourier transform coefficients of the sequence of input samples.

The aim of the invention is to enhance the functionality of the device by calculating the transform coefficients in the basis of Fourier, Haar, Walsh functions and complex rectangular functions.

The goal is achieved by the fact that the device containing the arithmetic unit, the operational and fixed memory blocks, the switch group, the iteration register and the count of operands, the information outputs of the operative and world memory blocks are connected respectively to the operand inputs and the arithmetic unit, whose information output is connected to the information input of the RAM, whose address input is connected to the outputs of the switch group, the parallel output of the register of iterations In accordance with the control inputs of the group switches, the information inputs of the group switches are connected, besides the second bit output, to the parallel output of the operand counter, the second bit output of which is connected to the read memory control input of the operational memory block, and the iteration counter is entered , group-elements I, shift register, driver of control signals, with the parallel output of the operand counter, excluding the inputs of the first and second bits, connected to the information inputs of the com the shift register, the switch output is connected to the clock input of the iteration register and the counting input of the iteration counter, the parallel output of which is connected to the first inputs of the corresponding elements of the AND group and the control input of the shift register, the outputs of the AND elements of the group are respectively connected to bits the control input of the switch, the parallel output of the shift register is connected, excluding the high-order bit, to the address input of the block of permanent memory, the second inputs of the AND-group elements are combined and are the first the input of the device mode setting, the driver of the control signals containing the element OR-H the first and second elements AND-NOT, the first, second, third and fourth elements AND, the clock generator, the counter and the driver of the pulses, the first inputs of the first elements AND, AND -NON and the inverse input of the second element NAND are combined and connected to the higher bit of the parallel output of the shift register, the output of the element OR NONE is connected to the second inputs of the first and second element AND NAND and to the inverted input of the fourth element AND, output to o60 cerned is connected to the control input of the pulse shaper, which first output is connected to second inputs of the second and. The third elements AND, the first inputs of which are connected to the outputs of the first and second elements NAND, respectively, the output of the clock generator connected to the counting input of the counter, the parallel output of which is connected to the address input of the pulse shaper, the third inputs of the first element NAND and the third element And and. the second input of the first element And connected to the shift control input of the register of iterations and is the second input of the device mode setting, the direct input of the fourth element And is the third input of the device mode setting, the counter overflow output is connected to the counter input of the operand counter, the second and third ram generator outputs pulses and outputs of the first, second, third and fourth elements of AND are connected to the synchronization input of the arithmetic unit, the input of the OR element is connected to the parallel output, excluding the senior sp d, shift register. FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a block diagram of a control signal generator. The device contains operational 1 and constant 2 memory blocks, an arithmetic unit 3, a group of switches 4, a register of 5 iterations, a counter of 6 operands, a switch 7, a counter of 8 iterations, a group of elements AND 9, a shift register 10 and a driver 11 of control signals. The driver of the control signals contains the element OR NOT 12, the first 13 and second 14 elements are NOT the first 15, the second 16, the third 17 and the fourth 18 elements AND, the generator 19 clock pulses, the counter 20, the driver 21 pulses. The arithmetic unit (AB) 3 is made similarly well-known, it is intended to perform an elementary A + B type transformation "W" and contains four adders, four result storage registers, two switches, two input real and imaginary parts storage registers, a sine register and a cosine register for input the values of the exponential coefficient W, the low bits of which through the valves are connected to the control inputs of the first, fourth and second, third adders, respectively, and the control inputs (the ventilation inputs The count of 6 operands, the register of 5 iterations, the group of switches A contain respectively Y + 1, and 1 bits and n switches 3t1 (n, N is the volume of the sequence of input samples), and the output of the first bit of the counter 6 operands is connected to the second inputs of the switch group 4, the output of the (J + 1) -th bit, starting from the third bit — to the first input of the j-ro switch, the output (i. + 2) of the bit — to the third input of the j-rp switch and the output of the third bit of the counter of 6 operands is connected to the third input of the first switch. The first control input of the j-ro switch is connected to the output (j-1) -ro of the register of 5 iterations, the second control input to the output of the j-ro discharge, with the first control input of the first switch and the second control input 10 switch of the nd switch are connected respectively to the logical potentials 1 and O. The counter 8 iterations and the group of elements And 9 contain K Iog2n bits and elements AND, respectively. The device works the next time. When implementing the fast Fourier transform (FFT) at the inputs XI, X2 X3 of the device, code 110 is set, the sequence of input counts is located in block 1 of the working memory (OP) in binary-inverse key, and the counters of operands 6 and 8 of iterations 8 and register 5 iterations reset to zero. A series of pulses from the second output of the synchronization block 11 nocTjmaet has 6 operands on the counting input, the output binary of the first, third and subsequent bits of the initial binary code is formed, and the output of the second bit has a write-read control signal of the OP block 1. At the control input of the switch 7, a zero code is set (elements AND 9 of the group are closed) and the overflow signal from the high bit output of the counter 6 operands is fed to the count input of the counter 8. iterations and the clock input of the register 5 iterations. At the same time, at the outputs of counter bits 8, iteration 1, the binary code of the number of iterations is formed, and the register of 5 iterations from the side of the low-order bit is entered. with a shift of the previously recorded information towards the higher bits. The signals from the parallel register output 5 iterations, arriving at the control inputs of group 4 switches, convert the source binary code from the parallel, the output of the counter 6 operands to the binary code of the write address and read operands for a specific iteration of the FFT according to the transformation graph with substitution and decimation over time. The binary code from the parallel output of the counter 8 iterations is fed to the control input of the shift register 10, which, depending on the iteration number and the initial read address code. The pair of operands generates the address codes of the sample from the exponential fixed memory block 2 coefficient W. The coefficient W (separate sine and cosine values) enters AB 3, which performs an elementary transformation of the form A + BW, where A and B are complex operands read from block 1 of the OP, represented as the values of their real and imaginary parts. The binary code from the parallel output of the register 10 shift also enters the input of the imaging unit 11 Pack. equalizing signals, namely to the input of the OR-NOT element (Fig. 2), the signal O at the output of which specifies the mode of operation of AB 3 Full complex multiplication. At the outputs of the first 13 and second 14 elements AND-NOT of the fourth 18 element I, a signal 1 appears, a series of write clock pulses in the storage registers of the AB 3 passes from the first output of the driver 21 pulses to the outputs of the second 16 and third 17 And elements and further pus "stumbles on the clock inputs of the record (separately) of the pro7 storage registers

izveneni Re In-cos W; Jm B-sin W and the storage registers of the results of the product Re B "sin W, Jm Bcos W, respectively. From the second output of the imaging unit 21 pulses and clock inputs of the sine and cosine registers AB 3, a series of pulses is received, shifting the information towards the low-order bit, and the signal 1 from the output of the fourth element And 18 allows the information from the low-order bits of the sine and cosine registers to pass through the gates at the first control inputs of adders.

The signal from the third output of the pulse generator 21 controls the switches, and in the multiplication cycle, the outputs of the input registers of the operands are connected to one of the information inputs of the adders and the products ReB-cos W, ReB "sin W, Jm B cos W and Jm B are calculated "Sin W, in the cycle of cross-addition to the same input of the adders through the switches, the results of the output from the outputs of the corresponding storage registers are received, the operations of the form Re B-cos W - Jm B-sin W Re (B" W) and Re B-sin are performed W + Jm B-cos W Jm (), and the results of the summation of Re () and Jm () are entered in the corresponding storage registers for the arrival of a separate write pulse from the first output of the pulse former 21, and in the tact of performing the operation of the type A + BW, the inputs of the adders are connected via switches to the input registers of operands, where the value of countdown A is recorded to the ETO14 and the information outputs of the adders the real and imaginary parts of the value B AB W W, and then the values A A + B are sequentially formed to write to block 1 of the OP 1; The signal from the high-order output of the shift register 10, determined by reference (depending on the logic O or 1) the sign of the information entered into the sine and cosine registers of the AB 3, is fed to the input of the driver 11 of the control signals and through the first element AND is fed to the control inputs of the adders. I

At the time of forming the address code of the exponential value

the effect with the indicators He / 2 at the output of the element OR-E1E 12 appears signal 1, which sets the mode of operation of the LP 3 Multiplication by 5 trivial multiplier. At the same time, at the output of the fourth element And 18, the signal O arrives in AB 3 and blocks the passage of information through the elements AND from the outputs of the lower bits of the sine and cosine registers to the first control inputs of the adders. At the first output of the pulse driver 21, instead of a series of write clock pulses, a single pulse appears that travels to the clock inputs of the record or the registers of the storage of the results Re B-cos WJ, Jm W (at the input X5 of the driver of the control signal O 11) registers of storing results of products Re B sin WJ Jm B sin fl (input X5 is potential 1) i Operands value (5 is valid and imaginary parts separately)

rewritten from input registers via adders to the corresponding storage registers upon the arrival of a given record record and multiplying by a trivial multiplier is completed. Next, a cross-add and A + BV / type operation are performed. which are similar to the mode Full complex multiplication

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when implementing the conversion in the basis of complex rectangular functions (BPPF) at the inputs XI, X2, X3 code 010 is set, the input samples are located in block 1 OP in binary-inverse order, and the formation of address codes when writing and reading the operands of block 1 OP for all iterations, similarly to the FFT. In the basis of the CPP, the sine and -sine sine functions take only integer values -O, +1, -1, and the operation mode of the AB 3 Full comp | Lex multiplication is changed so that in this case the AND elements at the outputs of the lower bits of the sine and cosine registers AB 3 is blocked (at the output of the fourth element And 18 is potential O), and multiplication of the operand B by the value (+1) or (-1) is accomplished by sending the value of the real and imaginary parts of operand B through the adders to the corresponding storage registers ( their clock inputs

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the recordings arrive through the second 16 and third 17 elements of AND single and veltsy with / of the first output of the driver 21 pulses), taking into account the sign of the complex function. Cross-adding and operations of type A + BW with BP CPP are performed in the same way as FFT. In addition, the mode of operation of AB 3 Multiplication by a trivial multiplier remains unchanged.

When implementing the transformation in the Walsh-shaped functions (BAC) basis, the code 000 is set at inputs XI, X2, X. The input information intended for processing is rearranged according to the law, either by binary-bit inversion or by the Gray code, depending on the type Walsh-shaped periodic function. The bits of the register 5 iterations are set to logical state 1, and zero information is written to the register from the high bit as the clock pulse arrives. The generation of address codes for reading and writing operands of block 1 occurs in the same way as a FFT, given that in this case the transformation graph changes, i.e. the last iteration of the FFT is similar to the first iteration of the control room, etc.

AB 3 works only in multiplication mode by a trivial multiplier.

ten

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moreover, the write pulse from the first output of the pulse former 21 passes through the second element I 16 only to the tact input of the record of the record of the storage of the results of the Re Bcos W and Jm Bcos W, then the cross-add Re W - Jm B -s-W W B ; Re B-sin W + Jm B-cos W

10 Jm B-cos W 1 sin W 0 and an operator of the form A +. B.

When implementing the transformation in the basis of the Haar-shaped functions (FFT) at the inputs XI, X2 and X. Set the 15 with the code 001. The location of the input data in block 1 of the joint venture and the operation of AB 3 in the multiplication by a trivial multiplier mode, similar to the control unit. Group of elements And 9 skips binary

20 code from the outputs of counter bits 8. iterations to the control input of the switch 7, whose output to the j-th (J O, ..., p-1) iteration is connected to the output (n-j) -ro of the bit

25 of the operand counter 6, and the codes of the write and read operand addresses are generated for the implementation of the truncated transform graph.

30 The proposed device allows the calculation of transformation coefficients in various bases of discrete orthogonal functions, namely Fourier, Haar, Walsh, and complex rectangular functions.

fi & 1

Fig-g

Claims (1)

A DEVICE FOR IMPLEMENTING QUICK TRANSFORMATIONS IN BASES OF DISCRETE ORTHOHONAL FUNCTIONS, which contains an arithmetic block, random-access memory and read-only memory blocks, a group of switches, an iteration register, and an operand counter, and the information inputs of the random access memory and read-only memory are connected to the input and the output of which is connected to the information input of the RAM block, the address input of which is connected to the outputs of the group switches, a pair The separate output of the iteration register is connected respectively to the control inputs of the group switches, the information inputs of the group switches, in addition to the output of the second category, are connected to the parallel output of the operand counter, the output of the second category of which is connected to the write control input - by reading the RAM block, which is different from . In order to expand the functionality of the device by calculating the conversion coefficients in the basis of the Fourier, Walsh, Haar functions and complex rectangular functions, a switch, an iteration counter, a group of AND elements, a shift register and a shaper of control signals are introduced into it, and the parallel output of the operand counter, excluding the outputs of the first and second bits, connected to the information inputs of the switch and the shift register, the output of the switch is connected to the clock input of the iteration register and the counting input counter and iterations, the parallel output of which is connected bitwise to the first inputs of the corresponding AND elements of the group and the control input of the shift register, the outputs of the elements AND groups are connected respectively to the bits of the control input of the switch, the parallel output of the shift register is connected, excluding the senior bit, to the address input of the read-only memory block, the second inputs of the AND elements of the group are combined and are the first input of setting the device mode, and the driver of the control signals contains an OR-NOT element, the first and second e AND-NOT elements, first, second, third and fourth AND elements, a clock pulse generator, pulse counter and driver, and the first inputs of the first AND, AND-NOT elements and the inverse input of the second AND-NOT element are connected to the high-order bit of the parallel output shift register, the output of the element is connected to the second inputs of the first and second elements AND NOT to the inverse input of the fourth element AND, the output of which is connected to the control input of the pulse shaper, the first output of which is connected to the second inputs of the second and third ele And, the first inputs of which are connected to the outputs of the first and second elements NAND, respectively, the output of the clock generator is connected to the counting input of the counter, the parallel output of which is connected to the address input of the pulse shaper, the third inputs of the first element AND NOT of the third element AND and the second input of the first element AND are connected to the iteration register shift control input and are the second input of the device mode setting, the direct input of the fourth element And is the third input of the device mode setting, the counter overflow output is connected to the counting input of the operand counter, the second and third outputs of the pulse shaper and the outputs of the first, second, third and fourth elements AND are connected to the synchronization input of the arithmetic unit, the input of the OR element is connected to the parallel output ohm, excluding high order, shift register. *