SU1599849A1 - Combination computing data converter - Google Patents

Abstract

The invention relates to computing and can be used in control systems and signal processing devices and random processes. The purpose of the invention is to expand the functionality by providing transformations over the table-defined functions of two arguments. This goal is achieved by the fact that a group of M computational information converters 1, (M-1) groups of four 2-5 blocks of AND elements in each and a synchronization unit 6 are entered into a combined computational information transformer containing a computational information transformer 1. 3 il.

Description

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The invention relates to computing and can be used in control systems and. signal processing devices and random processes. .

The purpose of the invention is to expand the functionality by providing transformations over the table-defined functions of two arguments.

FIG. G depicts the function al-- on the scheme of the combined computational information converter; in fig. 2 and 3 - the functional diagram of the computing information converter.

Combined computational information converter (CWPI) contains computational information converters (VPI) 1, blocks 2-5 of elements I, block 6 of synchronization, information inputs 7-13 of the first stage, analog output 14 of the first stage, digital output 15, inputs 16-19 synchronization of the first stage, inputs 20-22 of the first stage operation modes, groups 23-30 of the second stage information inputs, groups 31-34 of the second stage synchronization inputs, groups of 35-37 inputs of the second stage operation modes, group 38 analog outputs (Second stage fines and input 39 specifying the operating mode of the second stage.

The computational information converter, constructed according to the well-known scheme, contains converters 40-43, code-voltage, matching elements 44, 45, input registers 46-49, nodes JQ 50, 51 of the choice of sign bits, chip-52, 53, adder 54 modulo two, voltage converter 55

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inputs 62, 63, 65 and 66 of each i-ro VPI second stage KVPI. In each i-M second stage VPI, information is processed in accordance with one of the possible operations implemented in the VPI.

1. The operations of adding the first and second, third and fourth functions and multiplying the obtained, function sums, the samples of which are recorded in registers 46, 48, 47 and 49, respectively.

2. The operation of entering information on a sync-call at the moment of time t in the register 46 of the first computing unit i-ro VPI through input 62

with simultaneous transfer (shift) of information from the first register of the 46 (p - 1) -th computing unit (P 1, t) to the first register 46 of the O-th computing unit.

3. Operations of recording information on the clock at time t, respectively, in register 48 or reg. 47, or register 49 of the first computing unit of the i-ro VPI, respectively, through input 65, 63, or 66 with simultaneous transmission of information from register 48 (p - 1) -th computing unit (WB) to the register of 48 D-th WB or from the register of 47 (-1) -th WB to register of 47 O-th WB, or from register 49 ((1.) -Th WB to register 49 p-th WB.

4. The operation of entering information on a clock pulse at time t into register 46 or into register 48, or into register 47, or into register 49 of the first WB, either at input 62, or at input 65, or input 63, or through water 66 and entering information from the digital output 78 on the clock pulse

at time t to register 46 (n + 1) -th WB with simultaneous shift

code coded adder 56,

blocks 57-61, elements I, information-45 information from register 46 or register inputs 62-69, synchronization inputs 70-73, inputs 74-76 of setting operating modes, analog output 77, digital input 78 to outputs 79-82 transmission of information. 50

The interaction of the blocks and the processing of information in the CWPI is carried out as follows. .

Subject to processing digital information in the form of t, is the size of the numbers

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ra 48, or register 47, or register 49 (L-1) of the WB, respectively, in register 46, or in register 48, or register 47, or register of the 49th WB (p. 2., 3, ..., p) and the shift of information from the register of 46 () WB to the register of 46 cf-ro WB (O / p + 2, ... 2p).

Moreover, if the operation of entering information on a clock pulse at the moment of time t is realized through the information inputs 62, either 65 or 63 ,. or 66, depending on. state of entry of operation mode setting 39,

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N2-, N3-,, N4, in parallel arrives at the information inputs 69 and 64 i-ro of the VPI - second stage of the FIR (i 1, that) or sequentially - on

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inputs 62, 63, 65 and 66 of each i-ro VPI second stage KVPI. In each i-M second stage VPI, information is processed in accordance with one of the possible operations implemented in the VPI.

1. The operations of adding the first and second, third and fourth functions and multiplying the obtained, function sums, the samples of which are recorded in registers 46, 48, 47 and 49, respectively.

2. The operation of entering information on a sync-call at the moment of time t in the register 46 of the first computing unit i-ro VPI through input 62

with simultaneous transfer (shift) of information from the first register of the 46 (p - 1) -th computing unit (P 1, t) to the first register 46 of the O-th computing unit.

3. Operations of recording information on the clock at time t, respectively, in register 48 or reg. 47, or register 49 of the first computing unit of the i-ro VPI, respectively, through input 65, 63, or 66 with simultaneous transmission of information from register 48 (p - 1) -th computing unit (WB) to the register of 48 D-th WB or from the register of 47 (-1) -th WB to register of 47 O-th WB, or from register 49 ((1.) -Th WB to register 49 p-th WB.

4. The operation of entering information on a clock pulse at time t into register 46 or into register 48, or into register 47, or into register 49 of the first WB, either at input 62, or at input 65, or input 63, or through water 66 and entering information from the digital output 78 on the clock pulse

at time t to register 46 (n + 1) -th WB with simultaneous shift

information from register 46 or register

ra 48, or register 47, or register 49 (L-1) of the WB, respectively, in register 46, or in register 48, or register 47, or register of the 49th WB (p. 2., 3, ..., p) and the shift of information from the register of 46 () WB to the register of 46 cf-ro WB (O / p + 2, ... 2p).

Moreover, if the operation of entering information on a clock pulse at the moment of time t is realized through the information inputs 62, either 65 or 63 ,. or 66, depending on. state of entry of operation mode setting 39,

by means of blocks of elements I2-, 3; , 4, - and 5, information can be shifted only along the registers of the i-ro VPI (to the second inputs of the blocks of elements I2), 3i, 4; and 5 in this case is filed through the input 39 of the inhibitory potential, and thus the transfer of information from register 46, or register 47, or register 48, or register is prohibited. 49 2 p-th computing unit i-ro VPI to register 46, or pe1; Istr 47, or register 48, or register 49 of the first computing unit (i + 1) -ro VPI), or shift information simultaneously along registers 46, or registers 47, or registers 48, or registers 49 of all VPI of the second stage of the CFRP (the second potential is supplied to the second inputs of the blocks of elements And 2-5 through input 39),

After the time required to perform one of the possible operations, ftt on the digital outputs 78 of each i-ro VPI second stage will establish the digital equivalent of the i-M VPI operation (outputs 78 VPI second stage connection to the information input 69 VPI first stage).

After the time ut has elapsed from the beginning of the second stage VPI operation, at the outputs of synchronization unit 6 appear depending on the first stage operation VPI, the C1C1, UIC2, SHSZ, SHS4 clock pulses, through which information is recorded in the first stage in parallel to the VPI registers according to information inputs 69 and 64.

At the expiration of the time ftt from the beginning of the first stage, the digital equivalence of the operation performed by the HVCI, which enters into code 15 of the HIL code, appears at its output 78.

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the invention

The combined computational information transducer, containing the computational information transducer, the first, second and third inputs of which operation modes are respectively the first, second and third inputs of the specified operation modes of the first stage of the combined computational information converter, from the first to the seventh

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The information inputs of the computational information converter are respectively the first to the seventh information inputs of the first stage of the combined computational information converter; the first through fourth synchronization inputs of the computational converter are the first through fourth synchronization inputs of the combined first stage converter, respectively, the analog and digital outputs of the computational information converter are respectively the analog output of the first steps and digital output of the combined computational information converter, ex. due to the fact that in order to extend the functionality by providing transformations over the table-defined functions of the two arguments, a group of m computational

5 information converters, t-1 groups of four blocks of elements And in each and a synchronization block, with the first to fourth synchronization inputs of the computational information converter being connected to the first to fourth outputs of the synchronization block, respectively, from the first to the fourth inputs from the first to the fourth inputs of synchronization of the first stage of the combined computational information converter; the first inputs from the first to the fourth blocks of the elements of the i-th group (i 1, .. ", m-1) under The keys are connected respectively to the outputs from the first to the fourth information transfer busses i-ro of the computational information converter group, the outputs of the first, second, third and fourth blocks of elements of the i-th group are connected respectively to the first, second, third and fourth information inputs (i + 1 ) -ro computing group information converter, digital outputs of computing group information converters are connected to the corresponding code buses. Computing information converter of the first stage, but marketing computing converters outputs data groups form a group of the analog outputs of the second stage combined computing transducer

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Information from the first to the fourth synchronization inputs of the computational information converters of the group form respectively the first to the fourth groups of synchronization inputs of the second stage of the combined computational information converter; the first, second and third, in the course of setting the operation modes of the computational information converters, form the first, second and third groups the inputs of the job modes of the second stage of the combined compute-Fi .1

From the first to the eighth information inputs of the computing information converters, the groups form, respectively, from the first to the eighth group of information inputs of the second stage of the combined computational information converter, the second inputs of the first, second, third and fourth blocks of elements And the i-th group are connected to the input of the task the work of the second stage of the combined computational information converter.

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Claims (1)

Computing Formula The combined information, contents converter is a information information converter, the first, second and third inputs of which operation modes are the first, second and third inputs of the specified operation modes of the first stage of the combined information computing converter, from first to seventh information, tp-1 blocks of elements And synchronization, offset to the blue inputs syn30 information inputs of the computing information converter are respectively the first to seventh 'information the first-stage inputs of the combined computing information converter, the first to fourth synchronization inputs of the computing converter are the first to fourth synchronization inputs of the combined first-stage converter, respectively, the analog and digital outputs of the computing information converter are the analog output of the first stage and the digital output of the combined computing information converter characterized in that, in order to expand The functionalities are reduced by providing transformations over the table-given functions of two arguments; a group of m computational converters of groups of four in each and a unit are introduced into it than from the first by synchronizing the computational converter, the information generator is connected respectively to the first and fourth outputs of the synchronization block, from the first the fourth inputs of which are respectively the first to fourth synchronization inputs of the first stage of the combined computing converter and information, the first inputs from the first to fourth blocks of AND elements of the i-th group (i = 1, ..., m-1) are connected respectively to the outputs from the first to fourth · information transfer buses of the i-ro computing group information converter, the outputs of the first , the second, third and fourth blocks of elements And the i-th group are connected respectively to the first, second, third and fourth information inputs (i + 1) -ro of the computing information converter of the group, the digital outputs of the computing information converters of the group are connected to the corresponding m code buses of the first-stage information converter, the analog outputs of the group information converters form a group of analog outputs of the second stage of the combined information converter, the first to fourth 'synchronization inputs of the information converters of the group form the second to fourth synchronization inputs of the second stage of the combined computing information converter, first, second and third inputs Additions of the operating modes of the calculating information converters of the group form the first, second and third groups of inputs, respectively, of the second stage operating modes of the combined computing information converter, the first to eighth information inputs of the computing information converters of the group form the first to eighth information groups the inputs of the second stage of the combined computing information converter, the second inputs of the first, second, third and fourth ith blocks of elements And the i-th group are connected to the input of the job of the second stage of the combined computing information converter.