SU1104510A1 - Digital device for calculating sine-cosine dependences - Google Patents

Abstract

1. DIGITAL APPARATUS FOR CALCULATING sine-cosine dependence comprising a shift register low bits of the argument register high bits of the argument rows, a memory unit, the first and second registers terms, multiplexer, the adder and a control unit, the outputs of the first to fourth of which are connected to control inputs, respectively, of the memory block, the multiplexer, and the write inputs of the first and second term registers, the fifth output of the control unit is connected to the shift input of the shift register of the decimal bits of the argument, the recording stroke and input are connected respectively to the first input of the control unit and the sixth output of the control unit connected to the input of the high-order register entry of the argument, the output of which is connected to the address input of the memory block, the information inputs of the low-order shift register and the high-order argument register are connected with the input argument of the device, so that, in order to reduce hardware costs by reducing the capacity of the memory block, it contains a register of nodal values and a block for inputting the coefficient The control input of which is connected to the seventh output of the control unit, the eighth output and the second and third inputs of which are connected respectively to the recording input of the register of nodal values, the clock input and the recording enable resolution of the device, the ninth output of the control unit is connected to the output of the device conversion end, The information inputs from the first to the third multiplexer are connected respectively to the input of the memory § block, the cyMi-iaTopa output and the first output of the coefficient introduction block, (Л the second output and the information th input of which is connected respectively to the transfer INPUT and the output of the adder, the first and second inputs of the addends of which are connected to the outputs of the first and second registers of the addends respectively, whose information inputs are connected to the output of the register of nodal values, whose information input is connected to the output of the multiplexer and the output of the device and the control unit contains three elements OR-NOT, element NOT, three elements AND-NOT, element AND, three triggers, a counter and a memory node, the first output of which is connected to the first in Odom gate AND, whose output is connected to the counting input of a counter whose output is connected to the first input node memory zeroing counter input connected to the third input of the control unit, first inputs of first OR-NO element and AND-NO element and is connected via

Description

with the installation input into pain of the first trigger, the inverse output of which is connected to the information input of the first trigger and the first input of the second element OR NOT, the output of which is connected to the second input of the AND element and the second input of the memory node, the third and fourth inputs of which are connected respectively, with the output of the third element OR-NOT and the high-order bit of the first input of the control unit, the remaining bits of which are connected to the inputs of the third element OR-NOT, the second inputs of the first elements OR-NOT and AND-NOT are connected to the second input of the control unit and the first input of the second NAND element, the output of which is connected to the second input of the second element OR NONE and the clock input of the first trigger, the installation input in units of which is connected to the second output of the memory node, the third output of which is connected to the installation inputs to zero BTopqro and the third flip-flops, the installation inputs to the unit of which are connected to the outputs of the first and third elements AND-NOT, respectively, the outputs of the first element OR-NOT and the second 1 0 trigger are connected to the inputs of the third element AND-NOT, the output of the third trigger is connected to the second the input of the second element IS-NOT, the outputs from the first to the ninth control unit are connected respectively to the inverse output of the low digit of the counter, the fourth, fifth, sixth and seventh outputs of the memory node, the output of the digit of the counter, the output of the second element OR NOT and the third output of the memory node. 1, differ2. The device according to claim. The input unit is such that the coefficient comprises an adder, a shifter and a correction unit, the information input of the block is connected to the information input of the shifter and the input of the first adder term of the second addend which is connected to the output of the shifter and the input of the correction unit, the output of which is connected to the transfer input of the adder and the second output of the block, the control input and the first output of which are connected respectively to the control input of the shifter and the output of the adder.

The invention relates to computing, in particular to digital computing devices for finding trigonometric functions, and can be used in the development of large specialized integrated circuits for implementing digital sine and cosine solvers, when implementing digital hyperbolic sine and sinus solvers, as well as exponentials. A specialized processor is known that contains a register, a multiplier, an adder, And elements, a memory block, a control block, a shifter. An approximate polynomial is calculated according to the Horner scheme. The presence of a combination multiplier increases the speed L. The disadvantage of this processor is its complexity. Closest to this device is an arithmetic device of a specialized digital computing device containing two input registers into which the high and low bits of the argument are stored, a memory block, two sum registers, a multiplexer, an adder, and a control block. An external signal is used to write the argument to the input registers. The value of the function corresponding to the most significant bits of the input code is retrieved from the memory block and entered into the first register of the terms. Then the control unit increments the address of the memory block by one and its contents are entered into the second storage register of the interpolated function. The process of linear interpolation is carried out by feeding through the multiplexer to the input of the accumulating adder the contents of the first and second registers of the terms, i.e. the value of the function at the beginning and at the end of the interpolated interval. The input low-order register is a shift register. When the code is shifted to the right, a sequential code appears at the output of the least significant bit of the register. It is used to control multiplexer 2. A disadvantage of the known device is that the use of piece-line interpolation in the device with strict accuracy requirements leads to a sharp increase in the memory block size for storing the interpolation nodes. The aim of the invention is to reduce hardware costs by reducing the capacity of the memory block. The goal is achieved by the fact that a digital device for calculating sine-cosine dependences containing the shift register of the lower bits of the argument, the register of the higher bits of the argument, the memory block, the first and second registers of the components, the multiplexer, the adder and the control unit, outputs from first to the fourth one of which is connected to the control inputs of the memory unit, the multiplexer and the write inputs of the first and second term registers, respectively; the fifth output of the control unit is connected to the shift register shift input the best bits of the argument, the output and input of which are connected respectively to the first input of the control unit and the sixth output of the control unit connected to the input of the register of the most significant bit in the argument whose output is connected to the address input of the memory unit, information inputs the shift register of the lower and the register of the higher bits of the argument are connected to the input of the device argument, contains a register of nodal values and a coefficient introduction block, the control input of which is connected to the seventh output of the control block, the eighth output and the second and third inputs of which are connected respectively to the recording input of the register of nodal values, the clock input and the recording enable input of the device; the ninth output of the control unit is connected to the output of the device conversion end, the information inputs of the first to third multiplexer are connected respectively to the output of the memory block t, the output of the adder and the first output of the coefficient introduction unit, the second output and the information input of which are connected respectively to the transfer input and the output of the adder, ne the left and second inputs of the addends of which are connected to the outputs of the first and second registers of the addends, the informational inputs of which are connected to the output of the register of node values, whose information input is connected to the multiplexer output and the device output, and the control unit contains three elements OR NOT, the element NOT, three elements NAND, element AND, three triggers, a counter and a memory node, the first output of which is connected to the first input of the element AND, the output of which is connected to the counting input of the counter, the output of which is connected It is connected to the first input of the memory node, the counter-zeroing input is connected to the third input of the control unit, the first inputs of the first OR-NOT and AND-NOT elements and is NOT connected to the input of the first trigger to zero, the inverse output of which is connected to the information input of the first trigger and the first input of the second element OR NOT, the output of which is connected to the second input of the element AND and the second input of the memory node, the third and fourth inputs of which are connected respectively to the output of the third element OR NOT and the first low input and the control unit, the remaining bits of which are connected to the inputs of the third element OR-NOT, the second inputs of the first elements OR-NOT and AND-NOT are connected to the BTopbiM input of the control unit and the first input of the second element AND-NOT, the output of which is connected to the second input of the second the element OR NOT and the clock input of the first trigger, the installation input to the unit of which is connected to the second output of the memory node, the third output of which is connected to the installation inputs to zero of the second and third triggers, the installation inputs to the unit are connected to the outputs of the corresponding first and third elements, the outputs of the first element OR — NOT and the second trigger are connected to the inputs of the third element AND — NOT, the output of the third trigger is connected to the second input of the second element AND – NOT, the outputs from the first to the ninth control unit are connected respectively with the inverse output of the low bit of the counter, the fourth. the fifth, sixth and seventh outputs of the memory node, the output of the bits of the counter, the output of the second element OR-H, and the third output of the memory node. The coefficient insertion block contains an adder, a shifter and a correction node, the information input of the block is connected to the information input of the shifter and the input of the first term of the adder, the input of the second term of which is connected to the output of the shifter and the input of the correction node whose output is connected to the transfer input of the adder and the second output the block, the control input, whose output output is connected respectively to the control input of the shifter and the output of the adder. FIG. 1 is a block diagram of FIG. 2 and 3 are embodiments of a coefficient introduction unit and a control unit, respectively. The digital device for calculating sine-cosine dependencies contains a shift register 1 lower order bits, a register 2 higher order bits, a memory block 3, a multiplexer 4, a register 5 nodal values, the first and second registers 6 and 7 terms, adder 8, coefficient insertion unit 9 and control unit 10. The coefficient insertion block contains an adder 11, a correction block 12 and a shifter 13. The control block contains elements 14-16, a HE element 17, AND-HE elements 18-20, an AND 21 element, triggers 22-24, a counter 25 and a memory node 26 . A digital device for calculating sine-cosine dependencies works as follows. The inputs 27 and 28 of the control unit 10 receive signals of the clock generator and the signal for writing the argument code. As a result, control unit 10 generates control output signals, namely: output 29 generates a signal recording in registers 1 and 2 of the lower and higher order of the argument, output 30 is a left shift of register 1 of the lower order of the argument, output 31 - add one to the address of memory block 3, output 32 - control the status of multiplexer 4, output 33 write data from multiplexer 4 to the register 5 nodal values, output 34 - write in register 7 terms, interpolate interpolation interval function values, output3 - entry in register 6 of the term values of the interpolation function of the beginning of the interpolation interval, output 36 sets the transfer coefficient of the coefficient insertion block 9. The multi-bit code of the argument received at the input 37 of the lower 1 register and the input 38 of the register 2 most significant bits of the argument, according to the write signal from control block 10, it is written to the low-order register 1 and the high-order 2 register of the argument. Thereafter, the control unit 10 is reset. From the memory block 3, the content is selected at the address recorded in the register 2 of the high-order bits of the argument and through the multiplexer 4 according to the signal from the output 33 of the control block 10 is entered into the register 5 nodal values. Then, the control unit 10 generates a signal for adding one to the address of the memory unit 3, from which the content corresponding to the function value at the end of the interpolation interval is extracted and placed in the register 5 of node values. Since the register control signals of 5 nodal values and the control signals of registers 6 and 7 of the terms are antiphase, the write to the register of 6 or 7 terms, i.e. The former contents of the register of 5 node values are entered into the register of 6 terms, and then, after a clock cycle, the new content is entered into the register of 7 terms. Next, a signal is generated from the output 32 of the control unit 10 to the multiplexer 4. The multiplexer 4 is switched so that the output of the coefficient insertion unit 9 is fed to the information input of the register 5 of nodal values. The inputs of the adder 8 from the registers 6 and 7 of the terms receive signals corresponding to the values of the function of the beginning and end of the interpolation interval. For the edit offset, the signal corresponding to the half-sum of the function value at the beginning and at the end of the interpolation interval is removed from the adder 8, and the function output value corresponding to the middle of the interpolation interval is output at the output of the coefficient insertion block 9. This is achieved in that the required transmission coefficient is generated at the output 36 of the control unit 10. If the least significant bit in register 1 of the least significant bits of the argument is 1, and the rest is O, then control unit 10 stops its operation and the output of device operation in the form of a multi-digit code is formed at the output of multiplexer 4. In this case, the output 39 of the control unit 10 receives a signal about the end of the conversion. It should be noted that when the least significant bits of the argument of all zeros are written to the register 1, the signal about the end of the transform is generated when the output of the interpolation start function appears at the output of the multiplexer 4. At the output 30 of the control unit 10, a shift signal is generated, the most significant bit is pushed out of register 1 of the least significant bits of the argument, and 0 is written in place of the lower bit. The previously calculated value of the function in the middle of the initial interval is written to register 6 or 7 terms. That, after the shift, the high order register 1 of the least significant bits of the argument is 1, then Eu 1 the calculation of the value of the function is entered into the register of 6 terms as the value of the start of the new interpolation interval. If the high-order bit of register 1, the low-order bits of the argument are equal to 0, then the function value is updated at the end of the interval, i.e. An entry is made in the register of the 7 terms. After each iteration, the interval is halved. The transmission coefficient of block 9, the introduction of a coefficient of 1ent, with decreasing interval, tends to 1. Therefore, after a certain number of steps, it is possible to switch to linear interpolation, making an error less than permissible. From the output 32 of the control unit 10, a new value of the control signal is introduced, in which the signal from the output of the adder 8 through the input 40 of the multiplexer 4 is fed to the input of the register 5 of nodal values. This allows for subsequent steps to be limited to linear interpolation. Due to this, it is possible to shorten the cycle time and increase the device speed. The control unit 10 represents an automaton set to its initial state by an external argument recording signal. The internal state and the state of the outputs 31, 32, 30, 29 and 33 of the control unit 10 is determined by the number of pulses of the signal coming from the clock generator (not shown) to the input 32 of this block. The state of the outputs 35 and ZD of the control unit 10 is determined both by its internal state and by the contents of the high order register of the 1 lower order bits of the argument. Let us stop in more detail on the implementation of the coefficient introduction block 9. When calculating the function sinx, cpsx, the block transfer ratio should be1 D1 equal to sec -j-, the Output code of the adder 8 is fed to the input 41 of the adder 11 (Fig. 2), and to the input 42 it through the shifter 12. Output.36 of the control unit 10 sets the shift code. When storing interpolation nodes in memory block 3 with step by argument AO 2 and accuracy of calculations, for example, 27-28 binary bits, the engine 13 should have fifteen information outputs (inputs) and provide only eight two-bit shifts. Since each shift is produced by two bits, the 15-input combination shifter 13 for eight states can be replaced by two shifters (with even and odd inputs) with eight and seven inputs, respectively. In turn, such a shifter can be implemented on a programmable logic array (PLA), which allows the use of eight output functions in a volume of 48 conjunctions of 16 input variables. Note that the combination shift requires a PLA of 36 conjunctions of 11 variables. The redundancy in the PLM of the number of conjunctions and the reserve in the 7-input shifter of one output function allows to generate a correction signal from the output of the coefficient insertion block 9 to the inputs of the pernose of the adder 11 of the block 9 and the adder 8 of the device. Thanks to this, in addition to the shifter, the combinational node can also be placed in one of the PLMs.

12 corrections. The correction signal improves accuracy when working on the largest interpolation interval b. and is functionally a storage unit

5 And the use of constant type - -Gtr

Use as 9 adder 11 with shifter 13 is based on decomposition in a row

one

- eight

1 +

-%

128

In this case, the output code of the adder 8 is applied to the input 41 of the adder 11, to the second input - with a shift, defined. multiplier, and to the transfer inputs of adders 8 and 11 - the correction signal from the outputs of blocks 12 and 9 (one-bit approximation of the expression 20 5. L1).

3 Not

The use of the invention will allow at the current level of technology

to obtain calculators on a single chip with an accuracy of 2A-32 binary bits.

The use of even the simplest type coefficient insertion block (adder and combination shifter) allows for calculating values with an accuracy of 29 bits to reduce the size of the memory block in more than two seconds compared to the memory capacity of the base object.

An important advantage of the proposed. the device is the use of interpolation by the higher bits, which makes it possible to stop the computation at the remaining remaining low bits in the register of the lower bits and to obtain an exact result when performing only a part of the iterations. This significantly distinguishes this device from devices that implement the Walder algorithm, which have low performance at high hardware costs.

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Claims (2)

1. A DIGITAL DEVICE FOR CALCULATING THE SINUS-COSINUS DEPENDENCIES, containing the shift register of the least significant bits of the argument, the register of the highest bits of the argument, a memory block, the first and second registers of the terms, multiplexer, adder and control unit, the outputs from the first to fourth of which are connected to the control a memory block, a multiplexer and recording inputs of the first and second register of terms, the fifth output of the control unit is connected to the input of the shift of the shift register of the least significant bits of the argument, the output is One record of which is connected respectively to the first input of the control unit and the sixth output of the control unit connected to the input of the register of the upper bits of the argument, the output of which is connected to the address input of the memory block, the information inputs of the shift register of the lower bits and the register of the highest bits of the argument are connected to the input of the device argument, due to the fact that, in order to reduce hardware costs by reducing the capacity of the memory unit, it contains a register of nodal values and a coefficient input unit, controlled by the null input of which is connected to the seventh output of the control unit, the eighth output and the second and third inputs of which are connected respectively to the input of the nodal register register, the clock input and the write enable input of the device, the ninth output of the control unit is connected to the output of the device conversion end, information inputs from the first the third of the multiplexer is connected respectively with the output of the memory unit, the output of the adder and the first output of the coefficient input unit, the second output and the information input of which is connected are connected respectively with the input 'transfer and the output of the adder, the first and second inputs of the terms of which are connected to the outputs of the first and second registers of terms, the information inputs of which are connected to the output of the register of nodal values, the information input of which is connected to the output of the multiplexer and the output of the device, moreover, the control unit contains three elements OR-HE, element NOT, three elements NAND, element AND, three triggers, a counter and a memory node, the first output of which is connected to the first input of the element AND, the output of which connected to the counter input of the counter, the output of which is connected to the first input of the memory node, the counter zeroing input is connected to the third input of the control unit, the first inputs of the first elements OR-NOT and AND-NOT, and through the element is NOT connected to the installation input to Paul of the first Trigger whose inverse output is connected to the information input of the first trigger and the first input of the second OR-NOT element, the output of which is connected to the second input of the AND element and the second input of the memory node, the third and fourth inputs of which are connected respectively to the output the house of the third OR-NOT element and the high-order bit of the first input of the control unit, the remaining bits of which are connected to the inputs of the third OR-NOT element, the second inputs of the first elements OR-NOT AND AND — NOT connected to the second input of the control unit and the first input of the second element And NOT, the output of which is connected to the second input of the second OR-NOT element and the clock input of the first trigger, the unit input of which is connected to the second output of the memory node, the third output of which is connected to the zero inputs of the second and third triggers, input When units of one unit are connected to the outputs of the first and third AND-NOT elements, respectively, the outputs of the first OR-NOT element and the second trigger are connected to the inputs of the third AND-element, the output of the third trigger is connected to the second input of the second AND-NOT element, the outputs are the first to ninth control units are connected respectively with the inverse. the output of the least significant bit of the counter, the fourth, fifth, sixth and seventh outputs of the memory node, the output of the bits of the counter, the output of the second OR-NOT element and the third output of the memory node. 2. The device according to claim 1, including the fact that the coefficient input unit comprises an adder, a shifter and a correction unit, the information input of the block being connected to the information input of the shifter and the input of the first term of the adder, . the input of the second term is connected to the output of the shifter and the input of the correction unit, the output of which is connected to the transfer input of the adder and the second output of the block, the control input and the first output of which are connected respectively to the control input of the shifter and the output of the adder.