KR100256463B1 - Process and system for adding or subtracting symbols in any base without converting to a common base - Google Patents

Abstract

Processes and systems are provided that allow the addition and / or addition of any two symbols with any number of characters in any base without having to first convert to a common base with full precision. Regardless of the amount of characters in each symbol, the execution speed is almost constant for the characters. The process and system of the present invention do not require the use of floating point notation. In addition, the processes and systems of the present invention do not require or use standard numerical algorithms, or addition or subtraction tables, or exponentiation.

Description

Processes and systems for adding or subtracting symbols of any base

The present invention relates to a process and system for adding or subtracting symbols of any size to any base without having to first convert to a common base at full precision first.

Many problems arise when adding or subtracting numbers with any base. The number must first be converted to a common base such as base 2 or 10 to perform the calculation. This conversion process takes time. Also, as the number increases, the precision of the calculation result decreases. For example, conventional processes typically involve converting a calculation result to a floating point when the result exceeds a predetermined number of digits. However, converting the result to floating point results in reduced precision.

Accordingly, it is an object of the present invention to create a new and improved process and system that adds or subtracts any two numbers with any base without first having to convert the base to a common base.

Another object of the present invention is a new and improved process that first adds or subtracts a number with any base without having to convert the base to a common base, and the process generates accurate computational results for digits of substantially any size. And to provide a system.

It is a further object of the present invention to provide a new and improved process and system for adding or subtracting numbers with any base without the need to convert the common baseroll beforehand and without converting the result of addition and subtraction to floating point. have.

It is a further object of the present invention to provide a novel and improved process and system for adding or subtracting numbers with any base without first needing to convert the base to a common base and without having to exponentiation.

Another object of the invention is to be able to encode or process a set of data and to decode the resulting data after processing of the encoded data.

It is another object of the present invention to encode or process data in any language, such as, for example, a computer language, a spoken language, a written language, or the like.

Other objects and advantages of the invention will be in part apparent and obvious from the description.

1A-1E are operational flow diagrams illustrating the steps of the process of the present invention.

2 is a functional block diagram of a system for executing a process of the present invention.

3 is a functional block diagram of a bus operation, data processing and data control circuit of the system shown in FIG.

4 is a functional block diagram of a base conversion circuit of the system of FIG.

5 is a functional block diagram of a digital adder circuit of the system shown in FIG.

6 is a functional block diagram of a digital subtraction circuit of the system of FIG.

7 is a block diagram of a sequence controller circuit of the system of FIG.

8 is a functional block diagram of a preferred embodiment of a digital adder and subtractor subsystem that may be used in the system of FIG.

9 is a block diagram of a digital adder circuit of the subsystem of FIG.

10 is a block diagram of a digital subtractor circuit of the subsystem of FIG.

FIG. 11 is a block diagram of a circuit including a combination of the digital adder circuit of FIG. 9 and the digital subtractor circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

602: memory 604: adder and conversion circuit

606: sequence controller 608: reference table

612: address bus 614: data bus

As will be apparent to one of ordinary skill in the art, the foregoing and other objects and advantages are, in the first aspect, arbitrary on any base with full precision without having to first convert to a common base. Processes and systems for performing addition and / or subtraction of any two symbols related to a particular symbol system having a number of characters are achieved in the present invention. Regardless of the amount of characters in each symbol, the execution speed remains nearly constant for each character. The process of the present invention does not need to convert to a base of designated characters, nor to a common base. The process of the present invention also does not require the use of floating point notation. In addition, the process of the present invention does not require or use standard numerical algorithms, addition or subtraction tables, or exponentiation.

The process and system of the present invention performs addition or subtraction of characters using a predetermined floating base. Floating base as used herein means using any base without first converting to a common base. In a preferred embodiment, the process uses at least 2 and at most 36 floating bases. However, the process of the present invention can be modified to use a floating base greater than 36. The process can also be modified to use a base with a decimal point. In a preferred embodiment, the system of the present invention used to carry out the process described above uses more than 2 and less than 127 floating bases.

The characters to be added or subtracted may be numbers, alphabets, signs, symbols, and may also include any language symbols. It may be any computer language or any spoken or written language. Each symbol is associated with a specific symbol system. For example, if two numbers are added in the base ten number system, each number is a symbol, each digit in each number is a letter, and the base ten number system is a symbol system. The process selects a string for operation, and acts on that request. Also, the string can be any length and any character. The process and system of the present invention can be used to send or receive e-mail by designating electronic or computer circuitry, by designating specific identifiers, by designating electronic or computer circuits, in which parts of each block have different bases in encoding a document. have.

In a related aspect, the present invention relates to a first logic circuit for receiving data defining at least two numbers in a number system having a base, each number having at least one digit, the data also defining a desired base, The circuit adds a number of digits to produce a first intermediate sum, the logic circuit compares the first intermediate sum with the base, and the logic circuitry if the intermediate sum is greater than or equal to the base when the signal has a first state. Subtract the desired base from the first intermediate sum to produce the difference, and the first logic circuit outputs the difference if the intermediate sum is greater than or equal to the desired base, or outputs the intermediate sum if the intermediate sum is less than the desired base − ,

A second logic circuit that generates a carry signal for input to the first logic circuit for successive digit addition operations if the first intermediate sum is greater than or equal to the desired base. If small, it generates a no carry signal.

In another aspect, the present invention,

A first logic circuit for receiving data defining at least two numbers in a number system having a base, each number having at least one digit, the data also defining a desired base, and the logic circuitry to generate an intermediate sum Adding a number of digits, the logic circuit compares the first intermediate sum with the base, and the logic circuit derives from the first intermediate sum to produce a difference if the intermediate sum is greater than or equal to the base when the signal has a first state. Subtracts the base, and the first logic circuit outputs the difference if the intermediate sum is greater than or equal to the desired base and outputs the intermediate sum if the intermediate sum is less than the desired base.

A second logic circuit for generating a carry signal for input into the first logic circuit for continuous digit addition operations when the intermediate sum is greater than or equal to the desired base, where the second logic circuit is less than the desired base. The no carry signal is generated-which is directed to the data system.

In another aspect, the invention provides an input circuit for receiving data defining at least two numbers in a number system having a base, each number having at least one digit, the data also defining operation information and a desired base. The operation information determines whether the addition or subtraction operation should be performed.

A first logic circuit for adding a digit of one number and the desired base to produce a first intermediate sum if the operation is subtracted-the first logic circuit corresponds to generating a second intermediate sum if the operation is addition. Add a number of digits, the first logic circuit subtracts another number of digits from the first intermediate sum to produce a first order if the operation is subtracted, and the first logic circuit subtracts the second intermediate sum and the desired base. A comparator circuit for comparing, and outputs a control signal having a first state if the second intermediate sum is greater than or equal to the desired base and a second state if the second intermediate sum is less than the desired base;

Second logic circuit connected to the first logic circuit-the second logic circuit subtracts the desired base from the second intermediate sum to generate a second order when the operation is additive and the control signal has a first state, The comparator circuit of the logic circuit compares the intermediate difference with the desired base, the comparator circuit control signal has a first state if the intermediate difference is greater than or equal to the desired base, and has a second state if the intermediate difference is less than the desired base, and the second logic The circuit subtracts the desired base from the intermediate difference when the operation is subtracted and the control signal has the first state.

Third logic circuit that generates a carry / barrow signal for input to the first logic circuit for use in successive digit add or subtract operations-the carry / barrow signal is an add operation and the second intermediate sum is greater than or equal to the desired base. If the same, or if the operation is subtracted and the intermediate difference is less than the desired base, then the carry / barrow signal is the operation addition and the second intermediate sum is less than the desired base or the operation is subtracted and the intermediate difference is greater than the desired base. Is equal to or has a second state.

In a related aspect, the present invention provides a method comprising the steps of: (a) entering data into a storage match, the data defining at least two numbers in a number system with a base and a desired base, each number having at least one digit, (b) adding a number of digits in the adder circuit to produce a first intermediate sum, (c) determining by the comparator circuit whether the first intermediate sum is greater than or equal to a desired base, (d) step (c) If it is determined that the first intermediate sum is greater than or equal to the desired base, subtracting the desired base from the first intermediate sum in the subtractor circuit to produce a difference, (e) in step (c) the first intermediate sum is Output the difference to the storage medium if it is determined to be greater than or equal to the desired base, or output the storage medium to the first medium sum if it is determined in step (c) that the first intermediate sum is smaller than the desired base. Generating a carry signal with a latch connected to a comparator for inputting into the adder circuit for the next digit addition operation if it is determined in step (c) that the first intermediate sum is greater than or equal to the desired base. Directed to a process for performing an operation on data comprising a step.

In another aspect, the present invention provides a method comprising the steps of: (a) inputting data into a storage match, where the data defines a number in a number system having a base, each number having at least one digit and a value, and the data having a desired base Also defines-(b) adding the desired base with one digit of the number to produce the first intermediate sum in the adder circuit, and (c) the other from the first intermediate sum to generate the intermediate difference in the subtractor circuit. Subtracting the number of digits, (d) determining the comparator circuit if the intermediate difference is greater than or equal to the desired base, and (e) determining the final difference if the intermediate difference is greater than or equal to the desired base in step (c). Subtracting the desired base from the intermediate difference in the subtractor circuit to produce, (f) if the intermediate difference is determined to be greater than or equal to the desired base in step (c). Outputting the final difference to the storage medium, or outputting the intermediate difference to the storage medium if it is determined in step (c) that the intermediate difference is smaller than the desired base, (g) outputting the intermediate difference to the storage medium in step (c). Or if it is determined to be the same, a process for performing an operation on data comprising generating a right signal with a latch connected to the comparator for input to a subtractor circuit for the next digit subtraction operation.

In another aspect, the present invention provides a method comprising the steps of: (a) inputting data into a storage medium, the data defining at least two numbers in a number system having a base, each number having at least one digit and a value; Also defines the operation information and the desired base, where the operation information determines whether the addition or subtraction operation is to be performed, (b) in the adder circuit, the number of bases desired to generate the first intermediate sum if the operation is subtracting. Adding to one of the digits; (c) in the adder circuit, if the operation is an add, adding a corresponding number of digits to produce a second intermediate sum; and (d) in the subtractor circuit, the operation is subtracted. Subtracting another number of digits from the first intermediate sum to produce a first order, if (e) the second intermediate sum is desired if the operation is additive. Determining by the comparator circuit whether it is greater than or equal to the base, and (f) in the subtractor circuit, if the operation is added and it is determined in step (e) that the second intermediate sum is greater than the desired base, the first step is to generate a second order. Subtracting the desired base from the double sum, (g) if the operation is subtracting, determining with a comparator whether the first order is greater than or equal to the desired base, (h) in the subtractor circuit, operation subtracting and in step (g) Subtracting the desired base from the intermediate difference if it is determined that the intermediate difference is greater than or equal to the desired base, (i) carry / barrow for use in steps (c) and (d) for each successive digit addition or subtraction operation. Generating a Signal-The carry / barrow signal is an operation addition and in step (e) the second intermediate sum is greater than or equal to the desired base. If it is determined that the operation is subtracted and the intermediate difference is smaller than the desired base in step (g), the carry / barrow signal has the first state and the carry / barrow signal is the operation added and the second intermediate sum is desired in step (e). Directed to a process for performing an operation on data comprising:-is determined to be smaller than the base, or the operation is subtracted and the intermediate difference is greater than or equal to the desired base in step (g).

In describing preferred embodiments of the present invention, the same reference numerals will be described with reference to FIGS. 1 to 11 which refer to the same features of the present invention.

The following description of the process of the present invention relates to implementing the process of the present invention with a base number of 2 or more and 36 or less. However, the process of the present invention can also be applied to base numbers that are not within the aforementioned range.

1A-1E are operational flow diagrams illustrating the process steps of the present invention. Referring to FIG. 1A, the process begins at step 100, where the following four arguments (i) the number base ("BASER") and (ii) the first number ("NNUM"). "), (Iii) plus or minus sign (" SIGN "), and (iv) second number (" NNUM ") are parsed. Thereafter, a series of checks are performed on the arguments. In step 101, it is checked whether the base corresponds to 2 or more and 36 or less. If the base is outside this range, an error flag is set and the process ends.

Step 102 loads the symbol set into a predefined array designated as a "C" array. The symbol may be a number, a letter, a sign, or the like, and may be formed in any language as described above. Step 103 loads a portion of the symbol set into an "B" array. The portion of the "C" array that is read into the "B" array is from the "0" index of the "C" array to the BASE-1 index of the "C" array. Step 104 loads an "A" array. This "A" array is loaded from the "B" array. The value of the "Nth" index of the "B" array is loaded as the index for the "Nth" index of the "A" array. The "Nth" index of the "B" array is loaded as the value of the "Nth" index of the "A" array. Thus, the "A" array is loaded with data from the "C" array with the index of the "A" array equal to the value of the "C" array element from "0" to BASE-1.

In step 105, numbers are prepared for addition or subtraction operations. In particular, step 105 determines the length of the incoming number to be added or subtracted. The length of the first number NNUM is designated as "M". The length of the second number NNUM1 is designated as M1. In step 105, the variable designated by "CHGSIGN" is initially set to "" (blank).

The process then moves to step 200. In step 200, a "+" factor in which "SIGN" indicates an addition operation is determined. If "SIGN" is "+", the process moves to step 201, which is referred to as the "ADDSIGN" step in FIG.

In step 201, the second or "shorter number" is left-justified to zeros to be the same length as the number having more digits ("longer number"). Step 201 sets variables N and NUM to the length and value of the input digit having the largest number of digits. Step 201 also sets variables N1 and NUM1 to the length and value of the remaining input digits having fewer digits than the input digits designated NUM. If two input numbers have the same number of digits, the length and value of the first input number are specified as N and NUM, respectively, and the length and value of the second input number as N1 and NUM1, respectively, and the second input number. No additions will be added to this. After step 201, the process moves to step 205, described below.

In step 200, if "SIGN" is not "+" RK, the process moves to step 202. In step 202, it is determined whether "SIGN" is "-" indicating a subtraction operation. If it is determined in step 202 that "SIGN" is not "-", the process moves to step 203 described below. In step 202, if it is determined that "SIGN" is not "-", the process moves to step 204 for setting an error flag. The process then ends.

In step 203, designated as "MINUSSING" in FIG. 1B, the variables N and NUM are each assigned the length and value of the input digit having the largest number of digits. Step 203 also sets the length and value of the remaining input digits with fewer digits than the number specified by NUM to variables N1 and NYM1, respectively. The second or "shorter number" is left justified to zero to make the length the same as the number with the larger number of digits ("longer number"). If two input digits contain the same number of digits, the number with the highest value is designated as NUM and the lower number as NUM1. When both numbers have the same number of digits, no additional zero is needed. If the order of the numbers is reversed, that is, NUM is set to a low number and NUM1 is set to a high value number, "CHGSING" is set to "-".

After step 201 and step 203, the process moves to step 205, referred to as " CHECK1 " in FIG. In step 205, the individual digits of the first number are designated NUM and loaded into the " D " array. Digits are loaded from left to right into the "D" array. Step 205 then takes the values of each element of the " D " array and checks or verifies whether the digits are within the defined symbol base by using these values as indexes of the " A " array. Then, in step 205, it is determined whether there is a value at each indexed position of the " A " array. If there is no value in the "A" array, an error plug is set and the process ends.

After step 205, the process moves to step 206. In step 206, the individual digits of the second number designated NUM1 are loaded into the "E" array. Digits are loaded into the "E" array from left to right. Then, step 205 takes the values of each element of the "E" array and uses these values as the index of the "A" array to check or confirm whether the digits are within the defined symbol base. Then, in step 206, it is determined whether there is a value at each indexed position of the " A " array. If there is no value in the "A" array, an error flag is set and the process ends.

Then, in step 207, it is determined whether "SIGN" is "+". If it is determined that "SIGN" is "+", the process moves to the addition routine as shown in FIG. 1C and starts step 300. If in step 207 it is determined that "SIGN" is not "+", the process moves to step 208. Step 208 initiates a subtraction routine beginning at step 400 shown in FIG. 1D.

However, P 300 is the first step of the addition routine. The addition routine shown in steps 300-313 of the flow chart of FIG. 1C, described below by way of example, allows for continuous iteration or cycling through the "D" and "E" arrays simultaneously from the last index to the first index.

The addition routine is shown in the flow chart of FIG. 1d and described by steps 400-413 described in the examples below. The number of the largest value is identified, and the second number is left justified to zero to be the same length as the longest number. If the numbers are the same length and the second number is a larger value, the result will later change to negative to indicate a negative result. Longer numbers are read into an "D" array and shorter numbers are read into an "E" array. The addition routine allows for continuous iteration or cycling through the "D" and "E" arrays from the last index to the first index at the same time. The result of the subtraction is obtained by allowing it to cycle through all the elements of the "TOTAL" array from beginning to end, concatinating the results, and then removing the leading zeros. The sign of the result can be changed and all preceding zeros are removed except when there is only one zero.

The process of the present invention can be implemented in any of a variety of programming languages. Certain process steps may change when the process is implemented in a given language. However, in some programming languages such as REXX, there is no need to change.

The process of the present invention executes any two numbers of additions and / or subtractions with any number of digits to any base with complete precision and without the need to convert to a common base. Regardless of the number of digits in each number, the execution speed is almost constant for each digit. As mentioned above, the process of the present invention does not require conversion to a common base. The process of the present invention produces a result with full precision regardless of how many digits are used in the addition or subtraction operation. In addition, the process of the present invention includes (i) conversion to floating point, (ii) standard numerical algorithms for converting numbers from one base to another, (iii) definition of addition or subtraction tables, and (iv Does not require the use of exponentiation.

[System Architecture]

Referring to FIG. 2, a block diagram of a system 600 used to execute the process of the present invention is shown. The basic function of system 600 is to add or subtract two integers with a particular base. The integer can be of any length (ie, the number of digits is limited only by the amount of system memory). In addition, the base system for two integers is selectable within a range of specific design configurations (eg, 2 to 127).

The system 600 uses (i) converting digit symbols from a specific base to binary or from binary to a specific base using a ROM (Read Only Memory) reference table, and (ii) using a binary operation to convert the digits. It performs three functions: adding or subtracting, and (iii) processing each pair of digits of an input number or operand consecutively starting from the lowest digit.

System 600 includes an adder and conversion circuit 604, a sequence controller 606, and a system reference table 608. System 600 interfaces with memory 602. The memory 60 2 includes a random access memory section (RAM) 602a and a register stack section 602b. The random memory access unit 602a operates as shared memory. The memory portion 602 a and the register stack 602 b operate as translation links for interfacing data and control signals input to the system 600. This configuration is similar to how software functions interface with calling programs and pass parameters.

Adder and conversion circuit 604 receives two input operands or numbers from memory 602 via bus 610. Circuit 604 performs the basic arithmetic operations of base transform, addition, and subtraction for each digit of the two input numbers. Circuit 604 may be implemented with an arithmetic logic unit (ALU). The conversion of each digit symbol from a particular base to binary and vice versa is performed through symbol reference table 608. The lookup table 608 receives the table address generated by the circuit 604 via the address bus 612. The conversion is routed back to circuit 604 via data bus 614. Reference table 608 is preferably EPROM (erasable programmable read only memory). The circuit 604 outputs an error signal "ERR" 630 when inappropriate input data or hardware error is detected. The circuit 604 also outputs a carry "CO" signal 632, which will be described below.

Loop sequencing, error checking, and timing control are generated by the sequence controller 606. Controller 606 receives the system's master clock signal "CLK" 616, reset signal "RST" 618, and operation start clock signal "START" 620 from the main hardware system (not shown). Receive. Signals 616, 618, 620 drive and synchronize system 600. The sequence controller receives the "CO" signal 632 and processes the carry and barrow states for a sequential pair of digits to be added or subtracted. Controller 606 generates an address of a memory location within memory 602 that contains the input number to be added or subtracted. The address is input to the memory 602 via the data bus 622. Data is interchanged between the memory 602 and the controller 606 via the data bus 628. The parameters and data interface are based on shared access of the memory 602. Controller 606 outputs a multi-bit control "CNTL" signal 634 for each sequential series of execution steps. The controller 606 outputs a "STATUS" signal 624 to indicate the status condition of the system 600. The controller 606 also outputs an error indication signal "ERR" 626. The error signal "ERR" 626 is output in response to receiving any error from the circuit 604 that the error signal "ERR" 630 and the sequence controller 606 encounter.

The main hardware system (not shown) loads data, two integer operands into the shared memory section 602a, prior to outputting the RST and START signals 618, 620, which are input to the controller 606, The remaining parameters are loaded into the register stack section 602b. Circuit 604 loads the result of the addition or subtraction operation and other parameters on data bus 610 for input into shared memory portion 602 a and register stack portion 602 b for use by the main hardware system. .

3 shows bussing and configuration of the data area and control of the system 600. Three data blocks N1, N2, and Nx are shown in shared system memory 602a. N1 and N2 are two input integers to be added or subtracted, and Nx is a memory location where the result of the addition or addition operation is to be loaded. N1 and N2 may each consist of any number of digits. The output area for Nx is preferably at least one digit larger than the larger of N1 and N2. In the description that follows, the system configuration is based on one byte characters per digit, and the base range is 2 or more and 128 or less.

The register stack 602b stores eight parameters. The first register, designated "FUNC", represents the function to be performed, i.e. addition (+) or subtraction (-). The second register designated as "BASE" stores the numeric base to be used. The sixth, seventh, and eighth registers designated N1 @, N2 @, and Nx @, respectively, contain the memory addresses of the lowest digits for each integer. The third, fourth, and fifth registers designated N1_CNT, N2_CNT, and Nx_CNT, respectively, include counts or amounts (or lengths) of integer digits, respectively.

In a variant embodiment, the selected parameters may be loaded from the memory 602b into the register stack via the macro 636 shown in dashed lines without using the main hardware system. Through this configuration, the system 600 may be changed into a self contained system.

The function parameter stored in the "FUNC" register is typically 1 byte (ie 8 bits) and decoded into one of a number of possible functions, such as 1: 256, via the function decoder 637. As described above, the process of the present invention is configured to execute two functions, "+" (addition) and "-" (subtraction). If any other function is loaded into the register stack 602b, it will generate an error signal. However, system 600 may be extended to perform functions other than addition or subtraction.

System memory address bus multiplexer 640 receives a selection signal "SEL". The select signal " SEL " is received from the sequence controller 606 to select Nij to be addressed via an address stored in the Ni @ register and consists of a two bit control signal 634 (where I = 1, 2 or x is an integer, and j represents a specific digit for each integer). This configuration allows reading specific digits for N1 or N2 and writing digits to Nx via data bus 610. As each set of digits is processed, the Ni @ register is incremented to an address in the next digit system memory 602a. The main system (not shown) can fully access and control the system memory 602a via the address bus 622 and data bus 610.

The contents of the register designated as "BASE" in the register stack 602b are converted to a binary representation of the preferred number base. This is accomplished by the base select system reference circuit 700 shown in FIG. Base-converter circuit 700 converts the input base-symbol into an equivalent binary representation. As an example, when computed at base 16 for symbol " G ", the output of the base converter circuit is' 00010000'b. The base parameter 702 represented by the symbol in the particular base is output from the raster stack 602b and input into the address decode circuit 704 which generates the address of the EPROM 706. The content of EPROM 706 is pre-loaded with the corresponding binary representation of the base symbol to be decoded. Any base symbol with 8-bits will be decoded into a unique EPPOM address (1: 256). EPROM 706 preloads' 0'b at an address location corresponding to a symbol that does not indicate a valid or supported base, thereby generating an "invalid base" error. The output 708 of the EPROM 706 is a base in binary form and is input to the symbol reference circuits 608a-c and the digit add / subtract circuit 604. Comparator 710 checks whether the base binary value is greater than one. If the value of the base is not greater than 1, an error condition is flagged for the sequencer 606.

The actual symbol conversion is performed at one time after the invocation of the function. The output base in binary form is input to N1, N2, Nx symbol reference circuits 608a, 608b, 608c, which are three separate parts of the EPROM search circuit 608 of FIG. The output binary base is also input to the add / subtract circuit 604. N1 and N2 symbol reference circuits 608a and 608b convert the input digit symbols into binary representations of the symbols for the selected base, respectively. The binary representation is latched in the output register before being input into the circuit 604.

The Nx symbol reference circuit 608c is operated in the opposite manner to the N1 and N2 symbol reference circuits 608a and 608b described above. Circuit 608c receives the binary digits and converts the digits into equivalent representation symbols for the selected number base. Equivalence representation symbols are latched into output registers and then written to system memory 602a via data bus 610. The symbols N1j, N2j, and Nxj represent j-th digit symbols for N1, N2, and Nx, respectively.

The function of the digit add / subtract circuit 604 is to perform binary addition or subtraction on binary digit pairs in the selected number base system. This operation is then repeated for every digit of N1 and N2 from the lowest digit to the most significant digit in succession. This feature maintains proper carry and borrow between digit operations. This operation differs significantly from conventional binary addition or subtraction.

The sign multiplexer 650 adds a "-" sign symbol upon receipt of the selection signal "SEL" from the state sequencer circuit 606 when the result of the subtraction operation is a negative result. After the state sequencer 606 examines the carry / barrow output signal " Co / Bo " 632 outputted by the circuit 604, it is determined whether the state sequencer 606 outputs the selection signal " SEL ".

State sequencer circuit 606 steps through all of the hardware state necessary to perform the desired function. Circuit 606 uses N1_COT from register stack 602b to determine the number of digits accessed from system memory 602a. Circuit 606 flags the error via the error signal "ERR" 626 due to improper input data or system outage status.

Referring to FIG. 4, the base-to-symbol, N1 and N2 conversion operations are shown. The Nx symbol conversion function is not explicitly shown in FIG. 4, which is substantially the same as N1. The Nx symbol conversion function will be described in more detail below. As mentioned above, the main function of these blocks is to convert certain integers from base symbols to binary and vice versa. This is accomplished in hardware using the EPROM reference table.

Referring back to FIGS. 3 and 4, the N1 and N2 symbol search circuits 608a, 608b are functionally identical to each other. However, only the circuit 608a is described to simplify the following description. Circuit 608a converts each integer symbol Nij into equivalent binary representation. The integer symbol 712 is output from the system memory 602a and input to the address decode circuit 714 which generates one of the addresses of the EPROM 716. The specific EPROM reference table is selected by the base used. This allows full independence from the base-to-base symbol definition. If the base symbol is an ordered subset of the next higher order base and it is kept for all the bases used, the EPROM can be reduced to a single table. The binary output 718 of the selected EPROM is also checked through the comparator 720 in order to make this value smaller than the base binary value to be used. This process is repeated for each digit symbol of the input integer for the Ni_CNT digit. Ni_CNT comparator 722 causes circuit 608 to set to zero when clocked above the number of digits in the integer. This is required to handle integers of unequal length by patting zero to a shorter number of higher order positions. The binary output 718 is then latched into an output register 724 and sent to the add / subtract circuit 604.

The Nx symbol search circuit 608c performs the same function as the circuits 608a and 608b, but in the opposite manner in which the circuits 608a and 608b are performed. Circuit 608c receives binary input from sign multiplexer circuit 650 which receives input from add / subtract circuit 604. The circuit 608c then converts the input back to the corresponding base symbol. Circuit 608c is similar to circuits 608a and 6087b, but the EPROM in circuit 608c is loaded with different data. Circuit 608c does not require a comparator for checking the length of integers. The length of the integer output from circuit 608c is set by increasing Nx_CNT for all digits processed by sequencer 606.

Adding two binary digits of a particular base is a simpler operation if the two digits and the base are represented in a true binary form. Adding two 8-bit digits adds a number of standard logic macros configured to implement the functionality of some of the digit adder auxiliary circuits 800 of the digit add / subtract circuit 604 (see FIG. 3) shown in FIG. Can be achieved by use. Referring to FIG. 5, an intermediate sum is generated by the 8-bit adder circuit bit 802. Circuit 802 may be implemented by a standard 8-bit binary add / subtract macro with a carry input. For the first digit pair, the carry input is set to zero by the sequence controller 606. The intermediate sum is then compared by the comparator 804 with the base in binary form as well. Comparator 804 can be implemented by an 8-bit comparator macro. If the output of the comparator is set to " 1 " (i.e., intermediate sum ≥ base), the comparator sets a carry latch (L) 806 for the next operation and allows the base to propagate through the AND gate 808. . The last operation conditionally subtracts the base from the intermediate sum. This step is accomplished by subtraction circuit 810, which may also be implemented by an 8-bit binary macro. Carry out is also sent to the sequence controller 606 for final digit generation. Thus, circuit 800 includes a) adding a digit to produce an intermediate sum, b) comparing the intermediate sum with a base, and c) subtracting the base from the intermediate sum, if intermediate sum≥base. Setting a carry for addition to the next digit pair, d) subtracting zero from the middle sum if intermediate sum ≥ base, and setting a no carrry for addition to the next digit pair. Step, e) adding two digits, comprising repeating the above process for all digit pairs.

Referring to FIG. 6, an auxiliary circuit 900 for digit addition is shown. Circuit 900 is part of circuit 604 shown in FIG. The sequencer 606 processes twice all the digits contained in the two numbers when N1 is smaller than N2. The adder circuit 902 adds BASE to N1i (the first digit of the integer N1) to provide an intermediate sum. N2i (first digit of N2), N2i, borrow-in is subtracted from the intermediate sum through a subtraction circuit 904 to provide the intermediate difference. For the first pair of digits, the barlow-in is set to zero by the sequence controller 606. The intermediate difference is then compared to BASE by comparator 906. If the output of the comparator is set to " 1 " (i.e., intermediate difference≥base), the comparator resets the right latch (L) 906 for the next operation, causing BASE to propagate through the AND gate 908. . The final operation is conditionally subtracting the BASE from the intermediate difference via the subtraction circuit 910. The bow-in is also sent to the sequence controller 606 to determine if a second pass is required and to generate a subtraction sign ("-"). Accordingly, the auxiliary circuit 900 includes a) adding BASE to N1i to produce an intermediate sum, b) subtracting N2i and barlow-in from the sum to produce an intermediate difference, c) Comparing BASE, d) subtracting the base from the intermediate difference if intermediate difference≥base, setting no borrow for subtraction of the next digit pair, e) intermediate difference≥base If, the process of subtracting two digits comprising subtracting zero from the intermediate difference, setting the barrow for subtraction of the next digit pair, and f) repeating the above process for all pairs of digits. Do this.

At the end of the sequence, if the barlow state for the highest pair of digits is set, the sequencer 606 determines N1 > N2, and a second pass is initiated. The second pass consists of address pointer Ni_ @, recovery of digit counter Ni_CNT and swapping N1 and N2. Swapping of N1 and N2 is achieved by simply swapping the corresponding memory address registers N1_ @ and N2_ @. When the recovery and swapping operation is completed, the above-described digit subtraction processor is repeated again.

Referring to FIG. 7, the sequence controller 606 is a simple state machine implemented using a basic shift register. Sequencer controller 606 is started by enabling the system clock for the shift register and keeping the clock enabled while any shift register latch is on. The shift register is loaded into logic "1" by the first clock pulse and the START signal. Logic "1" is passed through the entire shift register string by turning on one latch at a time. The last latch generates a reset signal and enables the completion status condition (addition or subtraction process terminated) or error condition described above.

Recursion of sequencer 606 on a subset of states can be accomplished by forcing the bits in the branching latches in the shift register to the desired state until the desired number of loops are performed. This recursive capability is required once for each digit pair when an add or subtract operation is executed repeatedly. The basic functions performed by the sequence controller 606 include: a) resetting the system 600, b) setting a busy state for the system 600, and c) parameters from the memory 602, if necessary. D) store parameters received from register stack 602b, e) select and read base symbols, f) select and read N1I symbols, g) select and read N2i symbols, and h ) Decode and execute an operation, i) select and record an Nxi symbol, j) maintain (increment & decrement) counters and address registers, k) determine and set up a recursive condition, and l) (N1). <N2) determine a number of subtraction pass conditions, m) set the most significant digit ("1" or "-"), n) issue an error state, and o) terminate processing.

8 shows a strain adder / subtracter circuit 1000. The circuit 1000 is a variable base digit add / subtract circuit. Circuit 1000 performs a binary addition or subtraction operation on the previously coded digit pair in the selected number base scheme. Circuit 1000 is repeatedly enabled to perform addition or subtraction operations in a sequential manner on all digits in the pair in pairs of numbers from the least significant digit to the most significant. The circuit 1000 maintains the appropriate carry and barlow state conditions during operation for each digit pair, and considers the input data valid. Circuit 1000 performs addition and subtraction operations in a manner significantly different from conventional binary addition or subtraction.

Referring to FIG. 8, all databases are 8 bits wide. The Digit_1 and Digit_2 buses are binary coded digits to be added or subtracted with carry / barrow-in (Ci). The selected number base on which the operation is to be performed is input to the circuit 1000 through a database designated as BASE. The circuit 1000 outputs the result of the addition or subtraction operation on the Digit_Out bus, and also outputs a carry / barrow output Co state. The circuit 1000 also receives "Rst" and "Add / Sub" signals to select the initialization function mode. The system clocking distribution is not shown.

9 shows the auxiliary circuit 1100 of the digit adder of the digit add / subtract circuit 1000. As shown in FIG. Adding two binary digits from a particular base is much simpler if the two digits and the base are represented in true binary format. Adding two 8-bit digits can be accomplished by using a number of standard logic macros configured to perform the function of circuit 1100. Referring to FIG. 9, an intermediate sum of Ni and N2i (input integer to be added) is generated by the 8-bit adder circuit 1102. The intermediate sum is then compared to the base by an 8-bit binary comparator 1104 also in binary form. If mid sum ≥ base, the output of comparator 1104 is set to logic "1", which sets carry latch (L) 1105 for the next operation, and the base propagates through AND gate 1108. Be sure to The subtraction circuit 1110 conditionally performs the last step of the addition operation of subtracting the base from the intermediate sum. Accordingly, the auxiliary circuit 1100 subtracts the base from the intermediate sum, a) adding a digit to produce an intermediate sum, b) comparing the intermediate sum with the base, and c) subtracting the base sum if intermediate sum≥base. Step, setting the carry for the addition of the next digit pair, d) subtracting zero from the middle sum, if intermediate sum≥base, setting the no carry for addition of the next digit pair, e) all A process of adding two digits is performed which includes repeating the above process for a digit pair.

Referring to FIG. 10, a digit subtraction circuit 1200 is shown. The circuit 1200 realizes a subtraction operation of the digit addition / subtraction circuit 1000. Adder circuit 1202 adds base "BASE" to N1i (the first digit of integer N1) to produce an intermediate sum. Subtraction circuit 1204 subtracts N2i (the first digit of integer N2) and the right-in "BI" from the intermediate sum to produce an intermediate difference. For the first pair of digits, the right-in "BI" is set to zero by the sequence controller 606. The intermediate difference is then compared to the base "BASE" by the comparator 1206. If intermediate difference ≥ base, comparator 1206 outputs a logic "1", which resets the right latch (L) 1208 for the next operation, allowing the base to propagate through the AND gate 1210. do. Subtraction circuit 1212 conditionally performs a final operation of subtracting the base from the intermediate difference. A bor-out "BO" is also sent to the sequence controller 606 to determine whether a second pass is needed and whether to generate a "-" sign. Thus, circuit 1200 may comprise: a) adding BASE to N1i (the first digit of the first integer) to produce an intermediate sum, b) N2i (the second integer) from the intermediate sum to generate the intermediate difference. Subtracting the first digit) and the barrow, c) comparing the intermediate difference with BASE, d) subtracting the base from the intermediate difference to produce the final difference, if intermediate difference ≥ base, of the next digit pair Setting the no barrow for subtraction, e) subtracting zero from the middle car if intermediate difference≥base, setting the barrow for subtraction of the next digit pair, f) as described above for all digit pairs A process for subtracting two digits is included which includes repeating the process.

Referring to FIG. 11, the circuit 1300 includes a combination of digit add and subtract logic logic circuits 1100 and 1200, respectively. The circuit 1300 has an "Add / Sub" control line. When the add operation is to be performed, the Add / Sub control line input to AND gate 1302 is at logic " 0 ". When the subtraction operation is to be performed, the Add / Sub control line is at the logic "1" level. Thus, when Add / sub is at the logic "0" level, the output of AND gate 1302 is logic "0", and when Add / sub is at the logic "1" level, the output of AND gate 1302 is "BASE" which is the base data on the data bus. Add / sub circuit 1306 is also controlled by an Add / sub control line.

When the Add / sub control line is at logic "1", circuit 1304 adds the base to the i th digit of the first integer to produce a first intermediate sum. The circuit 1306 then subtracts the i th digit of the second integer from the first intermediate sum to produce an intermediate difference. The intermediate difference is then compared to the base "BASE" by the comparator 1308. If the difference is ≧ base, the comparator 1308 outputs a logic “1”, which resets the select register 1310 that resets the right latch “L” 1312. Logic " 1 " output from register 1131 also enables AND gate 1314 to transfer the base to subtraction circuit 1316. The circuit 1316 then subtracts the base from the intermediate difference. When the intermediate difference is smaller than the base, the comparator 1308 outputs a logic "0", which sets the select register 1310. Once the select register 1310 is set, the select register 1310 outputs a signal that sets the right / carry latch “L” 1312 for the next digit pair to be subtracted. When the latch 1312 is set, the right / carry signal "Co / Bo" is propagated to the sequence controller to determine whether a second pass is required and whether to generate a "-" sign. Logic “0” output from comparator 1308 is also input to AND gate 1314, which prevents the base from propagating to subtracting circuit 1416. Thus, when the intermediate difference is less than the base, the circuit 1316 subtracts zero from the intermediate difference.

When the Add / Sub control line is at logic "0", circuit 1304 adds zero to the i th digit of the first integer. The circuit 1306 then adds the i th digit of the first and second integers to produce the final sum. The final sum is then compared by base comparator 1308 with the base "BASE". If the final sum≥base, the comparator 1308 outputs a logic "1" to set the select register 1310 which sets the right latch "L" 1312, thereby carrying it for addition to the next digit pair. The signal Co is set. The logic " 1 " output from the comparator 1308 is also input to the AND gate 1314 which propagates the base to the subtraction circuit 1316. The circuit 1316 then subtracts the base from the final sum. When the final sum is less than the base, the comparator 1308 outputs a logic "0", which resets the select register 1310. Thus, the right / carry latch “L” 1312 will not set the carry for the next digit pair to be added. Logic "0" output from comparator 1308 is also input to AND gate 1314 and prevents the base from propagating to subtraction circuit 1316. Thus, when the final sum is less than the base, circuit 1316 subtracts zero from the final sum.

Accordingly, the circuit 1300 determines whether a) an addition or subtraction operation is to be performed, and if it is an addition, sets "Add / Sub" to "0", otherwise, "Add / Sub". Setting "to" 1 ", b) adding zero to the digit of the first integer N1 if the addition operation should be performed, c) otherwise, if the subtraction operation should be performed, the first intermediate sum. Adding a base to the digit of the first integer N1 to generate a; d) if the addition operation is to be performed, add the digit of the first integer N1 to the digit of the second integer N2 to generate a second intermediate sum; One step, e) otherwise, if a subtraction operation is to be performed, subtracting the first integer digit from the first intermediate sum to generate an intermediate difference, f) the operation is addition, and the second intermediate sum≥base If, from the second intermediate sum Subtracting the case, setting carry Co for addition of the next digit pair, g) otherwise subtracting zero from the second intermediate sum, if the second intermediate sum is less than the base, Setting the no carry Co for addition, h) subtracting the base from the intermediate difference if the operation is subtractive and intermediate difference≥base, setting the no-baro Bo for the next digit pair to be subtracted, I ) Otherwise, if the intermediate difference is less than the base, subtracting zero from the intermediate difference, setting Baro Bo for the next digit pair to be subtracted, j) repeating the above process for all digit pairs Run the process of adding or subtracting two digits.

The system of the present invention is configured to add and subtract string pairs of digits, but the system can be modified to perform additional and more complex operations. In addition, the specific subsystems described above may be implemented through various integrated circuit technologies.

The process and system of the present invention allow processing of data other than Arrai numbers. As mentioned above, the data may be selected from the group comprising numbers, alphabets, symbols, symbols or any symbol. It includes any computer language, or any spoken or written language. For example, the data may be two personal names that need to be added or subtracted, and the resulting data will be a new name. If this process is reversed, the user will get back the two original names. Application of the present invention in this manner will be very useful for encoding or encrypting a message and then subsequently decoding this data. The person who intercepts such data does not know how to decode such data. This is because, firstly, they do not know that the base is used, nor do they know that the floating base is used.

Although the present invention has been specifically described in connection with certain preferred embodiments, many variations, modifications and variations will be apparent to those of ordinary skill in the art in view of the foregoing description. Accordingly, the appended claims should be considered to embrace any alterations, modifications and variations as long as they fall within the true scope and spirit of the invention.

The present invention provides a novel and improved process and system for adding or subtracting any two numbers with any base without first needing to convert the base to a common base, and also without having to first convert the base to a common base. In providing new and improved processes and systems for adding or subtracting numbers with a base, the process produces accurate computer results for virtually any size digit, and does not need to convert to a common base in advance, Create new and improved processes and systems for adding or subtracting numbers with arbitrary bases without converting the result to floating point, and first having any bases without converting the base to a common base using exponentiation. Add or subtract numbers Provides new and improved processes and systems. The systems and methods provided by the present invention encode or process a set of data, and allow post-processing encoded data to decode the resulting data, for example, computer language, spoken language, written language ( written) allows you to encode or process data in any language, such as language.

Claims (29)

A data system, comprising: (a) a first logic circuit for receiving data defining at least two numbers in a number system having a base; Each number has at least one digit, the data also defines a desired base, the logic circuit adds the digits of the number to produce a first interim sum, the logic circuit Compares the first intermediate sum with the base, and wherein the logic circuit generates the first intermediate sum to produce a difference when the intermediate sum is greater than or equal to the base when the signal has a first state. Subtracts the desired base from the first logic circuit and outputs the difference if the intermediate sum is greater than or equal to the desired base, or the intermediate sum is less than the desired base. Output the intermediate sum when the first intermediate sum is greater than or equal to the desired base, and a carry signal to be input to the first logic circuit for subsequent digit-add operation. And a second logic circuit for generating a no carry signal when the first intermediate sum is less than the desired base. 2. The data system of claim 1, wherein the first logic circuit comprises a storage medium to receive data defining the numbers in the number system having the base and the desired base. 3. The first logic circuit of claim 2 further comprising: an adder circuit that adds the number of digits to produce the first intermediate sum, and wherein the first intermediate sum is greater than the desired base; And a comparator circuit having a first state in the same case and outputting a signal having a second state when the intermediate sum is less than the desired base. 4. The circuit of claim 3, wherein the second logic circuit comprises a latch responsive to the comparator and connected to the adder circuit, the latch being subsequent if the first intermediate sum is greater than or equal to the desired base. And a carry signal to be input to the adder circuit for a digit add operation, and generate a no carry signal when the first intermediate sum is less than the base. 2. The data system of claim 1, wherein the first logic circuit is configured to subtract zero from the intermediate sum when the intermediate sum is greater than or equal to the desired base. 2. The data system of claim 1 wherein the first logic circuit further comprises means for determining the number of digits in each number. The data system of claim 1, further comprising means for left-justified to zero for a number having fewer digits. 8. The system of claim 7, wherein the first logic circuit comprises a plurality of memory locations, the data system for storing a number having more digits and a number having fewer digits to a predetermined memory location. A data system further comprising means. A data system comprising: (a) a first logic circuit for receiving data defining at least two numbers in a number system having a base, each number having a value and at least one digit, said data being desired Also defines a base, the first logic circuit adds the desired base to each digit of the number having a larger digit amount or larger value to produce an intermediate sum, the first logic circuit generates an intermediate difference. Subtract the desired base from the intermediate sum to subtract the base circuit from the intermediate difference to produce a final difference when the intermediate difference is greater than or equal to the desired base. Output the last difference if the intermediate difference is greater than or equal to the desired base, or the intermediate difference is the desired bay Outputs the intermediate difference if smaller-(b) generates a borrow signal to be input to the first logic circuit for subsequent digit subtraction operations if the intermediate difference is smaller than the desired base, and And a second logic circuit for generating a no carry signal when the intermediate difference is greater than or equal to the desired base. 10. The data system of claim 9, wherein the first logic circuit comprises a storage medium to receive the data defining the numbers in the number system having the predetermined base and the desired base. 11. The apparatus of claim 10, wherein the first Lodge circuit comprises: an adder circuit that adds the desired base to each digit of a larger amount of digits or a larger value to produce the intermediate sum; A first subtractor circuit that subtracts the desired base from the intermediate sum in response to the adder circuit to produce a first state when the intermediate difference is greater than or equal to the desired base and the intermediate difference is less than the desired base. And a comparator circuit for outputting a signal having a second state in the case. 12. The circuit of claim 11 wherein the first logic circuit further comprises a latch responsive to the comparator and connected to the first subtractor circuit, the latch being input to the first subtractor circuit when the intermediate difference is less than the desired base. And a no carry signal if the intermediate difference is greater than or equal to the desired base. 10. The data system of claim 9, wherein the first logic circuit is configured to subtract zero from the intermediate difference when the intermediate difference is less than the base. 10. The data system of claim 9, wherein the first logic circuit further comprises means for determining the number of digits in each number. 15. The data system of claim 14 wherein the first logic circuit further comprises means for determining a number having a larger value. A data system comprising: (a) an input circuit for receiving data defining at least two numbers in a number system having a base, each number having at least one digit, said data also defining operation information and a desired base; The operation information determines whether an addition or subtraction operation should be performed; and (b) a first base that adds the desired base to one of the numbers to generate a first intermediate sum if the operation is subtraction. Logic Circuit-The first logic circuit adds a corresponding number of digits to produce a second intermediate sum when the operation is an add, and the first logic circuit generates a first order when the operation is subtracted. To subtract another number of digits from the first intermediate sum, the first logic circuit being equal to the second intermediate sum. Comparing a desired base, the control signal having a first state is output when the second intermediate sum is greater than or equal to the desired base, and the control signal having a second state is output when the second intermediate sum is less than the desired base. And (c) a second logic circuit connected to said first logic circuit, said second logic circuit comprising a second difference if said operation is addition and said control signal has a first state. Subtract the desired base from the second intermediate sum to produce, a comparator circuit of the first logic circuit compares the intermediate difference with the desired base, and the comparator circuit control signal is greater than the desired base. Is equal to or greater than or equal to the first state, and the intermediate difference is smaller than the desired base. Subtract the desired base from the intermediate difference if the previous operation is subtracting and the control signal has a first state-and (d) a carry to be input to the first logic circuit for use in subsequent digit addition or subtraction operations. A third logic circuit for generating a Barrow signal, wherein the carry / barrow signal is such that the operation is addition and the second intermediate sum is greater than or equal to the desired base or the operation is subtracted and the intermediate difference is less than the desired base. The second state if the operation is an addition and the second intermediate sum is less than the desired base or if the operation is subtracted and the intermediate difference is greater than or equal to the desired base. Has-a data system that includes. 17. The apparatus of claim 16, further comprising an output circuit for outputting a second difference when the operation is addition and the control signal has a first state, wherein the output circuit further includes the operation being added and the control signal being second. Outputting the second intermediate sum if the state is subtracted; outputting the final difference if the operation is subtracted; and if the control signal has the first state, outputting the final difference; Data system that outputs the primary if it has. 17. The data system of claim 16 wherein the input comprises a memory having a plurality of memory locations each having an address. 17. The apparatus of claim 16, wherein the first logic circuit comprises: (a) an adder circuit for generating the first intermediate sum; and (b) the second intermediate sum is generated if the operation is subtracted. And a subtracter-subtractor for generating the first difference if subtracted. 17. The data system of claim 16, wherein the second logic circuit includes a subtractor circuit for generating the second difference when the operation is an addition and generating the final difference when the operation is a subtraction. 17. The data system of claim 16 wherein the input circuit includes means for determining the number of digits in each number. 17. The data system of claim 16 wherein the input circuit further comprises means for determining a value of each number. 23. The data system of claim 22, further comprising means for assigning a minus sign to a final difference having a value less than zero. 19. The sequence controller of claim 18, having a input for receiving a data system clock signal, the sequence controller generating a memory location address of the memory for sequentially transferring each number of digits to the first logic circuit. The data system further includes). 17. The string of claim 1, 9 or 16, wherein the numbers in the number system are numbers, words, letters, signs, strings representing encoded data, strings representing characters and encoded characters representing encoded data. Data system selected from the group comprising. A data system comprising: (a) a first logic circuit for receiving data defining at least two symbols in a symbol system with a base, each symbol having at least one character, said data having a desired base; The logic circuit further adds the characters of the symbols to produce a first intermediate sum, compares the first intermediate sum with a base, and when the signal has a first state, Subtracts the desired base from the first intermediate sum to produce a difference if greater than or equal to a base, and the first logic circuit outputs the difference if the intermediate sum is greater than or equal to the desired base, or the intermediate Output the intermediate sum when the sum is less than the desired base, and (b) the first intermediate sum is greater than or equal to the desired base. Wu generate a carry signal is input to the first logic circuit for the subsequent character the addition operation that is, the first case is smaller than the first base is the desired intermediate sum no data system including a second logic circuit for generating the carry signal. 27. The data system of claim 26, wherein each symbol is selected from the group comprising a number, a word, a letter, a sign, a string representing encoded data, a string of characters and combinations of numbers representing encoded data. A data system comprising: (a) a first logic circuit for receiving data defining at least two symbols in a symbol system having a base, each symbol having at least one character, said data also defining a desired base; The first logic circuit adds the desired base to each character of a symbol having a greater amount of quantity or a larger value to produce an intermediate sum, and the first logic circuit adds the intermediate sum to generate an intermediate difference. Subtracting the desired base from the logic circuit subtracting the base from the intermediate difference to produce a final difference when the intermediate difference is greater than or equal to the desired base, and the first logic circuit subtracts the desired difference from the intermediate difference. Outputs the final difference if it is greater than or equal to the base or the intermediate difference is less than the desired base Output the intermediate difference when the intermediate difference is less than the desired base, and generates a borrow signal to be input to the first logic circuit for subsequent character subtraction operations, the intermediate difference being And a second logic circuit for generating a no carry signal when greater than or equal to the desired base. 29. The data system of claim 28, wherein each symbol is selected from the group comprising a string of numbers, words, characters, signs, strings representing encoded data, strings of characters and numerals representing encoded data.