SU408305A1 - DEVICE FOR EXTRACTING SQUARE ROOT - Google Patents

Description

one

The invention relates to computing and is intended for use in electronic computers of sequential operation and, in particular, in electronic keyboard computers that perform the operation of multiplying and working them in the decimal number system.

Square root extraction devices are known that use a method based on properties of a number of odd numbers.

However, in known devices, when calculating a square root, only one adder and three operational registers are used. Therefore, the number of elementary addition cycles required to determine the next bit of the result is at least twice the digit of this bit.

The aim of the invention is to increase the speed of the device and reduce the amount of equipment.

For this, the device contains an additional adder, the inputs of which are connected to the output of the first operational register and to the root calculation unit, and the output respectively to the inputs of the inverter unit and the circulation unit, the output of which is connected to the input of the first operational register,

the output of the second operational register is connected via an inverter unit to the input of the adder, the second input of which is connected to the output of the inverter unit, the output of the adder is connected to the input of the second operational register and the input of the root calculation unit, the other inputs of which are connected respectively to the outputs of the sign unit, the second comma unit, counter and additional

adder, the output of the calculation unit of the root is connected to the input of the first comma unit, the multiplication unit, the inverter units and the second operational register.

In addition, the root computing unit contains a blocking circuit, the output of which is connected to the definition circuit of the comma, the output of the definition circuit of the computation is connected to the input of the add-on control circuit, the output of which is connected via the circuit

control of the auxiliary register with the inputs of the auxiliary register, the second output of the control circuit of addition - subtraction is connected to the input of the circuit of formation of a constant.

The invention is illustrated in the drawings.

FIG. 1 shows a block diagram of the device; in fig. 2 - functional block diagram of the calculation of the root. Square ejector

The root contains operational register 1, up to 3 additional adder 2, circulation unit 3, operational register 4, block of inverters 5, adder 6, block of inverters 7, blocks occupied 8, 9, block of sign 10, calculation block, root P, counter 12 , block multiplying; 13.5 The device operates as follows. We assume that the numbers are represented in binary-decimal code with an excess of three with a natural comma, so that the operational register is used to store the digital part of the number, and the occupied block is made in the form of a counter for storing the position of the comma. Consider first the circulation circuits of the information-15 formation under the assumption that only two operational registers are used. When information is circulated in the operational register 1, the next decimal bit from the output of the register enters the additional-20 adder 2. From the output of the adder 2, information enters the circulation unit 3, from where it is fed to the input of register 1. When information is circulated operational register 4, the next decimal bit from the output of the register 25 enters the inverter unit 5, from where it is fed to the adder 6. From the output of the adder 6, information enters the register 4. When you add or subtract, information is circulated in both operational re-30 gistrah 1 and 4, and from the output of the additional adder 2, the information enters the inverter block 7. Depending on whether addition or subtraction is done from the output of the block 7, the information in the forward or rev 35 code is fed to the input of the adder 6, and to form an additional code to adder 6 is added to "1. As a result, in register 4, a sum or difference is formed.40 Let register 1 and the corresponding block of comma 8 be reset to zero (do not contain information), and the initial number (root expression) is stored in register 4 and in the corresponding block of comma 9. The sign 45 of the original number is stored in the sign block 10. Consider the general interaction of the blocks of the device when extracting the square root. First, the position of the initial result number is determined from the position of the original number in the block of comma 9 in the block of commander 850. Then subtraction is started, and at the appropriate time from the calculator root 11 to the additional adder 2 enters "1, as a result of which from 55 the highest bit or two high bits of the number in register 4 is subtracted" 1 and in register 1 is entered "one. During the next subtraction cycle, the accumulator 11 enters the adder 2 from the computation block 2,60, as a result of which 3 is subtracted from the register 4 and 3 is formed in the register 1. On further subtraction cycles, the adder 2 from block I receives 2 until a signal of no transfer arrives from the adder 6 to the calculator core-65 4. In this case, the addition is started, and the input of the additional adder 2 from the calculation unit of the root 11 does not receive information. As a result, the residue is restored with a simultaneous shift of the contents of register 4 by one bit to the left. At the same time, from block I is sent “1” to counter 12, which determines the time of generation in block 11 of the corresponding code for submission to adder 2. After this, the subtraction process starts again, and in the first cycle when entering “1 into” The number k is subtracted. "1 from the bit number + 1. At the end of the process in register 1, a double root value is formed. To obtain the final result, a constant of 0.5 is generated in register 4 and multiplication unit 13 is started. Obviously, this takes less time than dividing by. As a result, in register 4, the desired square root value is obtained. The essential difference of this device is that in one subtraction cycle in operational register 1 the sum of the previous number is formed with "2, and in register 4 - the difference between the previous contents of register 4 and the new contents of the register, 2. Let us consider in more detail the process of calculating the square root, assuming that a four-bit binary combiner type is used as an additional adder 2. The signal "Root on input 14 (see Fig. 2) triggers blocking circuit 15. If on output 16 of the block of character 10, a signal is received that the number in register 4 is less than zero. then output 17 starts the output and further execution of the operation is blocked. If the sign is positive, then register 1 and block 3 are started on output 18 to circulate information in register 1 and block 9, and the bus 19 is started via bus 19. 20 are received at the input 21 of the signal from the block 9 and at the input 22 - even clock pulses (bit) from the clock device (not shown). The circuit 20 provides the generation of pulses, which at the output 23 are fed to the counting input of the block 8, as a result of which in the latter the position of the comma of the double root value is formed. Let, for example, the 16-bit number be located in the 19-bit register in such a way that the most senior (19th) bit and two of the youngest (1st and 2nd) bits are free. Then the signal from circuit 20 at output-24 starts the counter 12 in such a way that the pulse from its output corresponds to the 17th bit. If the number of digits located to the left of the comma is even, then the circuit 20 sends an additional one pulse to the comma 8 block at output 23 and counter 12 at output 24, with the result that the pulse from counter 12 will correspond to the 16th discharge Thereafter, the addition / subtraction control circuit 26 is started up via bus 25. Subsequently, blocks 8 and 9 do not participate in the process of determining the doubled square root value, and block 9 is reset to zero, and block 8 stores the position of the com- plete doubled root value.

Circuit 26, at output 27, triggers register 4 and block 5 to circulate the information in register 4 and at output 28, the reverse code in inverter unit 7 for subtraction. At the same time, the auxiliary register control circuit 30 is started up via bus 29. The signal from counter 12 to input 31 is fed to circuit 30, as a result of which the latter, via bus 32, enters auxiliary register 33 with code 0100 (constant 1 in code 8421-3). Auxiliary register 33 consists of four triggers. The entry of code 0100 is performed according to T4 clock, and the device uses eight T clock cycles: from G1 to T8. Since register 1 does not contain any information at the initial time, the inputs of additional adder 2 are fed from register 1 to code 0000 and from auxiliary register 33 to code 0100 on output 34. As a result, in block 3 and in inverter unit 7 T1 (valveing is performed directly in blocks 3 and 7) the code 0100 is received (the digit " 1).

Let the pulse from counter 12 first correspond to the 16th bit. If the 19 bits of the register correspond to the 19 clock pulses A (from A1 to A19), then the code 0100 is written to the auxiliary register 33 in the 74L16 cycle, and in blocks 3 and 7, the code 0100 is received in G1L17. As a result, the digit “1 in the 17th register bit 1 and subtraction“ 1 from the register 4 is recorded. In addition, in G4L17, circuit 30 generates an OOP code and enters it in auxiliary register 33 on input 31. As a result, 1 by TlAlS, the OOP code (code zero) is entered, which is necessary in connection with the possibility of transfer during the following cycles from the 17th to the 18th digit of the register 1. The OOP code will occur only. When using code 8421-3 and only in the 18th or 19th bits of the register 1. In this case, the work cycle lasts from to G8L19

In the future, to the 17th bit of register 1 it is necessary to add the digit "2, and there may be a transfer to the next (18th) bit.

In order to add the contents of the 17th bit to the number 2, the AOR scheme works as follows.

According to G4L16, the code 0100 is entered into the auxiliary register 33. The auxiliary register 33 is reset by a constant clock pulse T2 and the lower bit of the register (1st bit), the next bit code is also entered in 72, because the operational registers 1 and 4 are shift registers. Then, when adding the contents of the 17th bit of register 1 and code 0100, there may be two cases depending on the presence or absence of transfer from the additional adder 2. Suppose, for example, in the 17th bit of the register

1 is the digit "9" (code 1100). Then, when adding the codes 1100 and 0100, a transfer is formed, which on the bus 35 through G5L16 enters the auxiliary register control circuit 30, where it is stored on a special

trigger According to G6L16 from circuit 30, an additional reset of auxiliary register 33 is performed via bus 36. According to G7L16, circuit-30 generates code 1000 and sends it to auxiliary register 33 via bus 31. When adding codes 1100 and 1000, code 0100 is generated in additional adder 2 (digit 1) and transfer to the next bit. This transfer signal is not used anywhere, since a special trigger in circuit 30 already stores

transference. Then, by the circuit 30, the auxiliary register 33 is dropped on the bus 36 and on T4A17, the code 0001 enters the auxiliary register on input 31. As a result, the number 11 in the register 1 is formed

and 11 is subtracted from the contents of register 4. Let, for example, the 17th digit of the register 1 contains the number 5 (code 1000). Then, when adding the codes 1000 and 0100, the transfer is not formed. Along G6L16, auxiliary register 33 is cleared, and by T7L16, circuit 30 generates code 0010, which is fed to input auxiliary register 33 at input 31. When the codes 1000 and 0010 are added, additional code 2 forms code 1010 (digit 7).

This process continues until, as a result of the next subtraction in register 4, a negative number is obtained.

Then from the adder 6 to the circuit 26 control the addition - subtraction on the bus 37 receives a signal of no transfer; in the next cycle, the circuit 26 on the output 28 suppresses the reverse code in the inverter unit 7 and starts

it's got my code in it. In the cycle of addition, the contents of register 4 are shifted by one bit to the left, and in counter 12 but output 38 is added, "1, as a result of which the pulse from this counter will be

correspond to bit 15, and in register 4, the positive balance is restored. Then the circuit 30 at the input 31 enters into the register 33 the code 0100 according to the cycle 74Л15, as a result of which in the 16th bit of the register 1 it is entered "1.

In addition, by 74Л16 circuit 30 at input 31 enters the auxiliary register 33 with the code 1111, and in the additional adder 2, adding adds a transfer to the next bit, which is blocked in the circuit

30 auxiliary register management,

As a result, "1." Is subtracted from the contents of the 17th bit of register 1.

After that, the whole process is repeated until the signal to the circuit 26 via bus 37 is not received again for the absence of transfer from the adder 6. Then the restoring again occurs (addition cycle), the counter is shifted 12, and so on. The 1 st bit subtraction of "1 from the contents of the 2 nd bit of register 1 is performed simultaneously with the addition cycle, so that as a result of the addition, no residue is recovered. Thereupon, the process of determining the doubled quadratic root value is completed and the addition control circuit 26 — subtraction over bus 39 starts the constant formation circuit 40.

The constant formation circuit 40, first of all, at output 41 resets the register 4 and sets the constant “0.5. In addition, the circuit 40 checks for the presence of a significant digit in the 18th bit and, if it is not present, shifts left one digit in the register I and its comma in block 8 to output 42. Then, output 43 starts the multiplication unit 13 After performing the multiplication operation in register 4, the desired value of the square root appears, and in block 9, its comma-separated position.

Thus, it takes a maximum of 10X16,160 cycles to obtain a doubled root value. (All numbers are equal to the root "9). Multiplication by 0.5 may require no more than 50 cycles. All in all, square root extraction is not required. more than 210 cycles.

Subject invention

Claims (2)

I. A device for extracting a square root containing operational registers. inverter units, adder, circulation unit, root calculation unit, multiplication unit, commanding units, sign unit and counter, characterized in that, in order to increase speed, it contains an additional adder, whose inputs are connected to the output of the first operational register and the root computing unit, and the output, respectively, with the inputs of the inverter unit and the circulation unit, the output of which is connected to the input of the first operational register, the output of the second operational register, via the inverter unit, connected to the input of the adder, second input of which is connected to the output of the inverter unit, the output of the adder is connected to the input of the second operational register and the input of the root calculation unit, the other inputs of which are connected respectively to the outputs of the sign unit, the second the unit of the com pies, the counter and the additional adder, the output of the computation unit of the root is connected to the input of the first unit of the comma, the multiplication unit, the blocks of inverters and the second operational register. 2. The device according to claim 1, characterized in that, in order to reduce the amount of equipment, the root calculation unit comprises a blocking circuit, the output of which is connected with the definition scheme of the comma, the output of the definition scheme of the comma is connected to the input of the control circuit of addition - subtraction, the output of which is connected through the control circuit of the auxiliary register to the inputs the auxiliary register, the second output of the addition control circuit — the subtraction — is connected to the input of the constant formation circuit. 0 /five t --- T 16P