SU1104508A1 - Dividing device - Google Patents

Abstract

A DELIVERY DEVICE containing a control block, a private register, a counter, an adder, a residual register, a divider register, characterized in that, in order to improve speed, a memory block, an adder reading counter, a subtracting counter, a multiplier block, and a control block are entered into it contains eight D triggers, two OR elements, four STI elements, three AND elements, two NO elements, three delay elements, we take the input of the initial installation of the device connected to the installation input of the first O-trigger, with the reset inputs from the second to the seventh D trigger of the control unit; the device start input is connected to the first input of the first OR element of the control unit; the device clock input is with the clock inputs of all D triggers of the control unit; the direct output of the first D trigger of the control unit is -OR, the output of which is connected to the information input of the second D-trigger, the direct output of which is connected to the first input of the first OR element and, through the first delay element, to the information input of the third D trigger, the direct output of which is inen with the first inputs of the first and second elements AND, with the first inputs of the second and third elements OR, the direct output of the fourth D-flip-flop is connected to the first input of the fourth element OR, with the third input of the first element AND-PI, with the first input of the second element I-STI, the output of which is connected to the information input of the first D-trigger, the direct output of the fifth D-trigger, is connected via the second delay element to the information input of the sixth ffl D-flip-flop, the direct output of which is connected to the second input of the second: element OR, with the second in This is the fourth input of the first element OR, the first input of the third element AND, the output of which is connected to the information input of the seventh O-trigger, the direct input of which is connected to the second input. the third element of the ShZh, the third inlet 00 of the first element OR, and through the third delay element - with the information input of the eighth D-trigger, the direct output of which is connected to the fourth input of the first AND-OR element, the third input of the second AND-OR element. the fourth, fifth and sixth inputs of the second AND-OR element are connected to the input of the first element NOT, the output of which is connected to the fifth, sixth inputs of the first AND-OR element, the second input of the third AND element, information

Description

The first input of the first D trigger is connected to the output of the second element I, the second input of which is connected to the output of the second element NOT, the input of which is connected to the second input of the first element I, the output of which is connected to the information input of the fourth D flip-flop of the control unit the output of the third D trigger, which is coefimf with the addition input of the totalizer 15% of the subtractor, the input of which is connected to the subtraction input of the subtracting counter and the direct output of the fifth D trigger of the control unit, the output of the fourth element OR of which is connected to the input of a private register entry whose reset input is connected to the forward output of the eighth O-trigger of the control unit, the input of the first element NOT of which is connected to the counter output, the reset input of which is connected to the forward output of the first P-trigger of the control unit, output of the third element OR which is connected to the information input of the counter, the output of the sign bit of the remainder register is connected to the input of the second element NOT of the control unit the output of the first element OR which is connected to the shift input of the private register, the write input to A reading counter of 1 08 is connected to the forward output of the second L-trigger of the control unit, the outputs of the I / 2 most significant bits of the remainder register (n is the size of the operands) are connected respectively to the inputs of the first group of the memory block, the inputs of the second group of which are connected respectively to the P / 4 older bits of the register of the divider, the outputs of the P bits of which are connected to the corresponding information inputs of the block of multipliers, the control input of which is connected to the output of the subtracting counter, the outputs of the block of multipliers with the corresponding and inputs of the adder, the outputs of which are connected respectively to the information inputs of the first group of the adder-subtractor, information inputs of the second group of which are connected respectively to the outputs of the register of the remainder, the information inputs of which are connected respectively to the outputs of the adder-subtractor, information inputs of the First group of which are connected respectively to the outputs And the bits of the divider register; the input of the register of the remainder is connected to the output of the second OR element of the control unit.

The invention relates to digital computing and can be used in the construction of arithmetic devices of high-speed digital computers with severe limitations on the physical characteristics and power consumption. A device for dividing is used, which implements the hardware method of the second order of dividing binary NUMBERS, containing the dividend register, the divisor register and horizontal rows of one-bit adders with elements at the inputs 2I-OR l. A disadvantage of this device is great complexity. The closest to the invention to the technical essence is a device for dividing, containing a control unit, a private register, a counter, an adder, a register of the remainder, a divider register 2j. A disadvantage of the known device based on the implementation of the logical and instrumental first order of methods for accelerating the division, is the large time of execution of the division operation. The purpose of the invention is to increase its speed. This goal is achieved by the fact that a memory unit, a divider register, a memory block, an adder-subtractor are entered into a dividing device containing a control unit, a private register, a counter, an adder, a residual register, a divider register. 3 subtractive counter, multiplier unit and control unit contains eight D-flip-flops, two AND-OR elements, four OR elements, three AND elements, two NOT elements, three delay elements (and the input of the initial installation of the device is connected to the installation input of the first D-trigger, from the reset inputs from the second to the eighth D triggers of the control unit, the device start input is connected to the first input of the first AND-OR control unit, the clock input of the device with clock inputs of all D-trigger control unit, the first output D-thrigge The control unit has the second input of the first ORI element, the output of which is connected to the information input of the second D-trigger, the direct output of which is connected to the first input of the first OR element and, through the first delay element, to the information input of the third D trigger, whose direct output connected to the first inputs of the first and second elements AND, the first inputs of the second and third elements OR, the output of the fourth D-trigger directly to the first input of the fourth element OR, and the third of the first element AND-OR to the first input of the second The AND-OR element whose output is connected to the information input of the first D-flip-flop, the forward output of the second Rtrigger is connected via the second delay element to the information input of the sixth D-Trigger, the direct output of which is connected to the second input of the second OR element, with the second input of the fourth OR element, with the second input of the second AND-OR element, the second input of the first OR element, the first input of the third AND element, the output of which is connected to the information input of the seventh O trigger, whose direct output is connected to the second input of the second OR element, the third input of the first OR element and the third delay element - with the information input of the eighth P trigger, the direct output of which is connected to the fourth input of the first AND-OR element, the third input of the second AND-OR element, the fourth, the fifth and the sixth inputs of the second element AND-OR are connected to the input of the first element NOT, the output of which is connected to the fifth, sixth inputs of the first element 08 AND-OR, the second input of the third element AND, the information input of the fifth D trigger connected to the output of the second element AND, second entrance which is connected to the output of the second element NOT, the input of which is connected to the second input of the first element I, the output of which is connected to the information input of the fourth D-trigger of the control unit, the direct output of the third D-trigger of which is connected to the addition input of the adder-subtractor whose input connected to the subtraction input of the subtracting counter and the direct output of the fifth D-trigger of the control unit, fourth output. The first OR element of which is connected to the input of a private register entry, the reset input of which is connected to the direct output of the eighth D-trigger of the control unit, the input of the first element NOT of which is connected to the output of the counter, the reset input of which is connected to the direct output of the first D-trigger of the control unit , the output of the third element OR of which is connected to the information input of the counter, the output of the sign bit of the remainder register is connected to the input of the second element NOT of the control unit, the output of the first element OR of which is connected to the input of the output hectare of private register, the input of the record of the subtracting counter is connected to the direct output of the second D-trigger of the control unit, the output of the P / 2 most significant bits of the register of the remainder (P-bit operand) are connected respectively to the inputs of the first group of the memory block, the inputs of the second group which are connected respectively to the outputs of the 4/4 bits of the register of the divider, the outputs of the bits of which are connected to the corresponding information inputs of the block of multipliers, the control input of which is connected to the output of the detracting counter, the outputs of the block multipliers with the corresponding inputs of totalizer. ra, the outputs of which are connected respectively to the information inputs of the first group of the adder-subtract, the information inputs of the second group of which are connected respectively to the outputs of the residue register, whose information inputs are connected respectively to the outputs of the adder-subtractor, information inputs of the first group of which are connected respectively to the outputs of r-rows the register divider, the input of the record of the register of the remainder is connected to the output of the second element OR of the control unit. FIG. 1 shows a block diagram of a dividing device; in fig. 2 - state transition graph of the automaton; in fig. 3 is a control block diagram. The device contains a residual register 1, a divider register 2, a private register 3, an adder-subtractor f, a counter 5, a multiplier block 6, a subtractive counter 7, a memory block 8, an adder 9, multiply 10 multi-bits, a control block 11. The control unit 11 is in the form of an automatic machine on the register with the unit being moved. The transition graph of the states of the automaton is denoted by the A, i 0/1/7 states of the automaton, the transition conditions are indicated on the arcs. The control unit 11 (FIG. 3) contains D-triggers 12-19, elements AND-OR 20 and 21, elements AND 22-24, elements OR 25-28, elements NOT 29 and 30, elements 31-33 of the delay. In control block 11, the input bit 34 receives a digit from the remainder register 1, output 35 is the summation input of subtractor 4, output 36 is the information input of counter 5, output 37 is the reset input of counter 5 ,. input 38 is the output of counter 5, output 39 is the input of register 3 private, output 40 is the zero register input of private 3, output 41 is the subtraction output of counter-subtractor 7 and from subtractor 4, output 42 is output register shift 3 quotient, output 43 is the input of the record of the counting subtractor 7, input 44 Start, output 45 is the input of the recording of the rest 1 register, input 46 Initial setting, clock input 47. The automaton is based on eight triggers 12-19 with asynchronous S and R inputs. The external signals of the device in the signal are Start and Initial Settings - clock. For definiteness, we assume that the multipliers are 10 four-bit. In this case, in register 2, the divider in the initial state is normalized on a binary basis, and 1–4 bits of the register 2 divider are connected to the address input of the memory block 8, and the firmware of the memory block 8 is made taking into account that the contents of the highest zero bit are yes equal to one. This achieves the accuracy of the division operation when implementing the accelerated division algorithm. The address inputs of the higher bits of the memory block 8 are connected to eight (in the case of 4-bit multipliers) high bits of the 1 register of the remainder, which is used to store the initial dividend, and subsequently the next remainder. The adder-subtractor 4 is designed to subtract from the next balance (the contents of register 1 of the balance) of the partial division of the divider by the next private digit formed in the adder-9, as well as to add (if the next balance is negative) to the contents of register 3 private register 2 divider. Register 2 is a divider and register 3 is a private shift, and shifts in them are made by the number of bits equal to the multiplier 10. Counter 3 is designed to count the number of multiplications, which is equal to the number of (divisible) divisions by the multiplier 10. So For example, for 40-bit mantis and 4-bit multipliers, the maximum number of multiplications is ten. The width of the counter 5 or the addition code is chosen in such a way that the appearance of a unit in the high bit means the completion of the division operation. The purpose of the remaining functional elements coincides with their name. The device works as follows. In the initial state in register 2, the divisor contains a dividend, in register 3 private a normalized checker, registers 3 private and counter subtractor 7 are reset, counter 5 is in its original state (reset or an addition code is written to it). On the Start signal, signifying the beginning of the division operation, the automaton goes from state A to state A. In this case, by the values of the higher digits of the divider and the dividend, coming from registers 1 and 2 to the address inputs of memory block 8, into the counter the highest digit of the number is recorded. In block 6 of multipliers, the divisor is multiplied by the highest digit of the quotient and the product is formed in adder 9. The product thus obtained in subtractor 4 is subtracted from the dividend and the result is entered in register 1 of the residue, shifted by four bits to the left as the next residue. The contents of counter 5 are incremented by one. In the event that the next balance obtained in this way is positive, the automaton goes to state 3. The highest digit of the quotient from the subtractor 7 is entered into the register 3 of the quotient. Next, the automaton enters the state AJ, similarly to the above, the next digit of the private and the next balance are formed until the occurrence of the MF signal, which means the end of the division operation.

If, on a yakom-dividing step, the next remainder turns out to be negative, then the automaton from state A goes to state Ax. This means that the next private figure, due to its approximate approximation, is one unit larger. Therefore, in this state of the automaton, this figure is reduced by one and the contents of register 2 of the divider are added to the contents of register 1 using subtractor 4. This adjusts the number and quotient. The next private digit is entered in register 3 private. The formation of a negative next residue means that

the next digit is a private zero. Therefore, if FST, then the automaton enters the state Ag, where the contents of counter 5 is increased by one, the contents of register 3 are shifted to the right, and then the digit zero is entered into the private tetrad of register 3. If / SCT, the automaton enters state A and the division operation continues in the same manner as described fy, otherwise the automaton enters state Hell, which means the end of the operation.

Note that if the next balance is non-negative, then the time to calculate the hexadecimal digit of the private i i, i 2 where t, is the transition time A, - A, i is the duration of the crust cycle. In the case when the next balance is negative, the time for calculating the two successive hexadecimal digits of the quotient. , where ij transition time A - A.

Assumed to obtain negative and non-negative residuals by events of equal magnitude, the average time of division, with accepted assumptions, reduced to one binary digit, is equal to

(2i ,.

in a known device, it is natural to assume that the average dividing time, reduced to one binary point, is not less than (t, -v 2L) 1/3. Therefore, the speed of the proposed device more than the speed of the known device is not less than 1.5 times.

Thus, the invention allows to reduce the execution time of the division operation by at least 1.5 times.

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Claims (1)

A DIVISING DEVICE containing a control unit, a private register, a counter, an adder, a remainder register, a divider register, characterized in that, in order to improve performance, a memory unit, an adder-subtractor subtracting a counter, a multiplier unit are introduced into it, and the control unit contains eight D-triggers, two OR elements, four OR elements, three AND elements, two NOT elements, three delay elements, we accept the initial installation input of the device is connected to the installation input of the first D-trigger, with reset inputs from the second to the eighth D igers of the control unit, the start input of the device is connected to the first input of the first OR element of the control unit, the clock input of the device is with the clock inputs of all D-triggers of the control unit, the direct output of the first D-trigger of the control unit is with the second input of the first AND-OR element, output which is connected to the information input of the second D-trigger, the direct output of which is connected to the first input of the first OR element and through the first delay element to the information input of the third G trigger, the direct output of which is connected to the first the odes of the first and second AND elements, with the first inputs of the second and third OR elements, the direct output of the fourth D-trigger is connected to the first input of the fourth OR element, with the third input of the first AND-OR element, with the first input of the second AND-OR element, the output of which connected to the information input of the first D-flip-flop, the direct output of the fifth D-flip-flop q is connected through the second delay element 9 to the information input of the sixth D-flip-flop, the direct output of which is connected to the second input of the second OR element, with the second input of the fourth element OR, with the second input of the second AND-OR element, the second input of the first OR element, the first input of the third AND element, the output of which is connected to the information input of the seventh D-trigger, the direct output of which is connected to the second input of the third OR element, the third input of the first OR element and through the third delay element, with the information input of the eighth O-trigger, the direct output of which is connected to the fourth input of the first AND-OR element, the third input of the second AND-OR element. the fourth, fifth and sixth inputs of the second AND-OR element are connected to the input of the first NOT element, the output of which is connected to the fifth, sixth inputs of the first AND-OR element, the second input of the third AND element, the information input of the fifth D-trigger is connected to the output of the second element And, the second input of which is connected to the output of the second element NOT, the input of which is connected to the second input of the first element AND, the output of which is connected to the information input of the fourth Г-trigger of the control unit, the direct output of the third Г-trigger of which is connected to the input m is the sum of the subtractor, the subtraction input of which is connected to the subtraction input of the subtracting counter and to the direct output of the fifth D-trigger of the control unit, the output of the fourth element OR of which is connected to the input of the private register record, the reset input of which is connected to the direct output of the eighth D-trigger of the control unit, the input of the first element which is NOT connected to the output of the counter, the reset input of which is connected to the direct output of the first A-trigger of the control unit, the output of the third element OR of which is connected to the information m is the counter input, the output of the sign discharge of the remainder register is connected to the input of the second element NOT of the control unit, the output of the first element OR of which is connected to the shift register input of the private one, the write input of the subtracting counter is connected to the direct output of the second Г-trigger of the control unit, outputs I / 2- the highest bits of the remainder register (η is the capacity of the operands) are connected respectively to the inputs of the first group of the memory block, the inputs of the second group of which are connected respectively to the outputs And / 4 of the senior bits of the divider register, the outputs P the discharges of which are connected to the corresponding information inputs of the block of multipliers, the control input of which is connected to the output of the subtracting counter, the outputs of the block of multipliers are connected to the corresponding inputs of the adder, the outputs of which are connected respectively to the information inputs of the first group of the adder-subtractor, information * the inputs of the second group of which are connected respectively to the outputs of the remainder register, the information inputs of which are connected respectively to the outputs of the adder-subtracter, the information inputs of the first group of which are connected respectively to the outputs AND bits of the divider register, the input of the remainder register record is connected to the output of the second OR element of the control unit.