SU881739A1 - Squarer - Google Patents

Description

(54) SQUARE

The invention relates to computing and can be used, in particular, as part of specialized computing devices for processing information about the progress of the pulp process according to the H-factor.

A known quadrant that contains a reference frequency generator, two binary counters, one of which controls the operation of another counter covered by feedback and connected to the output of the generator through a valve controlled by a trigger, through a delay line with an output the first counter. This scheme is based on the use of the fact that the second difference of the function y is equal to two, as well as on the conversion of the code into the number of pulses 1.

However, the presence of delay lines reduces the accuracy of the device. Before starting work, initial numbers must be entered into the counters, the choice of which is ambiguous (the first {1 detector must enter -1, that is, start all the units, and the second counter - 1, .. unit to the least significant bit), except Togo,

the frequency of the generator must be large enough for the time between the two input pulses to pass a packet of pulses, the largest number of which is 2.

The closest in technical essence to the proposed is a quad, containing a pulse generator, two counters, a comparison circuit, the output of which is connected to the trigger input, element I. In addition, the device contains an additional trigger (2.

ten

This device is not inherently high accuracy.

The purpose of the invention is to improve the accuracy of the calculation.

The goal is achieved by the fact that

Quadrator 15, containing a pulse generator, two counters, a comparison circuit, the output of which is connected to the trigger input, And element, is introduced a controlled frequency divider, the output of which is connected to one of the inputs of the And element, the second input of which is connected to the inverse output of the trigger, input installation of which is connected to the output of the first counter, the input of which is connected to the output of the last bit of the controlled frequency divider, the input of which is connected to the output of the pulse generator, the first and second groups of inputs of the comparison circuit are connected the bit outputs of the first and second counters, respectively, the input of the last of which is the information input of the device; the bit outputs of the second counter, starting with the first bit, are connected to the control inputs, starting with the last bit of the controlled frequency divider, and the output element is the output of the device.

The drawing shows a diagram of the quad.

The quadrator contains a pulse generator 1, a counter 2, a trigger 3, an AND 4 element, a controlled frequency divider 5, a register 6, and a comparison circuit 7. The output of generator 1 is connected to the input of controlled frequency divider 5, the control inputs of which are connected to outputs of register 6 in such a way that the low-order bit of register 6 is equal to the high-order bit of the frequency divider 5, the output of the last bit of the frequency divider 5 is connected to the input binary bit 2, and the total output with one of the inputs of element 4, the second input of which is connected to the output of flip-flop 3, the S input of which is connected to the output of comparison circuit 7, whose inputs are connected bitwise with the bit outputs of register 6 and counter 2, output n The last bit of which is connected to the R input of trigger 3.

The principle of operation of the device is as follows.

Capacities of the controlled divider 5 frequency, register 6 and binary counter 2 are equal to 2. Therefore, if the number X is recorded in register 6, then the total output of the divider 5 produces the frequency

AND)

X -1T

where Q is the oscillator frequency 1.

Pulses are received at the input of counter 2, the frequency of which is 4 ° / 2.

Upon arrival at the input of the counter 2, the number of pulses equal to the number x recorded in the register 6, the output of the comparison circuit 7 produces a signal that sets the trigger 3 to the unit state via the S input. The overflow pulse of counter 2 (2nd pulse) sets trigger 3 to the zero state (at the R input). A new quad cycle begins.

Thus, at the inverse output of trigger 3 there is a level 1 from the beginning

cycle until the moment the pulses of frequency fg / 2 enter the input of counter 2. The duration of this level

Ha

(2)

- s

Since one input of the element AND 4 receives the frequency y, the value of which is determined by the expression (1), then during the time when the second input of the element AND 4 has a level 1, the number of pulses appears at its output

.x-a

 X (E)

sj g, t - o. -h-

The proposed device does not contain delay lines, and the analysis of expression (3) shows that the instability of the frequency of oscillator 1 does not affect the accuracy of operation, since this instability equally affects the numerator and denominator of expression (3).

The value of f affects the speed of the device and depends only on the speed of the elements that implement the proposed scheme.

Claims (2)

1. USSR author's certificate number 113563, cl. G 06 F 7/38, 1957. 2. USSR author's certificate number 607215, cl. G 06 F 7/38, 1976. fo 7