SU377785A1 - DIGITAL SMOOTHING DEVICE - Google Patents

Description

one

The invention relates to the field of computing and measuring technology and can be used to smooth and center random processes.

Known digital smoothing devices containing a smoothing unit consisting of a puncturing adder connected to a register have a low smoothing accuracy.

The aim of the invention is to improve the accuracy of smoothing and expanding the functionality of the device.

To achieve this goal, it contains an additional accumulating adder, whose inputs and the lower-order bits are connected to the outputs of the inverse register code and the corresponding n inputs of the device, and from the high-order and sign bits to the sign input of the device and with the output of the inverted code of the sign bit register. Outputs of the direct code of the higher bits of the adder are bitwise connected to the corresponding inputs of the lower bits of the accumulating adder of the digital smoothing unit, and the output of the direct code of the sign bit of the adder to the inputs of the older and sign digit of the adder smoothing knot. The outputs of the direct register code are connected to the outputs of the device.

In drawing 1 shows a block diagram of the device.

It contains the inputs /, the additional accumulating adder 2, the device input 3, the device outputs 4, the accumulating adder 5, the device input 6 and -digit register 7. The capacity of the accumulating adder 5 -.

In the device under consideration, a digital algorithm is implemented in the form of a recurrent

1 well

- (";) -" .-- I

(one)

, +

TO,

where Xi is the current sampling of the input process,

ar is the current discrete of the smoothed process, moreover ai ao 0, and Agmax

 2 ".

Xi, fnp, 7 (2 G2 / pr fnp - input frequency input samples,

T, 272 T V2, where G is the selected smoothing interval.

The transfer function of the device in question is

K (p) / iC, (p) - / “p)

(3)

l + k, (p) (p)

30 where Ki (p) is the transfer function of the integrator, LR) is the transfer function of the 1st order aperiodic link. Taking into account relations (3) and (4), we have + 1 which corresponds to a Butterworth II order operator with an amplitude-frequency characteristic of the form () WTTfT / 1 - | - and a phase-frequency characteristic. p (co) arctg 1 - 0.37-2 The determination of the current discrete values of the smoothed process is performed in a cycle consisting of four cycles. Consider the f-th cycle of the device. Let after the (r-1) -th cycle in the Sul.mators 5 and 5 and in the register 7 the codes of numbers (Xi - yii), KZ-OI-I and In the cycle t are fixed, through inputs 1 to the adder 2 the discrete J is fed , -. In the adder 2, the code of the number 2 is fixed (Xi - ar,) - {- XiIn tact / 2, input 5 is given a coma. Pulse that produces the issuance of the code of the ai-i number to OUTPUT 4 and rewriting the code of the number in the adders 2 and 5. In this case, in the adder 2 Ii-i, the code of the number 2 (r -; - a; -i) Е (l: (- -a (i) - | - (xi-at-i) is fixed, and in adder 5, the code of the number K2-ai-i-0.1-1. In the cycle / C, input 6 is given a pulse, resetting register 7 and rewriting the code of the number - 2 (; k; -a / i) from adder 2 to the sum Ki 1 0 torus 5, in which the code of the number 5 10 15 20 25 30 35 40 45 50 - a, Jf - L (xi - o.) is fixed. During the step t a pulse is applied to input 8 is performed census of number aj ai + i - {- ff- (i - -ii -) from adder 5, in registrar 7. The device’s cycle has terminated. The code for a, recorded in register 7, is outputted at output 4 in the next tz cycle (i + l) -ro cycle, which is carried out in the above-mentioned sequence. It should be noted that, if, then a direct code of the number a is output, and at the output of the direct code of the trigger of the register sign 7, the pulse does not appear, but if d is output 1) and the reverse code, and a pulse appears at the output of the direct code of the character trigger. In order to improve the accuracy of calculations, it is necessary to increase the size of the nodes of the device under consideration in the direction of lower bits. Subject of the Invention A digital smoothing device comprising a digital smoothing unit containing an accumulating adder connected to a register, characterized in that, in order to expand the functionality of the device, it contains an additional accumulating adder whose lower-case inputs are connected to the outputs of the inverse code the register and with the corresponding n inputs of the device, and the older ones and the sign bit with the sign input of the device and with the output of the inverse code of the sign bit of the register, the outputs of the direct code of the higher bits of the adder are bitwise connected to the corresponding inputs of the lower bits of the papcl: digital adder of the digital smoothing unit, and the output of the direct code of the sign bit of the adder to the inputs (t-I) of the old and sign digits The adder of the digital smoothing node, the outputs of the direct register code are connected to the output of the device.

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8 iH3

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