SU786031A1 - Device for determining error parameters of discrete communication channel - Google Patents

Description

And the third group is connected to the output of the multivibrator and the installation inputs of the elements And the second group. The outputs of the third divider are connected to the first inputs of the elements of the fourth group, the second inputs of which are connected to the first input of the second trigger and the output of the inverter. The output of the second trigger through serially connected multivibrator. And the inverter is connected to the first input of the third trigger, to the reset input of which the output of the decoder is connected and the output of the third trigger is connected to the first input of the additional element And the second input is combined with the second input of the second trigger and the first contact of the mode switch work, the second contact of which is combined with the inputs of the first time divider and the time counter. The output of the additional element I is connected to the first inputs of the shift register, to the second inputs of which the outputs of elements AND of the fourth group are connected, and the outputs of the bits of the shift register. To the inputs of the decoder.

The drawing shows the structural electrical circuit of the proposed device.

The device contains a phasing unit 1, a sensor 2 reference signals, a comparison unit 3, a 4 error counter, triggers 5, 6, 7, groups of 8-11 elements AND, a time counter 12, 13 distorted blocks counter, dividers 14, 15, 16, switch 17 mode of operation, the multivibrator 18, the inverter 19, the element And 20, the counter 21 of the grouping coefficient, the shift register 22 and the decoder 23.

The device works as follows.

The information signals using block 1, which extracts the synchronization combination from the incoming information, phase out the sensor 2. Block 3 performs a one-by-one comparison of the reference sequence received from sensor 2 with the input sequence. 4 The result of the comparison is the flow of errors that arrive at the trigger 5 and set it in a single state, as well as to the counter 4 to count the number of errors Pos in the measurement session. 8, the measurement session period, the switch 17 is in the position in which the clock pulses arrive at the inputs of the counter 12 and the divider 16, the counter 12 counts the number of binary elements arriving at the device during the measurement session (h). .

Divider 16 divides the measurement session into blocks of different lengths; at the output of divider 16, a signal coincides with the last pulse in a block of length b. With this signal, trigger 5 is set to the original

condition. Thus, at the output of flip-flop 5, a signal appears if during the passage of a block through at least one error signal.

Such blocks are called distorted, their number NOUJ counts counter 13. During a measurement session, counter 4 counts the number of erroneous elements of the input sequence, counter 12 the number of transferred elements, and counter 13 the number of distorted blocks of length C. The session ends with the switch 17 being switched to the position in which the trigger b jumps to the one state with the first clock pulse in one state, a dividing signal is generated from the leading edge of the output signal of the trigger b using multivibrator 18.

This signal enters the groups 8, 9, 10 and opens them. The states of all and bits of counter 4 through group 8 are transferred to dividers 14 and 15, the bits of counter 12 through group 10 are transferred to divider 14, the states of counter 13 through group 8 to divider 15, after which the process de sloth binary numbers. The result of dividing divider 14 is a binary number at its output, equal to the error rate Kosh.

V -JZ2HJ ()

w h

The result of dividing divider 15 is a binary number equal to the ° ° part. OIU / NOUJ.

With the trailing edge of the dividing signal, h: e, the inverter 19, the trigger 7 is set to one, the trigger 6 is reset, and group 9 is opened.

The binary number from divider 15 is transferred through group 10 to register 22, the output signal of trigger 7 opens AND 20, the clock pulses through it arrive at the input of counter 21 and simultaneously to the synchronization inputs of bit-register 22. The number set in register 22 begins to move along register 22 until all its bits are set to zero. The indicated state is fixed by the decoder 23. The output signal of the decoder 23 is fed to the Reset trigger 7 input and sets it to the initial state, the AND 20 element closes and the clock pulses no longer come in the register 22 and the counter 21. The number of clock pulses / incoming to the counter 21 during the time when the element AND 20 has been opened, it determines the value of the grouping factor Qi. This number in binary form is removed from the output of the counter 21.

The grouping factor cf is determined by the ratio

. . "NOU,

The number of register bits is 22, start- on the slice, which is occupied by the quotient Posh / Ld, is equal to the grouping coefficient eC multiplied by 10.

This number is equal to the number of clock pulses needed for release (register number 22, counts counter 21.

The proposed device has a high accuracy of determining the degree of error grouping.

Claims (1)

1. USSR author's certificate 351334, cl. H 04 L 11/08, 1972 (prototype).