SU892712A1 - Device for converting pulse trains into time intervals - Google Patents

Description

54) DEVICE FOR TRANSFORMING SERIES OF PULSES INTO TEMPORARY INTERVALS

I

The invention relates to a pulse technique, in particular, to information processing systems represented in a pulse number form.

A device is known for converting a series of pulses into time intervals containing waiting multivibrators, a counting trigger, logic elements 13.

However, this device is characterized by a low conversion accuracy and an insignificant range of pulse frequency variations.

The closest in technical essence to the present invention is a device for converting pulses into time intervals, containing counters of the reference "current numbers, the outputs of which are connected to the inputs of the coincidence unit, a two-bit shift register, two AND elements, a prohibition block and a trigger.

while the device input is connected to the input of the prohibition block and the clock input of the shift register, the reset input of which is connected to the output of the coincidence block, and the inverse output of the first cell is connected to the reset input of the reference number counter and the first input of the first element AND connected by its output to the input of the counter reference number, the second

to the input to the inverse output of the second cell of the shift register, and the third input to the clock pulse bus, to the clock input of the trigger and to the second input of the second

t $ of the element I, connected by its output to the input of the current count number, the second input to the trigger output, and the third input to the inverse output of the second cell

n the shift register and the control input of the prohibition unit, the output of which is connected to the reset input of the current number counter 23. However, in the known device, the leading edge of the output pulse is generated by the second pulse of the series, and the rear through two pulse intervals after the last pulse of the series. In the case of a minimum interval between the series, which is determined by the absence of one pulse in the sequence, the rear edge of the output pulse and the formation of the reset pulse coincide with the first pulse following the series, which causes the device to malfunction, causing a conversion error to one series pulse. The purpose of the invention .-. more accurate conversion. This goal is achieved by the fact that a device for converting a series of pulses into time intervals, containing counters of the reference and current numbers, whose outputs are connected to the inputs of the coincidence unit, and a trigger, whose input is connected to the clock bus and the counting input of the reference number counter, and the trigger output is connected to the counting input of the current number counter, additionally the first pulse exclusion block, three triggers, the control counter and the coincidence block, whose inputs are connected to the counter outputs, are added. the current number and counter of the control, and the output is connected to the reset input) of the exclusion unit of the first pulse, the counting input of which is connected to the bus of the pulse series and the counting input of the first additional trigger, the reset input of which is connected to the inverse output of the second additional trigger, the counting input of which is connected to the output of the first additional trigger and the enable inputs of the reference number counter and the control counter, whose counting input is connected to the counting input of the current number counter, the reset input to It is costly connected to the output of the first pulse exclusion unit and the counting input of the third additional trigger, the reset input of which is connected to the output of the main matching unit, and the output connected to the enable input of the current number counter and the output bus of the device. FIG. I shows the functionality of the device; Fig. 2 shows time diagrams that explain his work. The device contains triggers 1-4, block 5, exclusion of the first pulse, counter 6 of the reference number, counter 7 of the current number, counter 8 control, blocks 9 and 10 coincidence, bus 11 clock pulses, bus 12 series of pulses and bus 13 the output of the device. Bus I1 is connected to the counting inputs of the counter 6 and trigger 3, bus 12 is connected to the counting input of trigger 1 to the inputs of block 5, the output of which is connected to the counting input of trigger 4 and the reset input of the counter 7, the counting input of which is connected to the counting input of the counter 8 and output trigger 3, and allowing - with trigger output 4 and bus 13, enabling inputs of counters 6.8 are interconnected with trigger output 1 and counting input of trigger 2, the inverse output of which is connected to reset input of trigger 1, inputs of unit 10 are connected to outputs of counters 6.7, and out - with the reset input of flip-flop 4, the block 9 inputs connected to outputs of the counters 7,8, and the output from the block reset input 5. The apparatus operates as follows. In the initial state of the device {FIG. 1, the reset circuit is not shown) triggers 1-4, block 5 and counter 6 are in the zero state, and counter 8 is in the state of the counted unit. The first impulse of the series arriving at bus 12, trigger 1 is transferred to one state and enables counters 6 and 8 to count. Clocks of ff frequency from bus 1 I go to counting inputs of trigger 3 and counter 6. At the output of trigger 3, pulses with a frequency of fJ.-f (2, which arrive at the counting inputs of counters 7 and 8. Counter 6 calculates the clock pulses, and counter 8 pulses with a frequency before the arrival of the second pulse of the series, which flips trigger 1 to the initial zero state, closing the counters 6 and 8 to zero by potential A zero difference at its single output trigger 1 flips trigger 2, which, with zero potential, blocks trigger 1 at the reset input from its inverse output. The number of clock pulses n calculated by the counter 6 is proportional to the pulse duration in the series The number of pulses counted by the counter 8 (h | 2 + l). Such states of the counters 6 and 8 are maintained for the entire duration of the device operation.

The first impulse of the series is eliminated by block 5 (Fig. 2). The second and subsequent pulses of the series come from the output of block 5 to the counting input of the trigger 4, operating in the hold state, and to the reset input of the counter 7, setting it to the idle state. The second impulse of the series, transferring the trigger 4, starts forming the output impulse, arriving at the resolving stroke of the counter 7 and the output bus 13. The counter 7 calculates the impulses with the frequency f, In each interval it calculates p / 2 impulses and returns the initial impulse of the series from the output of block 5. At the end of a series of pulses (there is no pulse in the sequence), counter 7 continues to count. In the state of miscalculation (p / 2 + 1) of pulses, block 9 triggers a reset pulse for block 5, setting it to the initial state. When calculating the p-th pulse by the counter 7, the block 10 outputs a reset pulse for trigger 4, thereby filling the formation of an output pulse, the duration of which is proportional to the number of pulses in the series. The first impulse of the next series is eliminated by block 5, and the second resets the counter 7 to its initial state, and flips trigger 4, at the output of which the next output impulse begins to form. Since the pulse series are formed from a sequence of stable frequency pulses, the determination of the interval between the pulses in subsequent batches is not required (counter 6 retains its state), which eliminates the first pulses of subsequent batches, thereby eliminating the possibility of overlays and malfunctions devices.

When using the proposed device in coding systems, where it may be necessary to change the frequency of a pulse sequence, a so-called phase pulse (signal) is used to restore the device to its original state before each frequency change.

Claims (2)

1. USSR author's certificate number 457173, cl. H 03 K 5/00, 1973. 2.Avtdrskoe certificate of the USSR No. 653742, cl. H 03 K 13/20, 1979 (prototype). Yu L ID fig z one B H g I