SU390525A1 - DEVICE FOR MULTIPLICATION OF DECIMAL NUMBERS - Google Patents

Description

Known multiplier devices are operating with full-digit decimal numbers. In known devices, decimal multiplication is difficult to implement if acceleration methods using multiplicative multiples are used.

The aim of the invention is to save equipment.

The proposed device differs from the known ones in that decimal multiplication is accomplished by adding multiples of the multiplicand — doubled and (or) superimposed — without their preliminary preparation, or by introducing special corrections after addition. With such a construction scheme of the device does not require special registers for storing multiples of the multiplicand.

The invention consists in that one input of the binary addition signal formation circuit of the tetrads is connected to the binary addition signal bus, another input of it is connected to the output of the first NOT circuit with the first input of the tetrad binary addition signal formation circuit. and with the input of the binary addition signal generating circuit tetrad with a shift to the left by three bits; the third input of the binary addition signal forming circuit tetrad is connected to the second input

2

a binary addition tetrads signal shaping circuit with a left shift by one bit, with one tetrade analysis circuit input and a multiplicative register output; output of the binary addition signal formation circuit tetrads Connected to the primary input of the accumulating adder of partial products, the second input of which is connected with the output of the binary signal generation scheme

 a tetrad with a shift to the left by one bit, the third input of which is connected to the binary addition signal bus with a shift to the left by one bit and to the first inputs of the first, second and third schemes "And, the second

the inputs of which and the first inputs of the fourth, sixth, seventh and eighth circuits AND and the input of the first circuit are NOT connected to the correction signal formation bus; the third terminals of the first and second circuits “And are connected to one of the outputs of the tetrad analysis circuit, the other output of which is connected to the fourth input of the first circuit“ And and the second input of the sixth circuit “And, the third output of the tetrad analysis circuit is connected to the fourth

the input of the second circuit "And to the third input of the third circuit" P, the outputs of the first and second circuits "And connected to the inputs of the first circuit" OR, the output of which is connected to the third input of the accumulating adder of partial products, the fourth input of which is connected to the output of the binary signal adding a tet; happy with a shift to the left by three bits, the second input of which is connected to the bus of the register of the multiplicable preceding tetrad, and the third input is connected to the second mn inputs of the fifth, seventh and eighth circuits "And, with the input of the second circuit" NOT with w adding hydrochloric binary signal with a shift to the left by three digits; the second input of the fourth circuit “AND and the third input of the fifth circuit“ AND is connected to the fourth output of the tetrad analysis circuit, the fifth output of which is connected to the fourth input of the fifth circuit; the output of the latter is connected to the first input of the second circuit “OR, second, third and fourth inputs which are connected respectively to the outputs of the third, fourth and sixth circuits, the output of the second circuit OR connected to the fifth input of the accumulator of partial products, the sixth input of which is connected to the output of the eighth circuit the output of the second circuit is NOT connected to the third The third inputs of the fourth and sixth circuits "And, the fourth inputs of the third and sixth circuits" And connected to the sixth output cxej we analyze tetrads, the seventh output of which is connected to the third inputs of the seventh and eighth circuits, the eighth output of the analysis circuit of tetrads is connected to the fourth input of the eighth circuit "And The ninth output of the tetrad analysis circuit is connected to the fourth input of the seventh And circuit, the output of which is connected to the seventh input of the accumulating adder of partial products, the latter output is connected to another input of the tetrad analysis circuit.

The drawing shows a diagram of the device on one tetrad.

The device contains accumulating adder / partial products, register of multiplicable 2, tetrad analysis circuit 3, binary addition bus, binary addition signal bus 5 left-shifted by one bit, binary signal 6 bus left-shifted by three bits, signal bus 7 the formation of the correction, the circuit S of the formation of the signal of the binary addition of tetrads, the circuit 9 of the formation of the signal of the binary addition of tetrads with a shift to the left by one bit, the circuit 10 of the formation of the signal of the binary addition of tetrads with a shift to the left by three times On the other hand, the OR / Y formation of the correction by 6, the scheme I / 2 of the correction formation by 5, the scheme OR 13 of the formation of correction by 12, the scheme 14 of the formation of the correction by 11, the scheme NO 15 and 16 (correction inverters), schemes “And 17-22, bus 23 of the register of the multiplicable preceding tetrad.

Circuitry and correction blocks are used to form the correct decimal sum after binary addition.

Multiplication in the device is performed sequentially by each digit of the multiplier. To reduce the number of actions by one digit, add multiples of the multiplicand to the intermediate product: addition with double and with reduced multiplicand. The table shows the number of actions for each digit multiplier.

From this table it is clear that one digit

the average multiplier is 1.7 actions.

When multiplying two decimal numbers, the next multiplier of the multiplier is analyzed and, in accordance with the table,

a certain sequence of decisive actions: add, add with doubled multiplicand and add with reduced multiplicand. The algorithm of ten-fold addition is known. In the device, it is performed as follows.

The binary addition signal bus 4 supplies the signal to the binary addition circuit of tetrad and generates a complete binary addition of the contents of accumulating adder 1 with the contents of the register of multiplicand 2. After a time interval sufficient for the spreads and the sum to be established, a correction signal is generated on bus 7. This signal

through the correction inverter / 5 stops binary addition and allows the formation of a correction to "6 on one of the schemes" And P or 18 forming a correction to "6. In the / 7 scheme, the output signal is generated in

when the value of the tetrad in the accumulating adder 1 of the partial products after adding was greater than 9, and in diagram 18, the output signal is generated if transfer from this

tetrads. If any of the signals at the outputs of the "AND P or 18" at the output of the "OR 11" circuit is present, a code "ITO" arriving at the input of the tetrad of the accumulating adder is formed and is folded according to the rules of binary arithmetic with its contents. After

determining the sum of the signals of addition and

corrections are removed from the corresponding

tires.

To add -particles with

The following regularity is used for the controlled multiply: the binary bits of the 8, 4, 4th tetrads of the multiplicand add up with the divisions of 4, 2, 1 (k-1) -th tetrad of partial products according to the rules of binary arithmetic: bit 1 / The cth tetrad indicates whether the code "5" should be added to this tetrad, and this is taken into account when adjusting the addition.

The rules for the sum correction after binary addition are as follows:

the tetrad, where the sum turned out to be greater than "9 and the bit size of 1 multiplier tetrad is zero, is corrected by

The tetrad, in which the multiplier tetrad size is equal to "1, is corrected to" 5 if the sum turned out to be less than five, or corrected to "11 if the sum turned out to be more than five.

To add a smoothed multiplicable on the add-on bus 6 by a shift to the left by three bits, a signal is sent to the add-on tetrads circuit 10 by a shift to the left by three digits, which passes the contents of the register of the multiplicand 2 to the accumulating adder 1 of the partial products in such a way that 8, 4, 2 bits (k-1) of the tetrad go through the bus 23 of the youngest tetrad into 4, 2, 1 bit, and the k-th tetrad, and organizes a complete double addition of the above tetrads in the accumulating adder.

The signal on the addition bus 6 also goes to the pa correction circuits, 14, to the And 21 circuit and to the NOT 16 circuit, the output of which blocks the correction on the 6 on the And 17 and 18 circuits. After determining the amount, a signal is sent on the bus 7 correction signal, which blocks the addition of scheme 10 and allows the formation of a correction in circuits 14, 12, and 21. In scheme 21, the output signal is generated when the first digit of the multiplicand tetrad is equal to "O and the resulting value of the tetrad and a. accumulator after add more than "9. The output of the circuit 21 is connected with the circuit "OR 11, forming a correction signal PA" 6. In the "And 12" scheme, the output signal is generated when the first digit of the multiplicand tetrad is equal to "1 and the resulting value of the tetrad of the accumulating adder after the addition is less than" 5. The output signal of circuit 12 in the form of a code "0101" is fed to the input of the tetrad of the adder / and is added to its contents according to the rules of binary arithmetic.

In diagram 14, the output signal is generated when the first digit of the multiplicand tetrad is equal to "b and the resulting tetrad value of the adder 1 after addition is greater than or equal to" 5. The output signal in the form of a " 1011-code enters the adder's tetrad input and adds to its contents according to the rules of binary arithmetic. After the sum is established during correction, the signals of addition to the multiplied mnable and the corrections for tires b and 7 are removed.

To add partial production with doubled multiplicand, the following regularity is used: binary bits of the 8, 4, 2, 1 kth tetrade of the multiplicable add up with bit 1 (k-1) -th tetrad and bit 8, 4, 2 partial works of tetrad according to the rules of binary arithmetic, thereby performing addition with a shift of one digit to the left.

The rules for the sum correction after binary addition are as follows:

- the tetrad, where the sum turned out to be greater than or equal to "4, and the tetrad of multiplicand greater than or equal to" 8, is corrected by

- the tetrad, where the sum was received was equal to "4, and when binary addition the transfer was fixed, it is corrected by

- tetrad, where the amount was received more than "9, is adjusted to

-tetrada, where the amount was received less than "4, and the transfer was fixed in binary addition, is corrected by

The tetrad, where the sum turned out to be less than 4, and the tetrad multiplied is greater than or equal to 8, is corrected to 6.

To add to the doubled multiplicated on the add-on bus 5 with a shift by one bit

to the left, a signal is applied to the binary addition signal formation circuit 9 of tetrads with a shift to the left by one bit. A full binary addition signal is generated so that bits of 8, 4, 2, 1 kth tetrads

the multiplicand is added together with the 1 (k-1) -th tetrad and with the 8, 4, 2 k-th tetrad of the accumulating adder. The same signal is received on the “And 22 formation of the correction circuit” on “6 and on the“ And

19 and 20 form the correction to "12. After the sum has been established, a correction signal is applied to the bus 7. which blocks the addition with doubled multiplication and allows the formation of a correction in the circuits

"And 17-20, 22. In diagram 17, the output signal is generated when the resulting value of the tetrad of the cumulative adder after adding is greater than" 9. In diagram 18, the output signal is generated in the event that

when, when adding with double M, the transfer was fixed, and the resulting value of the tetrad-accumulator adder is less than 4. In diagram 22, the output signal is generated when the resulting

the value of the tetrade of the cumulative adder / after addition with the double multiplicand is less than "4, and the tetrad of multiplicative is greater than or equal to" 8.

From the outputs of the circuits 17, 18 and 22 signals through

scheme // in the form of code "IT is fed to the input of the adder /.

In the coincidence circuit 19, the output signal appears in the case when the value of the adder's tetrad / after addition with a double multiplicator is greater than or equal to "4, and the corresponding tetrad of multiplicative is greater than or equal to" 8.

In the < 20 pattern, the output signal is generated in the case when, when adding c), the binary multiplier recorded transfer from the corresponding tetrad of the cumulative adder / and its value is greater than or equal to "4.

From the outputs of circuits 19, 20, the signals through the circuit "OR 13 in the form of a code" 1100 arrive at the input of the tetrade of the adder /, where the usual addition with its contents is performed. After the sum is established during the correction, the addition signal is shifted one digit to the left and the correction signals are removed from the buses 5 and 7.

Subject and s about-and r and and

A device for multiplying decimal numbers containing an accumulator of partial products, a multiplicative register, a tetrad analysis circuit, a binary addition tetrad generation circuit, a binary addition generation circuit of tetrads shifted to the left by one bit, a binary addition generation circuit of tetrads with a shift to the left for three bits, the schemes for forming the correction for five, and six, for eleven and twelve, performed on the logical elements "AND," OR, "NOT, characterized in that, in order to save about equipment, one input of the binary addition signal formation circuit the tetrads are connected to the binary addition signal bus, its other input is connected to the output of the “first scheme” NOT, with the first input of the binary addition signal formation circuit of the tetrads shifted to the left by one bit and with the first input of the circuit generating a binary addition tetrad signal with a left shift of three bits; the third input of the binary addition signal formation circuit of the tetrads is connected to the second input of the binary addition signal formation of the tetrads with a shift to the left by one bit, with one input of the tetra analysis analysis circuit and the input of the multiplicative register; The output of the binary addition signal shaping circuit of tetrads is connected to the first input of the accumulating partial accumulator, the second input of which is connected to the output of the binary addition signal generation circuit of the tetrads with a left shift by one bit, the third input of which is connected to the binary addition signal with a shift

to the left by one bit and with the first inputs of the first, second and third circuits "And, the second inputs of which and the first inputs of the fourth, fifth, sixth, seventh and eighth schemes" And And

the input of the first circuit is NOT connected to the correction signal shaping bus; the third inputs of the first and second “And” circuits are connected to one of the outputs of the tetrad analysis circuit, the other output of which is connected to the fourth input of the first And circuit and the second input of the sixth And circuit, the third output of the tetrad analysis circuit connects to the fourth input of the second And circuit to the third input of the third circuit outputs the first and

The second AND circuit is connected to the inputs of the first OR circuit, the output of which is connected to the third input of the accumulator of partial products, the fourth input of which is connected to the output of the tetrads binary addition signal shaping circuit shifted to the left by three bits, the second input of which is connected to bus of the register of the multiplicable preceding tetrad, and the third input is connected to the second inputs of the fifth, seventh

and the eighth schel1 "And, with the input of the second circuit" NOT and with the binary addition signal bus with a shift to the left by three bits; the second input of the fourth circuit “And and the third input of the fifth circuit“ And connected to the fourth output

tetrad analysis circuit, the fifth output of which is connected to the fourth input of the fifth circuit; the output of the latter is connected to the first input of the second OR circuit, the second, third and fourth inputs of which are connected respectively to the outputs of the third, fourth and sixth circuits; the output of the second OR circuit is connected to the fifth input of the accumulating adder of partial products, the sixth input of which is connected to the output

the eighth circuit of the output of the second circuit "is NOT connected to the third inputs of the fourth and sixth circuits" And, the fourth inputs of the third and sixth circuits "And connected to the sixth output of the tetrad analysis circuit, the seventh

the output of which is connected to the third inputs of the seventh and eighth circuits; the eighth output of the tetrad analysis circuit is connected to the fourth input of the eighth And circuit; the ninth output of the tetrad analysis circuit is connected to the fourth input of the seventh And circuit, the output of which is connected to the seventh accumulator input. from Mmator of partial works, the output of the connection is connected to another input of the tetrad analysis circuit.,., -.