SU541170A1 - Multiplier - Google Patents

Description

the conversion of the direct code to the additional one is connected with the third input of the device, and the output is connected with the input of the add-on block of negative numbers, the output of which is connected to the first input of the block of adders, the second input of the second conversion unit of the direct code to the additional one with the fourth input of the device, and the output is with the second input of the block adders, the output of which is connected to the output of the device.

The direct-to-additional code conversion block contains a memory element, a dynamic trigger, an AND-NOT element, and an OR element. The first input of the memory element is connected to the first input of the block and the first input of the NAND element, the second input is connected to the second input of the block, and the output is connected to the first input of the OR element, the second input of which is connected to the output of the dynamic trigger and the second input of the AND element NOT, and the output is with the dynamic trigger input, the output of the AND-NOT-element with the output of the block.

The block-heme device is represented in the drawing.

The device contains the first 1 and second 2 blocks of conversion of a direct code into an additional one, block 3 of addition of codes of negative numbers, element 4 and block 5 of adders. The direct code to additional conversion unit contains memory element 6, NAND element 7, element 8 OR, dynamic trigger 9.

Consider the work of the proposed device as a whole.

When multiplying positive numbers, the multiplier code is fed through block 1 to convert the direct code to additional code and block 3 to add codes of negative numbers to the first input of block 5 of adders without change. The multiplier code passes through the block of direct-to-extra code conversion 2 also without changing to the second input of the block of adders, where it successively unlocks the valves with its significant bits. Since the combination of opened valves in block 5 of adders corresponds to the code combination of a multiplier, and the inputs of each subsequent adder feeds the result of the previous summation and the multiplicable code delayed accordingly, the product code is formed as a result of summing the partial products.

In the case of multiplication of negative numbers, the multiplicand code, the passage through block 1, triggered by the sign multiplier of the multiplier, is converted to an additional one with respect to the original one, i.e., to a positive number code. A similar assignment undergoes a multiplier code, a pass through block 2. Further operations are performed as in the previous case. In this case, at the output of the block of adders 5, an additional product code is obtained.

When multiplying numbers: different zigkgok two cases are possible.

When the multiplicand is negative and the multiplier is positive, the first and second blocks

conversion of the direct code to the additional one is not triggered and the corresponding codes pass through them without modification, the multiplicand code is fed to the input of block 3 as an additional code of a negative number.

In this block 3, the addition of negative number codes is triggered and the multiplicand code arrives at the input of the block of adders with the addition of units following in time beyond the significant digit, so that in the block of adders,

there is a summation of partial products in the following form (, ai - the value of bits of the multiplier, starting with the youngest: you):

a 1X111111111 mantissa

a2Х 11111111 mantissa aZH1 111111 mantissa a4 X1 1 1 1 i 1 mantissa a5Х1 1111 mantissa a6Х1 111 m antissa

a7x1 11 mantissa

а8Х 11 mantissa

which corresponds to obtaining the result of multiplication in the form of an additional code of a negative number.

The second case, when the multiplicand is positive and the multiplier is negative, reduces to the previous case. In this case, the sign bit multiplier runs blocks 1 and 2, which convert the corresponding codes into

additional in relation to the original, after which the multiplicand becomes negative and the multiplier positive.

The elements of the controlled delay line in the block of adders provide the necessary

shift of partial products relative to each other. The valves of the controlled delay line are unlocked by the control pulses at the same moments when the corresponding valves are opened with significant bits of the motor. All valves are locked at the same time, after the block of adders (2 / n-j-i) -ro of the multiplicand arrives at the first input. When building specialized devices, such as

digital correction filters, the proposed device provides a gain in speed of about 1.5 times.

Claims (2)

1. A device for multiplying, which contains a block of adders and a block of addition of negative number codes, characterized in that, in order to improve the speed of the device, the first and second blocks of direct code conversion into an additional and AND elements are entered into it, the first input of the AND element is connected with the first input of the device, the second input with the second input of the device, and the output with the first input of the first the direct code to additional conversion unit and with the first input of the second direct code to additional conversion unit, the second input of the first direct code to additional conversion unit is connected to the third input of the device, and the output is connected to the input of the addition block of negative numbers, output " connected to the first input of the block of adders, the second input of the second block of conversion of the direct code to the additional one is connected to the fourth input of the device, and the output to the second input of the block of adders, the output of which is connected to device output. 2. The device according to claim 1, characterized in that the direct to additional conversion unit contains a memory element. a dynamic trigger, an NAND element and a 1-1LI element, with the first input of the memory element connected to the first input of the block and the first input of the NAND element, the second input to the second input of the block, and the output to the first input of the OR element, the second the input of which is connected to the output of the dynamic trigger and the second input of the NAND element and the output to the input of the dynamic trigger; the output of the NAND element is Connected to the output of the block. Sources of information taken into account in the examination: 1.Kartsev M. A. Arithmetic devices of electronic digital machines. 1958. 2.Nat US No. 3610907, cl. 235-164, 1971.