SU450167A1 - Device for dividing binary numbers - Google Patents

Description

(54) DEVICE FOR FISSION OF BINARY NUMBERS

Fall 15, the fourth group of matching schemes 16, the first additional group of matching schemes 17, the second additional group of matching schemes 18, the third additional group of matching schemes 19, the fourth additional group of matching schemes 20. The first input of the device 21 and the second input of the device 22.

The device works as follows.

The initial numbers for division in the device are the normalized divisor and the dividend, either in normal form or with one zero between the digit of the sign and the highest significant unit.

After the (t-1) th operation cycle is completed, the device is in the following state: the remainder register 2 contains the reverse or additional code of the last remainder (or dividend), the private register 10 contains the quotient that precedes the remainder located on the remainder register 2 ( at the beginning of the operation zeros). The state of the remaining elements is not significant. The signal for performing the f-ro cycle, which is fed to the second input of the device 22, the remainder of the remainder register 2, through the fourth group of matching schemes 16 and the first group of collecting circuits 1 is transmitted to the input of the high number word determination circuit 4 and the remainder shift scheme 8. At the same time the digit of the remainder sign from the output of the sign bit of the first group of collecting circuits 1 is supplied to control the converter of code 6, to control the scheme for determining the number of the highest unit of the word 4 and to the input of the shifting circuit and forming a private 12. Scheme 4 op Determining the number of the highest unit of a word, depending on the sign, converts the remainder into a direct code and counts the number of the highest unit in the remainder code, i.e., the number of zeros between the significant digit and the highest significant unit. The result of the count, equal to the number of zeros, goes to the control of the shift scheme of the remainder 8 and the shift and formation scheme of the private 12. The remainder received on the shift scheme of the remainder 8 is shifted to the left by the number of zeros in it, i.e. normalized, and fed to the second input adder 5. At the first input of the adder 5 through the code converter 6 from the register of the divider 7, in accordance with the sign of the remainder, the code divider. For a positive balance, the code is a divider is inverse, and for a negative balance, the code is a divider. The result of the addition is the i-th remainder, which from the output of the adder 5 through the first additional group of matching circuits 17 is fixed to the additional register of the remainder 3.

At the same time, the last quotient from the output of the private register 10 through the second group of matching circuits 14, opened by the signal at the second input of the device 22, and through the second group of collecting circuits 9 enters the input of the shifting and forming private quotient 12. This scheme shifts the quotient to the left by the number of zeros in the remainder, and the vacant positions of the private are filled with either the number 100 ... O, if the sign of the (i-1) -th OS1 5 tatka "plus, or 011 ... O, if the sign

(t-1) th residue “minus. Here k is the number of zeros calculated by the definition scheme 4

numbers of the highest word unit. The result is the quotient corresponding to the i-th remainder, through the third: an additional group of coincidence circuits 19 is recorded on the additional register of the quotient 11.

The execution signal (r + 1) -th cycle, which enters the first input of the device 21, performs actions similar to those described above, with the only difference that the initial balance for operation is the g-th residue,

located on the additional register of remainder 3 the quotient corresponding to the fth residue is on the additional register of quotient 11. The result (1 - {-) - b1t the remainder will be fixed on the register of the remainder 2, and the quotient corresponding to (t + l) -My the remainder - on the register of private 10.

Thus, due to the proposed node connections, each clock cycle is used as a working time, and the same clock cycle is preparatory for the next one. In addition, the adopted algorithm makes it possible to determine on the basis of a given balance, on average, several private bits. As a consequence, the speed of the device increases significantly.

Subject invention

A device for dividing binary numbers

containing the register divider, the output of which is connected to the first input of the converter of the code, the output of which is connected to the first input of the adder, the second input of which is connected to the output of the residual shift circuit, the first

the input of which is associated with the output of the definition circuit of the highest word unit and with the first input of the shift and formation of the private circuit, the output of which is connected to the first input of the first group of coincidence circuits, the second input of which is connected to the first input of the device, and the output to the input of the private register, the output of which is connected with the first input of the second group of matching circuits, the second input of which is connected to the second input of the device, the output of the adder being connected to the first input of the third group of matching circuits, the second input of which is connected to the first mu; the input of the device, and the output to the input of the register of the residue, the output of which is associated with the first

the input of the fourth group of coincidence circuits, the second input of which is connected to the second input of the device, characterized in that, in order to improve speed, the output of the adder is connected to the first input of the first additional group of coincidence circuits, the second

the input of which is connected to the second input of the device, and the output to the input of the additional residue register, the output of which is connected to the first input of the second additional group of matching circuits, the second input of which is connected to the first input of the device, and the output to the first input of the first group of collecting circuits, The second input of which is connected to the output of the fourth group of circuits is the same, the first output is with the first input of the high definition number circuit and the second input of the residual shift circuit, and the second output is with the second input of the converter code, with the second input of the higher number unit definition circuit and with the second input of the shift and private quotient circuit, the output of which is connected to the first input of the third additional group of coincidence circuits, the second input of which is connected to the second input of the device, and the output to the input of the additional private register whose output is connected to the first input of the fourth additional group of coincidence circuits, the second input of which is connected to the first input of the device, and the output to the first input of the second group of collecting circuits, the second input which is connected to the output of the second group of coincidence circuits, and the output to the third input of the shear and quotient formation circuit.

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