SU612240A1 - Converter of the integer part of binary code into binary-decimal one - Google Patents

Description

I

This invention relates to automation and computing.

A device is known for converting a binary code into a binary-decimal one containing triggers and elements AND-NPE ij. The disadvantage of it is low speed.

The closest technical solution to the proposed is to convert the integer part of the binary code into a binary-decimal, each tetrad of which contains triggers and AND-NOT elements, with the installation input of the first trigger connected to the first input BUS, and the installation inputs of the second, third and the fourth trigger is connected respectively to the outputs of the first, second and third elements, the output of the fourth element is NOT connected to the output bus, and the input bus is connected to the counting inputs of all four triggers, the first and second inputs of the first electric (the AND-NOT tape is connected respectively to the outputs of the fifth and sixth elements of the NAND, nepBfcffl and the second inputs of the second AND-NOT elements are connected respectively to the outputs of the seventh and eighth elements of the IS-NOT, inputs of the third AND element NOT connected to the outputs of the virgins and

of the tenth element of the NAND, the first inputs of the eleventh and fourth elements of the NAND are connected respectively to the i-vertex output of the first trigger and

outgrowth of the twelfth element AND-NOT L2J.

The disadvantage of it is also low speed.

The aim of the invention is a faster response time.

This is achieved by the fact that in each tetrad the direct output of the first trigger is connected to the first inputs of the fifth, eighth, tenth, and twelfth elements of the NAND, inverse output of the first

the trigger is connected to the first inputs of the sixth and the other NAND elements, the forward output of the third trigger is connected to the second inputs of the sixth, seventh, and eighth elements of the NAND, and the Jersey

output of the second trigger is combined with

the second input of the nineth NAND element, the third output of which is about the third and second inputs of the sixth and twelfth AND-NO elements, respectively

Claims (1)

and the direct output of the third trigger, the inverse output of which is connected to the first and second inputs of the seventh and fifth elements AND AND NOT, the direct output of the fourth trigger is connected to the second and the inputs of the tenth and one IAD elements of AND AND NOT, and the inverse output of the fourth trigger connected to the third inputs of the fourth and fifth elements, the third inputs of the first and second elements AND-NOT connected to the output of the eleventh element AND-NOT, and the second inputs of the first and fourth elements AND-NOT connected to the output of the sixth element AND-NOT. FIG. .1 is a diagram of the tetrad of the converter. Received notation s elements i-NOT - 1-12, triggers: 13-16, forming a tetrad. The converter operates as follows. If the state of the triggers of the tetrad corresponds to codes from zero; to four, then the setup input of the trigger 14 through the elements AND-NOT 1 and 5 is supplied to the level of the direct output of the trigger 13, to the installation input of the trigger 15 through the elements IS-NE 7 or 8 and 2 is fed to the direct output of the trigger 14, to the installation Trigger 16 input through elements 3 and 9 is applied to the direct trigger trigger output level 15. At the next clock pulse, a code is shifted one bit to the right with the input information bus level entered into trigger 13. If the state of the tetrad triggers corresponds to codes from five to nine, then. at the exit of the tetras hells element AND-NOT 4 using elements AND-NOT 6) 12 or trigger TB organizes the level of the transfer, and the elements AND-NOT S-- I through the elements AND-NOT 1-3 organize correction levels on. Trigger Trigger 14-16. On the next clock pulse, the arrival to the counting inputs of the triggers, the level corresponding to the input information bus level will be set at the single output of the trigger 13, the level determined by the AND-NE elements 1, 5, 6, 11, at the unit output of the trigger 15, a level determined by the AND-NO elements 2,7,8,11 is set, at a single output. the trigger 16 will be set by the level determined by the elements AND-HE 3.9.10. Liken In this way, the converter of a binary-decimal code into a binary one can be constructed. FIG. 2 shows the scheme of the tetrad. Received names: AND-NOT elements 1-12, trigger 13-16 ,, forming a tetrad, which operates as follows. If the permit level is set at the input, then in the tetrad, the code shifts by one bit to the right in the tetrad by the next clock pulse. At the same time, at the output of the trigger 13 a logical zero level will be set. At the direct output of the trigger 14, the level determined by the AND-HE elements 2 and 10 will be established. The direct output of the trigger 15 will set the i-level determined by the AND-HE elements 4 and 11; At the direct output of the rigger 16, the level determined by the AND-NES elements 6 and 12 is set. If the resolving level is set on the 17, then the correction code triggers on the next clock pulse in the triad triggers. At the same time, on the forward output of the trigger 13, a level determined by the AND-NE elements 1, 7 and 9 will be set; on the right output of the trigger 14, the level determined by the AND-NOT elements 3, 5 and 11 will be set; At the direct output of the trigger 16, the level determined by the elements AND-NE 7, 8 and 12 will be established. Using the invention allows to increase the speed of the code converter, and when used, the front trigger drivers increase reliability, since in this case cxef ; a does not impose restrictions from above on the duration of clock pulses and pulses. The proposed device for conversion can be used for S automation equipment and computing equipment. The invention of the converter of the integer part of a binary code into a binary-decimal, each tetrad of which contains triggers, and AND-NOT elements, with the installation input of the first trigger connected to the first input bus, and the installation inputs of the second, third and fourth trigger are connected respectively to the outputs of the first , the second and the third, I-NK elements, the output of the fourth I-NO element is connected to the output bus, and the second input bus is connected to the counting inputs of all four triggers, the first and second inputs of the first I-N element connected to the outputs of the fifth and sixth elements AND-NOT, the first and second inputs of the second element AND-NOT connected respectively to the outputs of the seventh and eighth elements-OB AND-NOT, the inputs of the third element AND-NOT connected to the outputs of the ninth and tenth NAND elements, the first inputs of the eleventh and fourth NAND elements are connected respectively to the inverse of the output of the first trigger and the output of the twelfth element NAND, characterized in that, in order to improve speed, in the treasury tetrad the first output of the first trigger is connected with the first inputs of the fifth, eighth / tenth and twelfth elements AND-NOT, the inverse output of the first trigger is connected to the first inputs of the sixth and ninth elements of AND-NOT, the direct output of the second trigger is connected to the second inputs of the sixth, seventh and eighth elets And -NO, the inverse output of the second trigger is connected to the second input of the ninth NAND element, the third input