SU1418731A1 - Device for rearrangement of natural number series and zero - Google Patents

Abstract

This invention relates to automation and computing. The aim of the invention is to expand the scope by calculating the number of permutation. The invention for the first time implements a direct algorithm for calculating a permutation number according to its coded representation and makes it possible to significantly reduce the search time for numbered objects while simultaneously reducing the amount of memory needed to store image elements. The device for numbering permutations contains input information bus 1 from (n-1) -th code group for connecting all codes of permutation elements of degree n, except for zero, (p-2) block of degree of permutation 2, () multipliers 3 on constant, multi-input the adder 4, the output information bus 5 numbers of permutations. 2 Il. (Oh (L

Description

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The invention relates to automation and computing and can be used to create high-performance specialized devices for solving combinatorial problems.

The aim of the invention is to expand the scope of application due to VyA1

the number of the generated reset is 10 P class C ,, In the block, .2J is the origin,

 FIG. 1 is a block diagram of the j device; in fig. 2 is a structural I diagram of a reorder reduction unit.

 The device contains an input of 1 elements of the permutation array, blocks 2 "-2.1 5 downsizing the degree of permutation: ki, where n is the number of elements in the permutation, multipliers 3, -3"., On; constant, multi-input adder A,; output 5.

: The block of the degree of permutation {ki contains memory blocks, where i is the number of the block of the degree of permutations,

; The device calculates the degree permutation number with the numbering of the elements from O to (p-1).

The principle of operation of the proposed device is based on dividing a certain number of permutations A y, degree n into classes of capacity (n-1). such that the leftmost element

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 which for a given conversion has the meaning of control information.

The device works as follows.

Codes of the permutation elements are fed to the input 1 of the device, while the input 1 j ,. l is a no-10 P class C ,, In a block, .2J a prog R a class C, In a block, .2J a

Diet converts a degree permutation (p-1) to a permutation of a degree (p-2) under control of the code C ,, Code on (p-2) the output of block 2 (,,. 2, corresponds to the class number C, which controls the process of reducing the degree permutations in the block., etc.

Code} of class numbers C, where k 1, (n-1) also goes to multipliers by the constant 3 („.)), Which perform the multiplication C | by the value of (n-k) /.

The codes from the outputs of the multipliers by a factor of three are summed in the multiple input adder 4, the output of which forms the code of the permutation number, which arrives at output 5.

Claims (1)

Invention Formula A device for numbering permutations of a natural number of numbers and a zero containing a multi-input adder, characterized in that, in order to expand the area the following relationship takes place: 40 45 the permutation equals the class number 35 i ™ by calculating the number of the permutation being generated, n-2 of the permutation degree lowering block is entered into it, where n is the number of permuted numbers, and n-1 multipliers per constant, while the value of the constant j-ro multiplier by a constant is equal to jj (j 1,2, .., p-1), with the i-th block Reducing the degree of permutation (i 1,2,., p-2) contains i memory nodes, inputs of codes of elements of the permutation array the first through (p-2) -and devices are connected to the first address inputs, respectively, from the first through (p-2) -th memory nodes (p-2) -th block of lower degree, the second address inputs of the memory nodes of which are combined and connected to the input of the (n-1) -th element of the device permutation array and the input of the (n-1) -th multiplier by a constant, the output of the k-ro memory node of the 1st of the permutation reduction unit (k 1,2, ..., 1-1; 1 2,3,.,., p-2) is connected to the first address input of the k-ro memory node pp (p-1). As a result of this decomposition, the classes will be numbered from O to (n-1). The number of the class to which the given permutation will be assigned, we denote C, Continuing the process, we obtain, respectively, C and (n-2), etc., The process of reducing the degree of permutation in the transition to a set of permutations of a lesser degree of statite in renumbering the elements of the original permutation Thus, reducing the degree of permutation by one consists in truncating the original permutation from the left by one element and decreasing the values of the remaining elements by one j. if this value exceeds the value of the item being dropped, The value of the leftmost permutation element is the class number. 50 : 55 3U (ll) -ro block of the degree of permutation, the output of the 1st memory node of the 1st block of the degree of permutation is connected to the second address inputs of all the memory nodes (1-1) of the block of the degree of permutation reduction and the input of the 1st multiplier on a constant, the output of the first node of the memory is the first 314 The first permutation reduction unit is connected to the input of the first multiplier by a constant, the outputs of the multipliers to the constant from the first to (n-1) -th are connected to the corresponding inputs of the multi-input adder, the output of which is connected to the output of the device. Manager (move of Fig. 2