SU122948A1 - Arithmetic unit - Google Patents

Description

Arithmetic devices that perform the multiplication operation are known. The main disadvantage of such devices lies in the fact that the multiplication operation takes considerable time. This has a negative effect on the speed of the machines. A significant reduction in the time it takes to perform an array of known devices is achieved by simultaneously deciphering the values of the multiplicative bits, but this significantly complicates the arithmetic unit of the computer.

The proposed device provides a reduction in the time required for the implementation of multiplication multiplication without significantly complicating the arithmetic unit. ATS is achieved by using a parallel logic circuit in an electronic computer for generating control pulses when decoding the values of pairs of multipliers.

The skeleton diagram of the device is shown in the drawing, where the following designations are given:

1 is the multiplier register, 2 is the multiplier register, 3 is the product register, 4 is the OR logical unit, 5 is the NO logical circuit, 6 are the gates, 7 is the digit corresponding to the youngest multiplier of the multiplier, 8 is the number corresponding to the highest

of the multiples of the bits of the multiplier, 9 is the unit of transfer resulting from the preceding partial production cycle,

10 is a switching function, but a feature of which is multiplied by 2 multiplied by a private projection;

11 is a switching function, on the basis of which to the partial product is added the product of the multiplicand by 2t,

12 is the unit of transfer to the senior bit of the multiplier, 13 is the switching function, on the basis of which the product of the multiplicand by 2 in the forward or backward course is added to the partial output, 14 is

the value of the delay for the time of one clock cycle; 15 — the logic circuit for generating control n pulses.

P1polzu device "PLP n submitting through them to the adder in nr mole; or reverse

in a code, the product of a multiplicand by 2- or only in the forward code of the multiplication of a multiplicand by 2i, the multiplication of the multiplication simultaneously by two digits of the multiplier per cycle. At THIS, the multiplication and partial rendering should be carried out simultaneously by two digits.

Subject and d on and e and

An arithmegic ycTpoiicTBo for an electronic digital computing machine and a parallel action, characterized in that, p. the purpose. , ie, i.e., i.e. operation of the damping operation, p} jgf & j i-ieHa logical scheme for 1.-H.-. (... .. A .. exp, UTK of control pulses with the increase of jonKe values of pairs of multipliers,

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eleven

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