SU478306A1 - Matrix parallel processor for calculating the Hadamard transform - Google Patents

Description

in the numerators of the third column, the fi matrix is connected to the inputs and outputs li of the processor directly.

G FIG. 1 shows a block diagram of a processor; FIG. 2 is a schematic of a computational unit.

Matrix pair The 1-core processor contains computational blocks 1, combined in three columns. The numbers 2 and 3 are designated respectively the inputs and outputs of the processor.

 Computing unit 1 contains the sum of the tori 4, 5 and inverter 6. The numbers 7.8 and 19, 10 denote the inputs and outputs of the computing unit, respectively. The information enters the processor, encoded in power at

; .-. ; -...., -.

: rascheny (SP). Coding is performed according to the following algorithm:

Scaling information ranging from O to 1.

Addition with the number 0.5. Multiplication by 2. Addition with the number 0.5.

 The first D1va binary bits that | | | to the left of the comma are the next ste-1:; foam increment ..;

|| In tab. 1 shows an example of coding, numbers, OO10011 in the form of power ones at | increments, then B (A + O, 5) T

iX.X and

1 (O.lOlOOll) where B is coded

 - ,.

: number, at- coding step number.

Table 1.

AT

2B

Decoding is an algebraic addition of quantitative I equivalents (weights) of power increments (see last; column of table 1).

 As you can see, the operation of complex 4 “nn is possible only in the absence of a re. noses one bit ahead, i.e. in the absence of combinations of power increments of the form 10.1О and ОО.О. This condition is fulfilled; it is always fulfilled by the existence of a number of theorems.

An example of the addition of the previously coded A number OO010011 (SP O1.1O.OO.

01.10.01.0О) and the numbers A 0.0010101

01; flO.00.10.OO.lO.ll) is provided

(SP in Table 2.

2B + O, 5

SP

Table 2.

Addition is performed as increments are received, in the example shown, from top to bottom, i.e., from higher increments to lower ones. Each computational unit 1 of a matrix parallel processor implements the expressions: (1) Bi4 ..- B, (2) where i is the column number of the matrix parallel processor, A, B are operands received at inputs 7 and 8 of computational unit 1, respectively . A: + 1, V. + 1 are the results of calculations arriving at the outputs 9 and 10 of the computing unit 1 of the matrix parallel processor, respectively. Computing units 1 are interconnected according to the graph describing the fast Hadamard transform. The number of inputs of a matrix parallel processor is always a multiple of a power of two. Then the number of processor columns will be equal to the value of the exponent, and the number of rows - the number of inputs divided in half. Each computational unit 1 processes information sequentially, starting with the higher bits. Computing unit 1 implements formulas (1) and (2), with adder 4 formula (1), and adder 5 - formula (2). Inverter 6 is needed to multiply the number, .lB by -1. The work of the matrix parallel pro processor is as follows. The inputs 2 are fed sequentially with information encoded as power-law during growth. The most significant bits of the result processed in the first column of the matrix parallel processor go to the second column for further processing, from there to the third column, and so on. At outputs 3, the leading bits of the final Hadamard transform result are added to inputs 2 the lower bits of the initial array of numbers continue to arrive. When the output of outputs 3 is sufficient to provide the required accuracy in the number of higher-level result, the calculation process can be stopped. It is easy to see that the operation of the computational unit 1 of the matrix parallel processor consists in receiving the next power increments of the operands and adding (subtracting) them in accordance with formulas (1) and (2). Power increments of the result are output from the computational unit of block 1, and the following pairs of increments are input to the input simultaneously with the output. It should be noted that each adder included in block 1 of the matrix parallel processor delays information by one clock cycle, which will be done from the above algorithm for adding two numbers represented as a power of increments. Obviously, the computing unit 1 of the matrix parallel processor in In general, information is also delayed by one cycle. Let us estimate the speed of the matrix parallel processor. It is determined by the delay of all computational blocks 1, i.e., the delay in the shortest serial circuit made up of computational blocks 1. In this case, the circuit length is equal to the number of columns of the matrix parallel processor, which can be calculated by the formula the time necessary to process the entire source array, times (in cycles) T to9., where H is the number of inputs of the matrix parallel processor equal to the number of numbers in the original volume-. the array being processed, and М - j is the number of most significant bits of the result, „; providing the necessary accuracy of calculations. If H is 1024, the duration of one clock cycle is 1 microsec, and M is 1O, then microsecond, which is 800 times faster than that of a known processor. Subject of the Invention Matrix parallel processor for calculating the Hadamard transform, containing computational blocks in matrix nodes made in the form of an adder, the inputs of each of which are connected to the inputs of a computational unit, and the first output of each computational unit is connected to In order to increase speed, each computing unit contains an inverter and an additional adder, whose output is connected to the second output of the computing unit, one in one of which is connected to the first input of the additional adder directly, and the other input through the inverter is connected to the second input of the additional adder, and the inputs of the first computational block of the second and third arcs of the matrix are connected to the first outputs of the first and second computational blocks of the first and second columns of the matrix, respectively, the inputs of the second computational block of the second and third columns of the matrix are connected to the first outputs of the third and fourth calculator of the first blocks of the first n second table btsov; matrices, respectively, the inputs of the third computing unit of the second and third columns of the matrix are connected to the second outputs of the first and second blocks of the first and second columns of the matrix, respectively, the inputs of the fourth calculating body block of the second and third columns of the matrix are connected to the second outputs: the third and fourth computing blocks of the first and second columns matrices, respectively, and the inputs of the computing blocks of the first column and the outputs of the computing blocks of the third column of the matrix are connected to the inputs and you processor moves, respectively.

2

x

7-8

2

ten