SU1123031A1 - Multiplying device - Google Patents

Abstract

A DEVICE FOR DRIVING, containing an M-bit multiplica register, an N-bit multiplier register, a two-digit code adder, a parallel adder, a result register, and the bit outputs of the parallel adder are connected to the corresponding result register inputs, characterized in that extensions of the field of application, the element I, N / 2 elements 2I-IPI, N / 2 half adders, (// 2 + 1) groups of two elements are introduced into it. that AND and (M-1) of elements 2I-OR in each, M / 2 groups of semi-adders (M + 1) half-adders in each, the multiplier register contains (N / 2 + 1) groups of bits, and the first group of bits contains two lower bits of the register of the multiplier, j- group of bits of the register of the multiplier (j 2, ..- ,, ..., N / 2 + 1) contains three bits each, with the most significant bit of the g and group of the multiplier register (i 1, ..., S / 2 + 1) is equal in value to the least significant bit (| l-I) of the group of bits of the register of the multiplier; the output of the higher bit of the first group of bits of the register of the multiplier is connected to the first input of the AND elementand with (М + 2) the weight input of the adder of a two-bit code, the inverse output of the first bit of the first group of register bits of the multiplier is connected to the second input of the element I, the inverse high-order output of the first group of bits of the register of the multiplier is connected to the first weight input of the two-adder code and with the first inputs of half-adders of the first group, the output of the most significant bit of the (K + 1) -th group of bits of the register of the multiplier is connected to the first input of the first element AND of the K-th element 2I-OR and c (M + 2k + 2) - M weight input of the adder two-fold code (,.,., (L, .., M / 2), the inverse output of the higher bit (K + O th group of bits of the register of the multiplier is connected to the first input of the second element AND the K th element 2И-OR, with the first Lusummator

Description

the input of the first element of the K-th element 2I-OR, the first input of the first element AND of each group is connected to the M-th bit of the multiplicative register, the first input of the second element AND of each group is connected to the output of the first digit of the multiplicable register, the first input of the first element AND The 8th element of the 2I-OR of each group is connected respectively to the (B + 1) -th output of the multiplicable register (... J the first input of the second element AND the t-th element of the 2Y-OR of each group is connected respectively to the -th output the multiplier register, the direct output of the lower bit of the first .group of the discharge in the register, the multiplier is connected to the second inputs of the first elements AND 2I-OR elements and the second inputs of the second element AND of the first group, the output of the first element AND device is connected to the second inputs of the second element AND of the first 2I elements, and the output of the K-th element 2I-OR device is connected to VSE1 AND the inputs of the second elements AND elements 2I-IPI and the second inputs of the first element AND (1s - "- 1) -th

group, the output of the k-th half-adder of the device is connected to the second, the inputs of the first elements AND elements 2И-OR and the second inputs of the first elements And elements 2И-OR and the second inputs of the second element AND (К + 1) -and the group, the output of the first and second element Both C and groups are connected to the second inputs (M + 1) of the first and first half summators and group of half summators, the output of the Pth element 2I-OR, and the group is connected to the second input (€ + 1) of the half summator If -and groups, output from the half-adder C -th group is connected to (2K + y-2) -th weight input of the adder About the code C 1, ..., (And + 1), the outputs of the first and second element And (11/2 + 1) -and groups are connected respectively with (fH + W) -M and (H + l) -M weight input of adder of two-code code, output of element 2I-Ш1И (М / 2 + 1) -th group is connected to SI + 6) -th weights (Я4 input number of code of two-level code, bus of logical unit of the device is connected to (М +2) -m and c (ftiH-2 | t + 1) -M weight inputs of a double Gd cat, yes.

The invention relates to automation and computing, and is intended for use in specialized timing arithmetic units.

i There are devices for multiplying a binary number (multiplicand) by another binary number (multiplier), which are used to form a product of a series of additions and subtractions of multiples of the multiplicand.

The closest to the technical essence of the invention is a multiplying device containing perHctp multipliers, a multiplicative register, a double-row code adder, a double-row code adder into a single register, an L2J result register.

However, to get the product of the additional multiplier code and the multiplicand code in the known device, you must enter a special

the conversion unit of the direct multiplier to additional code, which reduces the speed of the device and requires additional equipment for the equipment.

The purpose of the invention is to expand the scope of the device.

The goal is achieved by the fact that the multiplier / M-bit multiplier register, N-bit multiplier register, dual code adder, parallel cywuaTopf result register with the output of the parallel adder connected to the corresponding result register, the element entered I, N / 2 elements 2I-SCHSH, -K / 2 half-adders, (N / 2 + 1) groups of two elements AND and (1C-1) elements 2I-ISH each, .M / 2 groups of half-summatrs (( 1 + 1) half-adders B, pjerHCTp multiplier contains (N / 2 + 1) bit groups, and the first groups bits contains two lower bits of the multiplier register, 4 — the register bit group of the multiplier (j 2, ..., N / 2 + 1) contains three bits each, with the most significant bit of the i-th register group of the multiplier (1, ..., N / 2 + 1) is equal in value to the lower-order bit (4 + 1) -and groups of bits of the register of the multiplier, the output of the higher bit of the first group of bits of the register of the multiplier is connected to the first input of the element I and c (M +2) the weight input of the adder of the two-digit code, the inverse output of the low-order bit of the first group of bits of the register of the multiplier is connected to the second input of the element AND-, investment The primary output of the high bit of the first group of bits of the register of the multiplier is connected to the first weighted input of the matrices of the two-digit code and the first inputs of the half adders of the first group, the output of the high bit of the (+1) th group of bits of the register of the multiplier is connected to the first input of the first element If the 2nd element of the 2I-IPI and with (M + 2k + 2) -: M is the weighted input of the double-digit code (, ..., N / 2), the inverse output of the high bit (k + 1) -M group bits of the register multiplier is connected to the first input of the second element AND 1 th element 2И-OR, with the first inputs half-mat oors () -A group of half-motion motors and with () -m weight input of the adder two-digit code, the output of the second bit (k. + 1) -u of the group of bits of the register of the multiplier is connected to the second input of the second element AND of the k -th element 2I- ШШ and with the first input of the k-ro half semi-horizon, the inverse output of the second bit of the (+1) -th group of bits of the register of the multiplier is connected to the second input of the first element AND of the k-th element 2И-OR, output) of the shorter digit {K + 1 ) - ft

 V. The group of bits of the register of the twofold is connected to the third input of the second element AND the k-th element 2I-OR and with the second input of the k-th half-summator, the inverse output of the low-order bit (K + 1) of the second group of register bits is set. the inhabitant is connected to the third input of the first element AND the k-ro element 2I-OR, the first input of the first element AND of each group is connected to the M-th register register multiplicated, the first input BTopforo of the AND element of each group is connected to the output of the first digit register of the multiplicand, the first the input of the first element AND the 6th element 2I-OR of each group is connected respectively to the (6 + 1) output of the multiplicative register (Е 1, ..., М-1); the first input of the second element AND the E of the second element 2И-OR each group is connected to the C-m output, respectively, of the multiplicand, the direct output of the lower-order bit the first group of bits of the register of the multiplier is connected to the second inputs of the first elements AND elements 2И-ИПИ and the second inputs of the second element И the first group, the output of the first element И the device connected to the second inputs of the second elements И the elements 2И-ИПИ and the first element И the first group, output k-th element) 2I-RShI device is connected to the second inputs of the second elements AND elements 2I-OR and the second inputs of the first. element And (Y; + 1) -th group, -output of the k-g half-adder of the device is connected to the second inputs of the first elements AND 2I-OR elements and the second inputs of the first elements AND 2I-OR elements and the second inputs of the second element And OS + 1) -th group, output The first and second elements of the k.th group are connected to the second inputs of the {M + 1) -th and first half-adders of the second group of half-adders, the output of the B-th element 2I-ШШ 1 (-th group is connected to the second input (Е + 1) -th half-adder of the k-th group, output (-th half-adder of the k -th group and connected to (21: + (- 2) -th weight input of the adder dvadrovog o code (1, ..., M + 1), the outputs of the first and second element AND (.N / 2 + 1) -and groups are connected respectively with (M + Um and (N + 1) -M weights w the inputs of the adder of a two-step code ,, the output of the 8th element of the 2I-OR (L / 2 + 1) -th group is connected to the (11 + c) th input and the input of the adder of the two-row code; the bus of the logical unit of the device is connected to (M + 2) -m and with (M + 2k + 1) -M weight inputs of the adder of a two-strand code.

The drawing shows a block diagram of a multiplier.

The device contains a register of 1 multiplier, a register of 2 multiplicand, a block: 3 evaluations of multiplier and form multipliers, which are multiples of a multiplicative, containing a two-input element I (3-1), .. (H / 2) elements 2I-ШШ (3-2, 3-ji),

to obtain the product of the additional code M - f by another binary number go through without the block of preliminary translation of the direct code M to the additional | (implemented by inverting the direct code and summing it with the unit of the additional code), which reduces the multiplication time and saves the equipment when using the image

11 mR transfer without shear

10+ 2 mR with shift

01-ShTransmission without shift

00A lack of transmission

til

about

Lack of gear 110

+ Me

Transfer without shift 101 || + IU 100

+2 Mg

Shifting gear Oil -2M,

n 010

-Me

Transfer without shift 001 11

-My

000

No gear

reteni in specialized arithmetic devices.

Thus, when a multiplier and a multiplier is fed to a device in forward codes, the result is formed at the output of the multiplicand, as when the multiplier is fed to a device in a forward code, and the multiplier is added to an additional one.

Table 1

Pr my code

Reverse code and +1 ext.

table 2

Pr my code

Reverse code and +1 ext. ||

eleven

g44-sh

Claims (1)

A DEVICE FOR MULTIPLICATION, containing M-bit register of the multiplier, N-bit register of the multiplier, adder of the two-row code, parallel adder, register of the result, and the bit outputs of the parallel adder are connected to the corresponding inputs of the register of the result, characterized in that, in order to expand the scope, an element is entered into it And, N / 2 elements of 2I-IPI, N / 2 half adders, (X // 2 + 1) groups of two elements And and (M-1) 2I-OR elements in each, M / 2 groups of half adders in (M + 1) half adders in each, the register of the multiplier contains (N / 2 + 1) groups of bits, the first group of bits containing the two least significant bits of the register of the multiplier, the jth group of bits of the register of the multiplier (j = 2, ..'-., .. ., N / 2 + 1) contains three digits, and the senior digit (of the group of the register'multiplier (i = 1, ..., ^ / 2 + 1) is equal in value to the least significant digit (h + 1) of the groups of bits of the register of the multiplier, the output of the highest bit of the first group is discharged the multiplier register is connected to the first input of the element And and with (M + 2) the weight input of the adder of the two-row code, the inverse output of the smallest bit of the first group of bits of the multiplier register is connected to the second input of the element And the inverse output of the highest bit of the first group of bits of the multiplier register is connected to the first by the weight input of the two-row code adder and with the first inputs of the half-adders of the first group, the output of the highest bit of the (K + 1) -th group of bits of the multiplier register is connected to the first input of the first element AND of the Kth element 2I-OR and with (M + 2K + 2) th weight input § adder of a two-row code (k = 1,.,., ..., M / 2), the inverse output of the highest bit (k + 1) of the group of bits of the register of the multiplier is connected to the first input the second element AND of the K element of 2I-IPI, with the first inputs of half-adders of the (£ + 1) -th group of half-adders, mators and with (2K + 1) -th weight input of the adder of a two-row code, output; the second bit of the (k-1) th group of bits of the register of the multiplier is connected to the second input of the second element AND of the K-th element 2I-OR and with the first input of the k-th half-adder, the inverse output of the second bit of the (K-1) th group of bits of the register the multiplier is connected to the second input of the first element And the k-th element 2 AND-OR, the output of the lowest -. <S -> the discharge of the (K + 1) -th group of bits of the register of the multiplier is connected to the third input of the second element AND of the k-th element 2I-OR and to the second input of the K-th half-adder, the inverse output of the least bit (K + 1) of the group of bits of the register of the multiplier connected to the third input of the first element AND of the Kth element 2 AND-OR, the first input of the first 'element And of each group is connected to the Mth digit of the register of the multiplicable, the first input of the second element And of each group is connected to the output of the first bit of the register of multiplicable, the first input the first AND element (? -th element 2 AND-OR of each groups is connected respectively with the (E + 1) -th output of the register of the multiplicable (K = 1, ... 1), the first input of the second element And of the Cth element 2I-IPI of each group is connected respectively with the Cth output of the register of multiplicable, direct the output of the least significant bit of the first group of bits of the register of the multiplier is connected to the second inputs of the first elements AND of the elements 2 AND-OR and the second inputs of the second element And of the first group, the output of the first element of the device is connected to the second inputs of the second elements AND elements 2I-OR and the first element And of the first group , output of the K-th element 2I-IL the device is connected to the second inputs of the second elements AND elements 2I-IPI and the second inputs of the first element AND (k + 1) -th group, the output of the k half-adder device is connected to the second, inputs of the first elements AND elements 2I-OR and the second inputs of the first elements And the elements 2 AND-OR and the second inputs of the second element · AND (K + 1) -th group, the output of the first and second element And the K-th group is connected to the second inputs of the (M + 1) -th and first half-adders of the K-group, respectively half adders, the output of the? -th element of the 2I-IPI of the K-th group is connected to the second input (€ + 1) - about the half adder of the K-th group, the output of the half-adder of the K-th group is connected to the (2k + ^ - 2) -th weight input of the adder of the two-row code '(^ = 1, ..., M + 1), the outputs of the first and second the elements of the And (M / 2 + 1) -th group are connected respectively to the (M + U) ~ m and (Н + 1) -th weight inputs of the adder of the two-row code, the output of the Cth element is 2I-OR (K / 2 + 1 ) of the th group is connected to the (M + 6) th weighted input of the sum -. a torus of a two-row code, the bus of the logical unit of the device is connected to (C + 2) -m and to (M + 2K + D-M) by the weight inputs of the adder * two-row cat.