SU1249508A1 - Versions of multiplying device - Google Patents

Abstract

This invention relates to digital computing. The aim of the invention is to simplify the device. The device contains adders, quadrants and elements EXCLUSIVE OR. The operation of the device is based on the identity: AB (-fS) (4-b) / 2 where the multiplication table operation is replaced by a square squared table. A distinctive feature of the device is the construction of B square in accordance with the identity: (L ± B; / 2 2 C2 () 2 22 A 2 + Y2-t- +2 (+ Y) 2-2 (;;: 2-Y, where A and Y are high and low bits C, respectively. In this case, multiplication takes place in two cycles: the value of (L + c) is formed in the first cycle, and the value of (L-j5) / 2p itself is equal to the difference of these values. 2cfl, 3, ill., oo, 4;

Description

The invention relates to digital computing and can be used in digital computers.

The aim of izobet is to build a device.

FIG. 1 crivede functional s.ke.ma device according to the nerve variant; in fig. 2 - the same. but the second option; in fig. 3 - sipeMCHHaM device operation diagram.

The device for the first (fig.) And second (fng. 2) variants contains adders 1 --- 3, quadrants 4-6. groups of elements EXCLUSIVE OR 7 and 8, inputs 9 and 10 of the first and second operands, outputs AND, clock input 12, reset input 13, synchronization input 14, tsinnuyu 1 and sumator 16.

Kpo.vie TOi O, the device but the first option will contain adder 17 (Fig. 1).

Sunliness of the invention concludes with the following.

The greatest complexity of implementation of the multiplication formula

l. (

in the case of a large factor multiplier, it causes the operation to square the expressions

A + B

L, 1.2 -

split rea. -isations of quadrants in the form of ROM in this case require very large memory costs, breaking the value from the / g parts into n bits in accordance with the expression

When 2, denoted x zi and r, (. We have the identity

 2 (); g + (x + tJ} 4- (1--2) g

and. sh equivalent of the record

c2 + 2 (.: + «) + (x - + D).

The device multiplies two tons of 2-bit binary numbers. The multiplication is carried out in accordance with expressions (1) and (4) in two cycles. At the beginning of the first clock cycle T1 (FIG. 3), the signal at input 13 zeroes the adder 2. In the first clock cycle, in accordance with expression (1), the value of

ten

.f (+ B, - V o /

0

0

five

in the KOHiie cycle, the measured result of the IM-pulse at inlet 14 is recorded in the adder 2. In the second cycle T2, the value of

"(

The result obtained is the desired product of AB and is finally fixed by the second gating pulse. The multipliers are fed to the inputs of the adder 1, whose function is the calculation in cycles T and T2, respectively, the sum and difference of factors) | j А ± В. The value D obtained at the output of adder 1 is considered as the sum of two parts of D ..

2-x is a binary code in n-highs. bit output of the adder 1 y is the code on the remaining low bits of the output of the adder 1.

The calculated values, y, are received respectively at the inputs of the quadrants, as well as at the inputs of the adder 3. The adder 1 forms the sum or difference of the input factors .D |, 2 Л ± В. However, in expression (1), the value of the nomusum and semi-) relevance of the factors

L ± -b 2

The division by two for a binary number is realized by shifting it to the right by one bit. In this connection, the result at the output of adder 1 is interpreted as

L + B

Cl, 2 -,

That is, as a binary number with 2 / g-bit integer part and one fractional part. The adder 3 generates the value of the sum of the values of the codes from the high and low bits of the outputs of the adder 1 (+ Y). Quadrtor tables are written in the square, where each value of the input code received at the inputs of squares 4-6 is assigned to the value of its square at the output of quadrants 4-6. The input of the quadrant 4 receives (n- | -1) - the bit value of y, where the n-bits form the integer part of the binary number and one bit is its fractional part. The input of quadrant 5 receives an "-discharge value -% A%, which is an integer binary

number. The input of the quadrant 6 receives an (n- | - +2) -digit code {x + y} representing the (/ 2-f-l) -disable integer with one digit of the fractional part. Quad 4-6 form at their outputs, respectively, the values: x, y and (x + y). At the same time, x and y are 2y-bit integer numbers, and (x + y) - (2, 4-2) is a bit integer. The fractional part in the I / I expressions is discarded, which, however, does not affect the accuracy of the result. Indeed, if both factors are even or both are odd numbers, then the values

 (A) and d {)

with

2 -Z- V 2

are also integers, and their fractional part is zero.

If one factor is even and the other is odd, then the fractional part of the values of cf and c is (01) 2 and, when calculating the difference AB, it is reduced. The shifts required in expression (4) are realized by connecting the outputs of quadrants 4-6 with the corresponding shifts. The adder 16 generates the sum. The adder 17 generates the value 2j: y (; с + (/) - (x - | -i /) by subtracting in return codes from the value (A: + Y) coming from the quadrant 6) the value coming from the outputs of the adder 1 to the inverse adder inputs 17. By virtue of the identity of the comparison () () at j :, adder 17 subtracts the absolute value smaller from the larger one. Necessary in this case (when adding the numbers presented in the reverse code) correction is performed by applying a correction signal the transfer input is only in the first cycle T1. In the second cycle correction is not made, h This is necessary for normal operation of adder 2. The latter generates in the first step T1 a value c () + {2 -2x: y) obtained by adding the value (-y supplied to the inputs of adder 2 from the outputs of quadrants 4 and 5 and the value 2x coming from the output of the adder 17 to the inputs of the adder 2 with a shift by l-bits. These values are fed to the adder 2 through groups of elements EXCLUSIVE OR 7 and 8.

In the first cycle T1, the signals are transmitted in an unchanged form, and in the second cycle T2 are inverted and transmitted in the return code, rtt) at the end of the first cycle T1, after fixing the result with a signal at input 14, adder 2 contains the value c. In the second cycle T2, the value of

/} B (+ yi) - (2 -2xy).

The subtraction is carried out in reverse codes, the result is corrected by the correction signal received at the transfer input in the second cycle T2 and the preadjustment of the result in the adder 17. At the end of the second cycle T2, the result is fixed

in adder 2. For normal operation of the device, the input factors must be represented in the direct code. In this case, a larger factor (L) must be given

on the first inputs of the adder 1, and the smaller factor (B) - on its second inputs. In the first clock cycle T1, at a low level at the input 12, the adder 1 performs the addition of the factors, performed the operation. In the second cycle T2 at a high level

at the input 12, the adder 1 forms the difference of the factors, performed the operation ab. Some increase in speed, as well as simplification of the output adder by a certain increase in memory capacity (by about a third) can be achieved by implementing a squaring in accordance with expression (2). Therefore, in the second version of the device (Fig. 2}, quadrants 4 and 5 in this case are assigned the function of forming, respectively, the values (1-2) / and () x.

In this case, quadrants 4 and 5 are implemented in the form of a ROM with the organization, respectively, and.

The quadratures 4 and 5 form the values (1-2) / and () x, respectively. With

this, since the value is (1-2), it is represented in the reverse code. The adder 16 generates a value (1-2) y + 2 (). The fifth adder 2, together with the groups EXCLUSIVE OR 7 and 8, performs the formation of the value of C a in the first cycle of T1 and the formation of the product AB in the second cycle of T2.

If it is necessary to further increase the magnitude of the factors, the calculation of the values of c is carried out in accordance with the expression (2) at K. The quadrator is divided into k independent quadrants. The number of adders required to form the expressions is divided into k independent quadrs. The number of adders required to form the expressions (zi + z /) for various / and / (equal to

ff / h1

. Each of these internal adders via a separate quad is connected to the corresponding inputs of the output summing circuit.

Claims (2)

1. A device for multiplying, containing the first, second and third summers, the first and second quadrants, with the inputs of the first and second groups of the first adder connected to the inputs of the first and second operands of the device, the inputs of the first quadrant connected to the outputs of the bits of the first adder from the first to (n + nth (2n is the width of the operands), the inputs of the second quad The rator is connected to the outputs of the bits of the first adder from () to (2n-- | -1) -th, the outputs of the bits of the second adder are connected to the outputs of the device, characterized in that, in order to simplify the circuit, it contains the third quadrant, the fourth and fifth adders and two groups of EXCLUSIVE OR elements, the inputs of the first group of the third adder are connected to the outputs of bits from the first to (n- | -1) -th first adder, the inputs of the second group of the third adder are connected to the outputs of bits with ( p + 2) -th (2p + 1) -th first adder, outputs of the third adder are with the inputs of the third quadrant, the outputs of the first and second quadrants are connected to the inputs of the first and second groups of the fourth adder, respectively, the outputs of which bits are connected to the inverse inputs of the first group of the fifth adder, the inputs of the second group of which are connected to the outputs of the third quadrant, the first and second quad moves are connected to the first inputs of the EXCLUSIVE OR elements of the first group, the outputs of which are connected to the inputs of the first group of the second adder, the outputs of the bits of the fifth adder are connected to the first the input inputs of the EXCLUSIVE OR elements from the first to (2n - (- 2) -th second group, the first inputs of the Exclusive OR elements from ()) to (3n +) - th of which are connected to the bus value of "1 device, the outputs of the EXCLUSIVE OR elements the first group is connected to the first inputs of the bits from the first to the fourth of the second adder, the outputs of the EXCLUSIVE OR elements of the second group are connected to the second inputs of the bits from the (+1) to 4nth second adder, the clock input of the device is connected to the input of the addition of the control- by subtracting the first adder, the carry input the adder, the second inputs of the EXCLUSIVE OR elements of the first and second groups and with the inverse transfer input of the fifth adder. 2. A multiplier containing the first, second, and third adders. the first and second quadrants, the inputs of the first and second groups of the first adder are connected to the inputs of the first and second operands of the device, the inputs of the first quad are connected to the outputs of the bits of the first adder from the first through (n- | -1) -th, inputs of the second quad are connected to the outputs of the bits of the first adder with (n + 2) -th to (2p + 1) -th, the outputs of the bits of the second adder are connected to the outputs of the device, characterized in that, in order to simplify the circuit, it contains the third quadrant, the fourth adder and two groups of elements EXCLUSIVE OR, and in Odes of the first group of the third adder are connected to the outputs of the bits from the first to (p-4-1) -th first adder, the inputs of the second group of the third adder are connected to the outputs of the bits from (n + 2) -th to (2p + 1) - the first adder, the outputs of the third adder are connected to the inputs of the third quadr, the outputs of the second quadrant are connected to the first inputs of bits from the first to the 3rd "fourth fourth adder, the second inputs of bits from (n + 1) -th to (Zi + 2) which is connected to the outputs of the third quad, the first inputs of the elements EXCLUSIVE OR from the first to the nth first group The sensor is connected with a value of "About the device, the first inputs of the EXCLUSIVE OR elements from (n + 1) -th through the first group are connected to the outputs of the first quad, the first inputs of the EXCLUSIVE OR elements from the first to (3- | -2) -th second group connected to the outputs of the fourth adder, the first inputs of the EXCLUSIVE elements OR from the {3n- + 3) -th to the 4nth second group are connected to the value of "1 device, the outputs of the EXCLUSIVE OR elements of the first and second groups are connected to the inputs of the first and second groups of the second adders, second inputs of elements EXCLUSIVE OR first first and second groups are connected to the input of the second adder transfer, an inverse input of the fourth adder transfer control input of addition - subtraction of the first adder and the clock input of the device. FIG. J