SU1098005A1 - Device for orthogonal walsh-adamard transforming of digital signals - Google Patents

Abstract

1. A DEVICE FOR ORTHOGONAL CONVERSION OF DIGITAL SIGNALS BY WALSH ADAMAR, containing serially connected Walsh – Hadamard transformation blocks on base two and a control unit, and the information input of the first Walsh – Hadamard transformation blocks on base two is a device by a device by a device by a device. Controls are connected to the controllable 1m inputs of the corresponding Walsh-Hadamard conversion units on the base two, characterized in that, in order to extend the functionality A device consisting of a Walsh-Hadamard transform with a sample size of N 10 where m, n, 1 are non-negative integers, it contains n Welsh-Hadamard base six transform blocks and k Welsh transform blocks Hadamard has ten bases, and the output of the Walsh-Hadamard conversion unit on the base two is connected to the information input of the first Walsh-Hadamard conversion unit on the base six, the output of the conversion unit according to Walsh-Hadamard base six is connected to the information input of the first Walsh-Hadamard base conversion unit ten, the output of the k-th Walsh-Hadamard base transformation block ten is the device output, the first output of the first group of the control unit is connected to the control input of the first group each of the conversion blocks by. Walsh-Hadamard on the base six and ten, the outputs (the t + O-th group of the control block (i 1, ..., p) are connected (L to the corresponding 1m control inputs of the second group of the i-ro conversion block by Walsh Base Hadamard six, the outputs of the n--1+ group of the control unit (j 1, ..., fc.) Are connected to the corresponding control inputs of the second group of the j-ro Walsh-Hadamard conversion unit on the base with ten. 00 2. A device according to claim 1, characterized in that the Walsh-Hadamard transformation unit in the settlement two consists of two series-connected x delay elements, a switch and an arithmetic node, the input of the first delay element and control inputs of the switch are the information and control inputs of the block, respectively, the inputs and outputs of the delay elements are connected to the information inputs of the switch, the output of which is connected to the input of the arithmetic

Description

which node whose output is the output of the block.

3. The device is pop, 1 round, so that the Walsh – Hadamard transform block at the base six contains ten successively connecting elements of the delay of the first group, delay elements of the second group, four switches, three arithmetic node and adder, the input of the first delay element of the first group being the information input of the block, the input and output of the first delay element of the first group, as well as the outputs of the third, fourth, sixth, seventh, ninth and tenth delay elements of the first group are connected to the formaID1ONN inputs of the first switch, the output of which is connected to the input of the first arithmetic node, the outputs of the second, fifth and eighth elements. The delays of the first group are connected to the information inputs of the second switch, the output of which is connected to the input of the second arithmetic node, the additional outputs of the third, fourth, sixth and the seventh delay elements of the first group are connected to the information inputs of the third switch, the output of which is connected to the input of the third arithmetic node, the output of which is connected to the first informational ry input of the fourth switch and through the delay element of the second group to the second information input of the fourth switch, the outputs of the first and second arithmetic nodes and the output of the fourth switch are connected to the cy inputs of the simulator, the output of which is the output of the unit, the control input of the fourth switch is control The first input group of the block, the control inputs of the first, second, and third switches are the control inputs of the second group of the block.

4. The arrangement according to claim 1, characterized in that the Walsh-Hadamard base transform unit has eighteen successively connected delay elements of the first group, a delay element of the second group, four switches, three arithmetic nodes and an adder, and the input of the first delay element The first group is the information input of the block, the input and output of the first delay element of the first group, as well as the outputs of the second, third, fifth, sixth, seventh, eighth, tenth, eleventh, twelfth, thirteen the eleventh, sixteenth, seventeenth and eighteenth delay elements of the first group are connected to the information inputs of the first switch, the output of which is connected to the input of the first arithmetic node, the output of which is connected to the first information 1. (the ion input of the second switch and through the delay element of the second group to the second information) to the second terminal input: atator 5, the additional outputs of the fifth, the tenth, and the fifteenth delay delay elements of the first group are connected to the information inputs of the third switch; The first is connected to the input of the second arithmetic node, the additional outputs of the sixth, seventh, eighth, ninth, eleventh, twelfth, thirteenth to fourteenth delay elements of the first group are connected to the information inputs of the fourth switch; the output of which is connected to the input of the third arithmetic node, the output of the second and third arithmetic nodes, as well as the output of the second switch are connected to the input ..: adder, the output of which. is the output of the block, the control input, the second switch. control, the input of the first group of the block, the control inputs of the first, third, and fourth switches are the control inputs of the second group of the block.

5, The device according to claim. 1, tl and ch yu sch e e tem; that the control unit contains: 1kit I set the di generator hi the sequence of the connected divisors of the clock

two,

serially connected frequency dividers for six, k -1 serially connected frequency dividers for ten and h-f 1 pulse formers, and the code of the master oscillator is connected to the input of the first frequency divider by. two ,, the output of the iV-th frequency divider by two is connected to the input of the first frequency divider by six, the output of the h-th frequency divider by six is connected to the input of the first frequency depot by ten output of the m-th frequency divider by two is connected to the input

of the first pulse former, the output of the L. –th frequency divider by six is connected to the hopper i + 1 of the L-pulse generator, the output of the ith (B 1, ...,) frequency divider by ten is connected to the input of n + 1 + the pulse generator, the output of the master oscillator and the outputs of the frequency dividers by two, besides the m-th frequency divider by two, form the first group of outputs of the block, the outputs of the "-th (f 1, ..., n) are the outputs of the pulses are outputs (, + 1) th block group.

The invention relates to automation and computing and can be used to build digital filtering devices, image processing and transmission, pattern recognition, based on the fast Walsh-Hadamard transformation algorithm, when the input sample size is Nro, where pp is 2.4, 8, 12, 16, 20, ..., 100, and n and V are any natural numbers.

A device that performs an orthogonal Walsh Hadamard transform for samples with a volume containing three single transform channels that are connected in series and provide at the output of the third channel the Walsh-Hadamard transform coefficients from a sequence composed of eight values of f 1.

Closest to the present invention is a device for orthogonal conversion of digital signals to Walsh-Hadamard, comprising serially connected Walsh-Hadamard conversion blocks on the base two and a control unit 2.

However, the known devices cannot be used for solving information processing tasks in cases where the size of the input sample is different from 2.

The aim of the invention is to expand the functionality of the device, which is to transform according to Walsh-Hadamard with the volume

m

1 10

2

Where

m, n

non-negative integers.

The goal is achieved about

In that the device for orthogonal digital Walsh-Hadamard signal conversion, containing successively connected Walsh-Hadamard conversion blocks at the base two and the control unit, the information input of the first Walsh-Hadamard conversion unit on the base two is the device input the outputs of the first group of the control unit are connected to the control inputs of the corresponding BeTCTByroutfix conversion blocks according to the Walgau-Hadamard base two, contains n series-connected conversion blocks according to Walsh base amara six and K series-connected Walsh-Hadamard base blocks are ten, and the output of the m-th Walsh-Hadamard base block two is connected to the information input of the first Walsh-Admar transformation block six, output n the th Walsh-Hadamard conversion unit on base six is connected to the information input of the first Walsh-Hadamard conversion unit on the bottom ten, the output of the Walsh-Hadamard conversion unit on the basis of ten is output ode device, the first output of the first group of the control unit is connected to the control input of the first group of each of the conversion units according to Walsh Adamar on the base six and ten, the outputs of the (1 + 1) -th group of the control unit (1 1 ,. . ., p) are connected to the corresponding control inputs of the second group of the i-th Walsh-Hadamard conversion unit at the base six, the outputs (n + 1 + j) -th group of the control unit (j 1, ..., 1) are connected to corresponding to the control inputs of the second group of the j-ro transform block according to Walsh-Hadamard on the base of ten. The Walsh-Hadamard transform block at the base of two consists of two series-connected delay elements, a switch and an arithmetic node, the input of the first delay element and the control input of the switch are the information and control inputs of the block, respectively, the inputs and outputs of the delay elements are connected to the information inputs of the switch, the output of which is connected to the input of the arithmetic node whose output is the output of the block, the Walsh – Hadamard transform block at base six contains de first delay elements of the first group, delay elements of the second group, a switch network, three arithmetic nodes and an adder, the input of the first delay element of the first group being the information input of the block, the input and output of the first delay element of the first group, and the outputs of the third fourth, sixth, seventh, ninth and tenth elements of the delay of the first group are connected to the information inputs of the first switch, the output of which is connected to the input of the first arithmetic node, the outputs of the second the first, fifth and eighth elements of the first group of delays are connected to the information inputs of the second switch, the output of which is connected to the input of the second arithmetic node, the additional outputs of the third fourth, sixth and seventh delay elements of the first group are connected to the information inputs of the third switch, the output which is connected to the input of the third arithmetic node, the output of which is connected to the first information input of the fourth switch and through the delay element of the second group to the second information the ion input of the fourth Koi-fMyTaTopa, the output of the first and second arithmetic nodes and the output of the fourth switch are connected to the inputs of the adder, the output of which is the output of the block, the control input of the fourth switch is the control input of the first group of the block, control of the inputs of the first, second and second The third switches are the control inputs of the second block group. The WalshAdamaru base conversion block of ten contains eighteen serially connected delay elements of the first group, a delay element of the second group, four switches, three arithmetic nodes and an adder, the input of the first delay element of the first group being the information input of the block, the input and output of the first delay element the first group, as well as the outputs of the second, third, fifth, sixth, seventh eighth, tenth, eleventh, twelfth, thirteenth, fifteenth, sixteenth, seventeenth о and the eighteenth delay elements of the first group are connected to the information inputs of the first switch, the output of which is connected to the input of the first arithmetic node, the output of which is connected to the first information input of the second switch and through the delay element of the second group to the second information input of the second switch, additional outputs , the tenth and the fifteenth delay elements of the first group are connected to the information inputs of the third switch, the output of which is connected to the input of the second ari of the sixth, seventh, eighth, ninth, eleventh, twelfth, thirteenth and fourteenth delay elements of the first group are connected to the information inputs of the fourth switch, the output of which is connected to the input of the third arithmetic node, the outputs of the second and third arithmetic nodes, and the output of the second switch is connected to the inputs of the adder, the output of which is the output of the block, the control input of the second switch is the control input of the first group of the block, channeling inputs of the first, third and fourth switches are the gate inputs of the second block group. The control unit contains a master oscillator, m serially connected frequency dividers for two, n serially connected frequency dividers for six, serially connected frequency dividers for ten and n + lc pulse shapers, with the output of the master oscillator connected to the input of the first frequency divider by two, output The m-th frequency divider by two is connected to the input of the first frequency divider by six, the output of the And-th frequency divider by six is connected to the input of the first frequency divider by ten, the output of the t-th divider is often The two are connected to the input of the first pulse generator, the output of the i-ro splitter by six is connected to the input of the 1 + 1 th pulse generator, the output of the e-th (P 1, ..., k-1) frequency splitter by de t connected to the input of the n + t + t th pulse generator, the output of the master oscillator and the outputs of the frequency dividers by two, except for the m-th frequency divider by two, form the first group of outputs of the block outputs (q, 1, ..., b + k) pulse generator are the outputs (c}, + 1) of the control unit group. FIG. Figure 1 shows the functional on the scheme of an orthogonal digital signal transform according to Walsh-Hadamar U4 in Figures 2-4: functional diagrams of Walsh-Hadamard conversion blocks above base six, ten and two, respectively; in fig. 5 is a functional block diagram of the control unit for the case, n 2, 1c 2; in fig. 6 is a timing diagram for the input and three output signals of the pulse generator in FIG. 7 is a graph of a calculation sequence for order N 2-6. The device contains m Walsh-Hadamard base transforms of 1 serially two, n Walsh Hadamard base six transforms of 2 connected blocks 2, k base Walsh-Hadamard base of ten formations in series, k control unit 4 informational inputs 5 and outputs 6 of the Walsh-Adam conversion unit, input 7 and output 8 of the device. The Walsh-Adamaru transform block on base six contains delay elements 9 -, - 9 10, switches 11-, - 11 g, arithmetic nodes 12 3, adder 13, information input 14, control inputs 15, output 16. The Walsh-Hadamard conversion block the base ten contains the delay elements 17, -17, g, 18, com19, arithmetic mutators 20j, adder (21), information lines, matrix input 22, control input 23, output 24. The Walsh-Hadamard transform block at the base two contains delay elements 25, -25, switch 26, arithmetic unit 27, a formation input 28, control input 29 and output 3 O. The control unit contains a master oscillator 31, a frequency changer two 32, a frequency divider by six 33 and 34, a frequency divider by ten 35, pulse shapers 36-39, output groups 40-52. The master oscillator 31 and frequency dividers 32-35 set the switching frequency in the conversion blocks 1-3, affecting their control inputs. The switching frequency in subsequent conversion blocks should be reduced by a number of times equal to the base of the previous channel. So, for the case corresponding to FIG. 5, the output 40 of the control unit 4 is connected to the input 29 of the conversion unit at the base 2, the group of outputs 41-43 in order of decreasing frequency is connected to the inputs 15, 15, 15j of the first conversion unit at the base six, etc., the group outputs 50-52 in descending order, frequencies to inputs 23, 232, 23z of the second conversion unit at the base of ten. In addition, for all values of m, n, 1, the output of the master oscillator 31 is connected to control inputs and 15 of all conversion blocks on the base six and to control inputs 23x j of all the conversion blocks on the base ten. The delay of the signals on the delay elements should be proportional to the switching frequency in the respective conversion units. As delay elements, you can use the shift registers of the corresponding width. In this case, the main output of the delay element is the output of the last bit, and the output of the penultimate bit of its offset is used as an additional output. The arithmetic nodes in the conversion blocks perform the operations of adding or typing pairs of operands,

arriving at their summing or subtracting inputs.

The device is designed for a natural order of input data, and the results of calculations are also obtained in a natural order convenient for the inverse transformation.

In accordance with the use of the algorithm, the following transformation is performed on the input data sample represented by a vector of size N

F

(one)

F is the resulting transformation, A is the N-N Hadamard matrix. The construction of the FHT (fast Hadamard transform) over the input arrays of size N p is based on the recurrent method developed by the authors for constructing Hadamard matrices of order N P (, (Ro 2,4,8,12,16,20100), in particular pQ 2), Let X and Y be matrices that g transformations on the basis of m p 6 and p 10 will have the following form +1 О 0 + 1 -1 -1 0 + 1 +1 О 0 + 1-1 -1 +1 + 1 -1 -1-1 00 -1 +1 -1 0-1 o -1 -1 + 1 00 -1

(2)

 Yi.

1 -1 +1

ABOUT

Ltd

about 1 -1

0 + 10 1 -1

about o +1

-1 -1 -1 + 1-100

about +1

-1 -1-1-1 + 1 о о о о +1

+1 0 0-1 + 1 + 1 + 1 + 1

about 0 + 1 about 0 + 1 + 1-1 +1 +1

0 + 1 о о 0 + 1-1 + 1 +1 +1

about o 0 + 1 0 + 1 + 1 + 1 -1 +1

o 00 0 + 1 + 1 +1 +1 +1 -1

Y

ten

We define the notion of -y-operator, translating strings a, a,

four

ag,. . .a j of matrix A j on matrix j A 15 as follows

-but

H ®V; .

is an Hadamard matrix on the order of t. Here, O is a straight line (Kronecker product of matrices

 P is the order of the Hadamard matrix;

p is a base converting ni, equal to 6 or 10; matrix Н „, -j- Н ,. For the practical implementation of the device BPA conversion

tF3

for the constructed Hadamard matrices at the i-th stage of the transformation will be (for the base p 6)

(6)

fi X, f,. + Y.

f

1-1

gpe

f3i Xfe f ..;. (xi + x) f ..xi, f., + xf f .., (7) g daty yi J Y in the transform block on the base six (Fig. 2) the operator f is realized using a delay element 10 for two clocks and a switch 114. The numbers entered at the second input of the switch appear at its output with a changed sign. A similar role in the conversion unit for the base ten (Fig. 3) is performed by the delay element 18 and the switch 194. According to (4)

v-l f,

fc -i

The Xg matrix is represented as

+ 1 0 0 -H 00 0 + 1 0 0 + 1 0

Xg Xj, + X, 0 0 + 1 0 0 + 1 +1 00-1 00 0 + 1 0 0-1 0 0 0 + 1 0 0-1 For the base, the Hadamard transform (1) at the i-th stage will have view

X-iof i-i-

L + 1 О О О 0 + 10 00 о 0 + 10000 + 1000 00 + 1 0000 + 1 00 000 + 10000 + 10 0000 + 10000 + 1

+ 1 0000-1 0000 0 + 1 0000-1 000 00 + 1 0000-1 00

-o о о +1 о о о о -1 -1 о 0-0 о 0 + 1 о о о 0-1

Using (12), we get for

,

.f (l

l (f Uz.)

f. ((bl

(8,9,10

f (4l1 (s

About About and 0-1o About 0-1 0o about 0-1-1 0-1-1 about o -1 0-1 00. -t -1 000 Matrix X and X dl view also valid

1-1-1 о о о о о о

1-1-1 00 o o o

0-1-100000

10-100000

1-1000000

(121

00 0 + 1 + 1 + 1 + 1

about o 0 + 1 0 + 1 + 1 + 1

about o 0 + 1 + 1 0 + 1 + 1

about o 0 + 1 + 1 + 1 0 + 1

o o 0 + 1 + 1 + 1 - o

- (13, 14)

K9I 1 (101) l ((lQ) l ((lOI 1 (91

(15)

f ((4) .jl (5)

)

)

flOl + f 1 (5)

KM + 1 (41

in this case, a device for converting blocks; Odie;: black hpoobrazovann on the basis ofiiiiia two, two blocks of gfeobrazovani on the basis of; six n two blocks ires; 6 times) zann51 on the base of ten,

;;; nspcoii conversion unit

siJTopoe should delay the alarks ,, ozrlstaya in two - 2, so everyone -epe ;; t: -; -; ; ki two bits of the third block (on

o ..; B: dv:, 1ga ъ) calch element for.: tenu

J .. i 6} 2 bits of re-1; In chPPvert -Sjiotce

U OB s /: (yig, B) Kalud element:;: k ;; {OisIg1; -1y test 10 - 120 bits to Y ::; L-; KI v ;; - esT 1i

bum

Piii. : .i

oc; - o; j :: lh

delay

; ee. m. iOTyio.-j ;; d ..

 : 1 ;;. G: TS --- IT OF THE PULSE OF IMPULSE)

discrete and ore signal 71a pog: hp; d arrive on the first way obo, zozgni,

leads d, 1 y :: exact transformation

. LYaEg-and sutkki and difference pos-u

bark to the second conversion unit, where the G | base transformation is six (six-point conversion) according to formula (b), where f and output vectors of the first and second conversion blocks, respectively, and f, -jj-fg.

In the third conversion block: the base transform is base transformation ten (ten point-to-point conversion) according to the form

f - h G V f

L 2 .. 10 1-. |., - .j ,, | 1, | .

6 of the fourth and fifth blocks are converted according to the bases six and ten by the formulas:

f.U

f-,

f

2 6 fl

f, -; Y

3

(WITH

f4 te g

year

and

weekends

1S

-2-3

The second, third, fourth, and fifth transform blocks, respectively.

The advantage of the proposed device is the EFFICIENCY of the conversion;

5 with mixed oh. for N 10 nosaniye, te

Ras; 1C1The blocking of blocks with different ocHoaaHMHiiH can be combined 13 anyway.

For the following: For the Reverse BPA, the same device is used without the I-.f-.ieneHUH,

nineteen

- S

-. -; : pz1yG -.:...- rrrE-C:; aa2 ;;

28

Z5

zg

l

31

five

Tv

4 / 424J

mmPPPG

27

thirty

FIG.

Jtf

5U

J

gf f

W5t52

7i.

Claims (5)

1. A device for orthogonal conversion of digital signals by Walsh Hadamard, containing series-connected Walsh-Hadamard transform blocks at base two and a control unit, the information input of the first Walsh-Hadamard transform block at base two being the input of the control unit, the outputs of the first group connected to the control inputs of the respective Walsh-Hadamard transform blocks on the basis of two, and the fact that, in order to expand the functionality of troystva consisting in transforming the Walsh-Hadamard when the sample size N = 2 ^m 6 ⁿ · 1θ \ where m _(ri | kneotritsatelnye integers it comprises n serially connected conversion units of Walsh-Hadamard base-six and a serially connected conversion units according to Walsh-Hadamard on the basis of ten, and the output of tn-ro of the Walsh-Adam conversion unit ^ RU on the basis of two is connected to the information input of the first Walsh-Hadamard conversion unit on base six, the output of the r> th Walsh-Hadamard transformation unit base six is connected to the information input of the first Walsh-Hadamard transform block on base ten, the output of the Walsh-Hadamard transform block on base ten is the output of the device, the first output of the first group of the control unit is connected to the control input of the first group of each of the blocks conversion by. The Walsh-Hadamard base is six and ten, the outputs of the 0 + 1) -th group of the control unit (ΐ = 1, ..., p) are connected to the corresponding control inputs of the second group of the 1st block of the Walsh-Hadamard base six, the outputs (n + 1+ of the jjth group of the control unit (j = 1, ..., k) are connected to the corresponding control inputs of the second group of the j-ro of the Walsh-Hadamard base conversion base ten.> 2. The device pop. 1, characterized in that the Walsh-Hadamard transform unit on the basis of two consists of two delay elements connected in series, a switch and an arithmetic unit, the input of the first delay element and the control input of the switch being information and control inputs of the block, respectively, the inputs and outputs of the delay elements connected to the information inputs of the switch, the output of which is connected to the input of arithmetic SU „„ 1098005 of a node whose output is the output of the unit. 3. The device of the circuit 1 due to the fact that the Walsh-Hadamard transform unit on the base six contains ten series-connected delay elements of the first group, delay elements of the second group, four switches, three arithmetic unit and adder, and the input of the first delay element of the first group is the information input of the block, the input and output of the first delay element of the first group, as well as the outputs of the third, fourth, sixth, seventh, ninth and tenth delay elements of the first group are connected to the info the input inputs of the first switch, the output of which is connected to the input of the first arithmetic unit, the outputs of the second, fifth and eighth delay elements of the first group are connected to the information inputs of the second switch, the output of which is connected to the input of the second arithmetic unit, additional inputs of the third, fourth, sixth and seventh elements delays of the first group are connected to the information inputs of the third switch, the output of which is connected to the input of the third arithmetic node, the output of which is connected to the information input of the fourth switch and through the delay element of the second group to the second information input of the fourth switch, the outputs of the first and second arithmetic nodes and the output of the fourth switch are connected to the inputs of the adder, the output of which is the output of the block, the control input of the fourth switch is the control input of the first group of the block, the control inputs of the first, second and third switches are the control inputs of the second group of the block. 4. The device according to p. 1, characterized in that the Walgg-Hadamard transform unit on the basis of ten contains eighteen series-connected delay elements of the first group, a delay element of the second group, four switches, three arithmetic nodes and an adder, the input of the first delay element of the first group is the information input of the block, the input and output of the first delay element of the first group, as well as the outputs of the second, third, fifth, sixth, seventh, eighth, tenth, eleventh, twelfth, thirteenth fifteenth, sixteenth, seventeenth and eighteenth delay elements of the first group are connected to data inputs of the first switch, whose output is connected to the input of the first arithmetic unit, whose output is connected to the first data input and the second kommuStatora through delay element WTO = ·. group of the second information input of the second switch, the additional outputs of the fifth, tenth and fifteenth delay elements of the first group are connected to the information inputs of the third switch, the output of which is connected to the input of the second arithmetic unit, the additional outputs of the sixth, seventh, eighth, ninth, eleventh , twelfth, thirteenth and fourteenth delay elements of the first group are connected to the information inputs of the fourth switch, the output of which is connected to the input of the third arithmetic node, the outputs of the second and third arithmetic nodes, as well as the output of the second switch are connected to the inputs of the adder, the output of which is the output of the block, the control input of the second switch is the control input of the first group of the block, the control inputs of the first, third and fourth switches are control inputs of the second group block. 5. The device pop. 1, the difference is that the control unit contains a master oscillator, hi of series-connected frequency dividers by two, n of series-connected frequency dividers by six, 1 <-1 of series-connected frequency dividers by ten and with e to the pulse shapers, and the output of the master oscillator is connected to the input of the first frequency divider by. two, the output of the inth frequency divider by two is connected to the input of the first frequency divider by six, the output of the rth frequency divider by six is connected to the input of the first divider ° by ten, the output of the mth frequency divider by two is connected to the input of the first pulse shaper, the output of the L-th frequency divider by six is connected to the input of the i + 1-th pulse shaper, the output of the Pth (g = 1, ..., k-1) frequency divider by ten is connected to the input n + 1 + 2-nd pulse shaper, the output of the master oscillator and the outputs of the frequency dividers into two, except for the m-th frequency divider two, form the first group of inputs of the block, the outputs of the η, th (q, = = 1, ..., b + k) pulse shapers are outputs of the (<^ + 1) th group of the block.