SU1525859A1 - Frequency synthesis device - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to expand the range of synthesized frequencies and increase the uniformity of the output pulses. The device contains a control unit (CU) 1, adders 2 and 3 codes, r-r 4 reference frequency, sensor 5 reference frequencies, switches 6 and 7, unit setting 8 codes, controlled dividers 9,10 and 12 frequencies, trigger 11, regsiters 13 and 14 of memory and counters 15 and 16. This device provides the formation of a signal whose output frequency is proportional to the input frequency with a given proportionality coefficient. In this case, the error in the formation of the output frequency is determined by the capacity of the counters 15 and 16, which expands the frequency range. Running counter 15 with setting the code to the state equal to the maximum code of counter 17 avoids the loss of some of the input information. The device according to Claim 2 is characterized by the execution of the CU 1 consisting of the control counter 17, the control trigger 18, the AND 19 element, the AND 20 block of elements and the decoder 21. 1 cp f-ly, 1 ill.

Description

The invention relates to radio engineering and can be used in servo spectrum analyzers and in monitoring devices.

The purpose of the invention is the expansion of the range of synthesized frequencies and increase the uniformity of the output pulses.

The drawing shows an electrical block diagram of a frequency synthesis device.

The frequency synthesis device comprises a control unit 1, a first adder 2 codes, a second adder 3 codes, a reference frequency generator 4, a reference frequency sensor, a first switch 6, a second switch 7, a code setter 8, a first controllable frequency divider, a second controllable frequency divider 10, trigger 11, third controllable frequency divider 12, first * memory register 13, second memory register 14, first counter 15, second counter 16. In this case, control unit 1 consists of control counter 17, control trigger T8, element And 19, block elements And 20, decipher 21. Ator.

A frequency synthesis device operates as follows.

The generator 4 generates a reference frequency, which is fed to the input of the sensor 5, from the output of which a set of frequencies representing a geometric progression with the denominator q is supplied to the second multi-bit inputs of the first and second switches and 7, the output part of the output of the first and second switches 6, 7 is determined by the input code Ν _{β <} arriving at their first inputs from the output of the corresponding first and second adders 2,3. ,

If the specified multiplication factor is presented in the form K = n ^ / w ^ 2, where w, is the code at the installation input of the first controlled divider 9; | w ₂ is the code at the installation input of the second controlled divider 10, L 0 (integer), then the code R, »L is generated at the first output of code 8 setter, the code R _t = 0 is generated at the second output of code 8 setter. If the output of the first adder 2 contains the code N ^, and the output of the second adder contains the code Nj, then the frequency of the frequency grid f ₆ = f ₀ „· 2 '^ will be selected at the output of the first switch 6, and the frequency f _p = i _Ofi - at the output of the second switch 2 * ³ .

At the output of the first controlled divider 9, a pulse sequence f _? = f ₆ / m _f ⁼ = f0 „/ w ϊ 2, and at the output of the second controlled divider 10 there will be a frequency f, 0 = / ш2 2 · * ³ , codes m, ир are set respectively from the third and fourth outputs of the code setter 8,

A pulse of the input frequency enters through the first input of the control unit to the second input of the control trigger 18 and charges it, which terminates the reset conditions of the control counter 17. At the first output of the control trigger 18, the Log level appears. 0, which prohibits the passage of pulses from the second inputs of the element And 19 and the block of elements And 20 to their outputs. At the same time, the Log level is set at the fourth multi-bit output of the control unit 1. 1 and the output code Nt of the first adder becomes equal to the code R, acting on its first input, and the output frequency of the first controlled divider 9, arriving at the second (input of the control unit 1, b ^ det is defined as f у = f _e „/ та 2 * '”= Μ) -2 ^D.

With each pulse of this sequence, the code of the control counter 17 will increase by one, and a write pulse (from the second output of control unit 1) and an initial setup pulse (at the first output of the block) will appear at the second and then on the first outputs of the decoder 21 management 1). With the beginning of the recording pulse, the information states of the first and second counters 15, 16 and the state of the trigger 11 are transferred to the first and second registers 13, 14. The impulses of the initial installation reset the second counter 16 and trigger 11 to the zero state, and the first counter 15 is set to a state in which its code is equal to the maximum code of the counter * control 17,

In this case, the transfer pulse from the output of the control counter 17, arriving at the first input of the control trigger 18,. > resets the latter, resulting in. the control counter 17 will be in the reset state until a new input pulse appears. The pulses from the output of the first controlled divider 9 through the element And 19 are fed to the input of the first counter 15, increasing its code with each pulse by one. After filling the first counter 15, the next pulse acting on its input leads to overflow of the first counter 15 and all its bits go from a single to a zero state. In this case, the level difference at its second output can not be the first input of the control unit 1 control trigger 18 is again cocked and closes the passage of pulses through the element And 19 to the second input of the first counter 15. In this case, the output code of the first counter 15 together with the output of trigger 11 captures the mantissa code the repetition period of the input pulses w _y , and the state of the outputs of the second counter 16 will correspond to a code of the order of the period of the input frequency P _l , which pulse from the second output of the control unit 1 to change the state of the second counter

16, since the Log level acts on its first reset input. 1 from the second output of flip-flop 11. Since flip-flop 11 is made in the form of a D-flip-flop, the state of its input will be synchronized from the Log level. 1 to Log level. About under the action of the signal from the second output of the first counter 15 leads to a change in the state of the outputs of the trigger 11. In this case, the second 25 counter 16 receives permission to count pulses at subsequent moments in the first and second registers 13, 14. Since at L 0 the code on the first output of code setter 8 is zero, then the frequency at the output of the second controlled divider 10 will be set equal to f _{/ 0} = f _w / w ₂ · 2 ^₽ *, This frequency is fed to the input of the third controlled divider 12, the division ratio of which is determined by the code from the outputs of the first register 13. When in When the next pulses arrive at the second input of the first counter 15, the code increases from zero to the maximum, while an additional pulse sets the first counter 15 to zero, and the code of the second counter 16 increases by one, and this code goes to the second one through the block of elements And 20 the input of the first adder 2, increasing its code cN _t = LHaN £ = L + 1. In this case, the frequency at the output of the first switch 6 decreases by half and becomes equal to fy = / m _f · 2 The rate of change of the code of the first counter 15 also drops by two times. With each of this, the output frequency of the third controlled divider 12 and, therefore, the output frequency of the frequency synthesis device is determined by

Since t * = ' ₌ ^t d_ ² ™' t _l t ^ 2 ^T * T _m -f _Oh, then

those. the output frequency is proportional to the input with a proportionality coefficient K = m _f / m _t 2 ^D.

For L with 0 f ₅ f о> 2_ n “2 ^p ''

subsequent overflow of the first counter 15 increases by one the code of the second counter 16 and the pulse frequency at the input of the first counter 15 again decreases by 2 times, while the state of the trigger 11 does not change. The state of the trigger 11 is used as the unit of the highest digit of the mantissa code of the input frequency period, the remaining bits of which are represented by the output code of the first counter 15. The value of the mantissa code in this case changes in time to the maximum value periodically. At the end of the time interval and with the arrival of the next pulse on for the output frequency, a similar result is obtained.

I

The error in the formation of the output frequency is determined by the capacitance

V MAX <G (first counter 15 1 / sh 2 / sh.

If counter 15 is Q, then it is defined as 2 ^{_ <ϊ} 4 <

the frequency range depending on the second counter 16 = Fma-c / Fmhh = ² ^ ^VI · ^{So П} ₽ ^AND Q and Q _t = 3, 0,1Z ί Г ί 0,2Ζ, = 2 = 512, i.e. the range is expanding.

number of bits of the first error in

from discharge D - 10

D frequencies

Ί

Since the write control pulses in the first and second registers 13, 14 lag behind in time by several periods of the clock frequency from the moment the pulse counter was prohibited by the first counter 15, as a result, by the time the code is read in the first counter 15, the code manages to take steady values even at the highest input frequency, the input clock frequency can be selected as the maximum allowable based on the speed of the element base, which will increase the reliability.

The execution of the first counter 15 with the installation of the code in a state equal to the maximum code of the control counter 17, avoids the loss of part of the input information.

Claims (2)

Claim 1, a frequency synthesis device containing a reference frequency generator, a first switch, a code generator, first and second registers. Memory, a first counter, a first code adder and a control unit, the first input of which is a signal input of a frequency synthesis device, characterized in that, with In order to expand the range of synthesized frequencies and increase the uniformity of the output pulses, a frequency reference sensor, a first controllable frequency divider, a second counter, a trigger and a second code adder connected in series are introduced, the second switch, the second controlled frequency divider and the third controlled frequency divider, the output of which is the output of the frequency synthesis device, while the second bit inputs of the first and second switches are combined and connected to the corresponding bit outputs of the horn frequency sensor, the input of which is connected to the output of the reference frequency generator, the output of the first switch is connected to the input of the first controlled frequency divider, the output of which is connected to the second input of the control unit, the first input of the trigger is combined with the first input of the first counter and connected to the first output of the control unit, the first input of the first memory register is combined with the first input of the second memory register and connected to the second output of the control unit, the third output of which is connected to the second input of the first counter, the first and second trigger outputs respectively connected to the second input of the first memory register and to the first input of the second counter, the second input of which is combined with the second input of the trigger and connected to the transfer output of the first counter, the code output to connected to the code input of the first memory register, the code output of which is connected to the installation input of the third controlled frequency divider, the first and fourth outputs of the code generator are respectively connected to the first inputs of the second and first code adders, to the installation inputs of the second and first controlled frequency dividers, the second input the first adder codes is connected to the fourth output of the control unit, the output of the first adder codes is connected to the first input of the first switch, the second input is second; of the code adder is connected to the output of the second memory register, the second input of the latter is combined with the third input of the control unit and connected to the output of the second counter. 2. The device according to p. 1, characterized in that the control unit contains a serially connected control counter, a control trigger and an element And, as well as a block of elements And and a decoder, the first, second and third inputs of which are connected respectively to the second, third and fourth outputs a control counter, the first input of which is connected to the second control trigger, the second input of which is the first input of the control unit, the second input of the control counter. combined with the second input of the element And is the second input of the control unit, the first input of the block of elements And is connected to the first output of the control trigger, while the first and second outputs of the decoder and the output of the element And are respectively the first, second and third outputs of the control unit, and the second input and the output of the block of elements And are respectively the third input and fourth output of the control unit.