SU521663A1 - Device for determining the phase of a pseudo-random sequence - Google Patents

Description

(54) DEVICE TO DETERMINE THE SEQUENCE OF SEQUENCE OF SEQUENCE OF RANDOM. and an adder 14 modulo two, the exponent of the interconnect to the second BxcfjD block of recursive counters, Q input buffer ro-, hisgra i 2 connected to the input of the core (5 torus 2, | prn this output of the auxiliary gene axopa 10 SRP connected to the second input: block 13 read gates and through the block; 11 weights - with the second block in the switching gates, and the output; clock generator 1 is connected to the up-4 input of the buffer register 12, the device operates as follows. In the initial state, all bits are and account-geekOB are set to In addition to the zero bit of the auxiliary generator 10 SRP, which is used. Then the buffer is retanded into. The 12 is filled with the received element {SRP signals, With the t clock generated by the oscillator 1 clock (with the rest of the first P. bits 6y (j ) The ep-: register 12 is written to the generator 9 of the bandwidth as the initial phase of this generator. The 1-clock high-frequency clock generator generates 2p clock pulses with a period t for each main clock pulse that has a repetition period t. equal to the period of the elementary signals of the bandwidth, therefore, during the time of one clock cycle tj, the contents of the serial register 12 completely recycle through the feedback circuit. The signals of the first T bits of the register 12 are sequentially inputted to the input of the adder 14 modulo two through the corresponding gate of the block 13, which is kept in the open state by a single signal, derived from the zero bit output of the auxiliary generator 10 SRP. From the output of the adder 14, the signals arrive at the control of the corresponding pe-. Versatile counters that also receive counting pulses from the output of a block of 11 weighted coefficients that pass through the gates of block 6, controlled by the switch 5, In the latter, the unit moves by the clock frequency f of the down frequency and is recorded by each clock pulse tg. From block 7 reversing; counters, the signal bits of the bits are drawn through block 8. census vents to the corresponding bits of generator 9. Thus, the first received five elementary signals are recorded in generator 9 of the memory bandwidth as its initial phase VQ. Next, the generator 9 PSP produces. an exemplary hypothesis of one OS with the phase of Vo, which is compared with the last postulated individual of the correlator 2, io) of the first unit 3 and; of the blocking unit 4; If, after the time TQ of the core, the threshold is exceeded, then the signal for capturing the phase of the bandwidth is generated. If, however, the threshold is not exceeded, then the census block 8 will record the new estimate of the initial phase Po, which is obtained as a result of accumulation of receiving signals Mbtx. The accumulation of signals in the block of reverse counters is carried out simultaneously with the correlation process over the entire time Ta, which is achieved in the following manner. Starting from this initial state, the auxiliary generator 10 memory bandwidths in each clock cycle t. generates single sigts of spars on 1i0sods of those of their razrtdov, which correspond to the received element {SRP signals, modulo two of which gives the value of bits Qp, a, ... nd ", constituting the initial phase - As a result The corresponding signals from the outputs of the buffer register 12 are gated using a block of 13 read gates, so that at the output of the adder 14 modulo two in each tick ij, the digits Ig, fl, ... fl-nt are successively generated - Noah frequency record c in block 7 reversible counters for their accumulation. With the accumulation of signals, a significant role is played by a block of 11 weighting factors, the purpose of which can be explained as follows. During the operation of the auxiliary generator 10 SRP at the outputs of its bits there appear all possible combinations of P units, and therefore, the number of elementary signals involved in the summation when generating QQ values, and | , ... f, -; in each cycle t, it turns out to be different, varying from 1 to P, while the smaller the number of summable signals, the more: the result is reliable when oiH has a certain probability of distorting the summed signals; therefore, with the accumulation of signals in block 7 reversible counters tse-; to give these signals different weights according to their reliability; This is ensured by the use of 11 weighting factors, which on | the basis of the analysis of the number of units at the outputs of the auxiliary generator 10 SRP in Kaift t tact. produces a corresponding number of counting pulses, proportional to the weight given to the Ug estimate.

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From the output of the block, 11 weighting coefficients are fed to the corresponding counting inputs of the block 7 reversible meters: the block 6 of the koMSfyTauHH gates, controlled by the pulses of the switch 5, cut through.

The proposed device is essentially the same. Increases the value of getting the correct estimate of the SRP phase, which leads to a reduction in the average phase determination time several times.

Claims (1)

Invention Formula % ycTpoiJcTBo to determine the phase of a pseudo random sequence (PRS), contains -. A clock generator and serially connected correlator, threshold unit and gating unit, while a chain is connected to the other input of the correlator, consisting of serially connected switchboard, switching valve unit, unit reversing counters, a census valve block, another input of which is connected to the output of the crushing unit, and a generator of the memory bandwidth, so that, in order to reduce the phase determination time, in black auxiliary generator PSP, a block of weighting factors, as well as serially connected buffer register, block of reading gates and modulo two adder, whose output is connected to the second input of the reversible counter unit, are entered, and the input of the buffer register is connected to the input of the correlator, while the output of the auxiliary generator The memory bandwidth is connected to the second input of the readout valve unit and through the weighting factor block to the second input of the switching valve unit, and the output of the clock generator is connected to the input of the control buffer th register. Sources of information taken into account during the examination: 1. Auth. Sat № 470О82, Л1КЛ Н 04 Ь 7 / О8, 10.27.73. (prototype).