SU1350838A1 - Analyzer of state of cyclic clock receiver - Google Patents

Abstract

The invention relates to telecommunications and provides increased noise immunity for receiving digital information. The analyzer contains a charge unit 1 consisting of a trigger 16, an element AND 9 and a key 14, resistors 2-5, a threshold block (PB) 6, elements And 7, 8, 10, a capacitor 11 and keys 12, 13, 15. In the synchronization establishment mode, at the direct output of PB 6 (output of the device) there is a zero potential, which prohibits the operation of elements AND 7, 9. The high potential at the second output of PB 6 permits the operation of elements AND 8, 10. Upon entering the input of the analyzer of the first response to a code combination, which coincides in appearance with the synchronizing signal, begins the countdown of the duration of stem which coincides with the repetition period of the true clock signal, flip-flop 16 generates an error signal. When put, the voltage at the direct output of the trigger 16 through the open key 15 is charged by the capacitor P. When put, the voltage on the inverse output of the trigger 16 through the open key 13 and the resistor 2 is discharged by the capacitor 11. When the voltage on the capacitor is reached 1I of the threshold level PB 6, a high potential is formed at its output, respectively. establishment of synchronism, 1 zp f-ly, 2 ill. i (lc ate

Description

The invention relates to telecommunications and can be used in frame synchronization receivers of multichannel digital transmission systems.

The purpose of the invention is to improve the noise immunity of receiving digital information,

Fig. 1 shows a structural electrical circuit for analyzing the states of a frame alignment receiver; FIG. 2 shows timing charts which explain his work,

The state analyzer of the frame alignment receiver contains block 1 charge, first 2, second 3, third A and fourth 5 resistors 5 threshold block 6, first 7, second 8, third 3 and fourth 10 elements And, capacitor 11, first 12, second 13 , the third 14 and fourth 15 keys trigger 16.

The state analyzer of the frame alignment receiver works as follows.

A digital digital signal (in case of using a one-bit clock signal or a signal from the output of the signal decoder (not shown) of the frame synchronization receiver (in case of using a multi-bit clock signal) arrives at the analyzer information input. At the output of the signal decoder, a response time appears if -in group digital

 A code pattern appears on the channel, coinciding in appearance with the clock signal. Sequence of responses from a signal decoder

The action at the information input of the analyzer is shown in FIG. 2a, where large amplitudes of the responses correspond to true synchronization signals, and the first responses are reduced to false synchronization signals that follow non-periodically from cycle to cycle. The analyzer's clock input receives a signal (FIG. 26) generated by the group signal distributor (not shown). At the initial time, in synchronization mode, the voltage on the capacitor 11 is zero and the first output of the threshold unit 6 also has a zero

Potential prohibiting the work of the first 7 and third 9 elements I. You0

five

five

0

five

0

five

0

Such a potential at the second output of the threshold block 6 permits the operation of the second 8 and fourth 10 elements I.

After the arrival of the first response in the first cycle (FIG. 2a), the group signal distributor begins to deduce the cycle time that coincides with the tracking period of the true clock signal. At the end of the reference cycle, a positive edge of the SFG signal is generated, 26). If at this moment there is a response at the analyzer information output, then a negative front is formed after a time interval shorter than one clock interval, otherwise the formation of a negative front is delayed until this cycle of the next response, which is illustrated by the diagram in fig. 26 in the second and third cycles.

Starting from the third cycle, in which the true synchronizing signal is detected, the temporal position of the positive edges of the signal in the diagram (Fig. 26) begins to coincide with the instants of the appearance of responses caused by the true synchronizing signal. At the same time, the voltage on the second and first additional inputs of the charge unit (direct and inverse outputs of the trigger 16) varies according to the fng, 2c and 2g diagrams. In the second and third cycles, under the action of a positive voltage at the forward output of the trigger 16 The fourth element is opened AND lOj causes the fourth key 15 to open and the capacitor 11 charges through the fourth resistor 5, In the third - fourth cycles. A positive voltage from the inverse output of the trigger 16 opens the second element 8 and causes the discharge of the capacitor 11 through from the covered second switch 13 and the first resistor 2. Starting from the fourth cycle, the voltage across the capacitor I continuously increases and in the seventh cycle reaches the threshold level

2e)

causing potency measurement

At the first time point, the frame alignment is considered to be set, and the analyzer enters the state of synchronization maintenance.

in which the work of the first 7 and third 9 elements of I and for is permitted; - the work of the second 8 and fourth 10 elements of I. ceases.

In the seventh cycle, after switching the threshold unit .6, the third key 14 is opened and the voltage on the capacitor 11 through the second resistor rises to the voltage of the power source. In the seventh cycle, due to symbol failures of the synchronizing signal, the response does not appear (dotted) but at the same time the formation of a negative front in the diagram (Fig 2b) is not delayed until the next response due to the presence of a high level at the output of the analyzer. Due to the loss of one response in the synchronization maintenance mode, a partial discharge of the capacitor 11 occurs through the open first switch 12 and the third resistor 4,

Any values of accumulation coefficients for synchronization and for exit from synchronism, calculated for specific practical conditions and determined by the error rate in the communication channel, as well as the type and volume of the synchronizing signal, are easily realized by appropriately setting the resistor and capacitor values without changing the circuit configuration.

Claims (1)

Invention Formula 1, The frame synchronization receiver state analyzer containing a charging unit, the first and second inputs of which are respectively the information and synchronization inputs of the frame synchronization receiver state analyzer, the first resistor, one output of which is connected to the common bus, the second resistor, capacitor, one the output of which is connected to the common bus and the other to the input of the threshold block, the first output of which is the output of the frame synchronization receiver state analyzer, characterized in that. 0 five in order to increase the noise immunity of digital information, a third resistor is inserted, one output of which is connected to the common bus, the first AND element and the first key connected in series, the other end of the third resistor connected to the signal input, the second And second element connected in series, the signal input of which is connected to another output of the first resistor, while the outputs of the first and second keys and the output of the charging unit are connected to the input of the threshold unit, the first additional output of which is supplied Connected to the first inputs of the first and second elements And, to the second input of the first element And, to the third input of the charging unit and to the second input of the second element And the first and second outputs of the threshold unit, respectively, are connected, and the charging unit contains successively connected trigger The third And element and the third key, whose signal input is the fourth input of the charging unit and connected to the first output of the second resistor, the second output of which is the power supply of the state analyzer of the frame synchronization receiver, is output The return key is the output of the charging unit, the third input, the first and second additional outputs, which are respectively the second input of the third AND element, the inverse and the direct outputs of the charging unit trigger, 2, the analyzer according to claim 1, that is, by introducing i serially connected fourth element I, the first input of which is connected to the second output of the threshold unit, and the fourth key, to the signal input of which is connected the first output of the fourth resistor, the second the output of which is connected to the second output of the second resis0 five 0 five 50 torus, and the output of the fourth key is connected to the input of the threshold unit, while the second additional output of the charging unit is connected to the second input of the fourth element I. J / y n jiJbijiJl IL 1IIIg n. ) n il I1II h hh K ,. h and lore CPU g. 2.