SU1220122A2 - Matched filter - Google Patents

Abstract

The invention relates to telecommunications, in particular to devices for processing composite pseudo-noise signals. The aim of the invention is to increase the speed by reducing the time required for the cyclic frequency of the composite signal. The goal is achieved by adding a counter of 14 collapsed code groups, the first and second logical elements (LE) OR 15 and 18, the first and second LEs 20 and 22, S registers 16-1, to the device. ., 16-5 pseudo-random sequence formations, 5 match elements 17-1 ,,. ,, 17-S. The device makes it possible to reduce the selection time of the cyclic frequency of the composite signal by more than 7 times, which reduces the time for entering the synchronism of the communication system. Il.1, Supplementary to auth. № 913537. i (lu ts :) to

Description

one

The invention relates to telecommunications, in particular to devices for processing composite pseudo-noise signals, and is an improvement of the known device according to the author. R 913573.

The purpose of the invention is to increase the speed by reducing the time taken to extract the cyclic frequency of the composite signal.

The drawing shows the functional electrical circuit of the device.

roystva

The device contains a passive delay line 1 with taps, a block of weakening the Doppler effect, a matrix of 3 code groups, a block of 4 threshold elements, maximum signal detectors 5, registers 6-1, ..., 6-hi shift, a matrix of 7 code sequences , generator 8 clock pulses block 9 automatic frequency control, distributor 10 rolled pulses, block 11 time intervals, consisting of parallel-connected counters 12-1, ..., 12-to clock pulses, f-input element 13 coincidence, counter 14 rolled code groups, email OR OR 15.3 registers 16-1,.,., 16-S pseudo-random sequence formation. S elements 17-1, ..., 17-S coincidence, the second element OR 18, the first pulse counter 19, the AND element 20, the second pulse counter 21, the second And element 22.

The taps of the passive delay line 1 through block 2 are connected to summing matrix 3, the outputs of which are connected via block 4 threshold elements to registers 6-1,.,. , 6-f-nn dispenser 10 folded pulses. The first input of the counter 14 of collapsed code groups is connected to the output of block 4, the second input is connected to the output of generator 8, the inputs of the OR 15 element are connected to the outputs of block 4, the first inputs S of the pseudo-random sequence forming registers 16-1, .. ,, 16-S are connected with the output of the element OR 15, the second inputs are connected to the output of the generator 8. The first inputs S of the matching elements 17-1, .. ,, 17- S are connected to the outputs of the registers 16-1, ..., 16-5, the second inputs are connected to the output of the element OR 15, the third inputs are connected with the output of the counter 14. The inputs of the second element

Sh

15

20

25

thirty

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that OR 18 is connected to the outputs of the elements 17-1, ..., 17-S; The first input of the counter 19 pulses is connected to the output of the generator 8, and the second input is connected to the output of block 4. The first input of the AND 20 element is connected to the output of the counter 19, the second input to the output of the counter 14, and the third input to the output of the second element OR 18. The first the input of the counter 2I is connected to the output of the generator 8, the second input is connected to the output of the element And 20, the first input of the second element And 22 is connected to the output of the counter 21, the second to the output of the input element 13, the output is connected to the gate input of the detector 5 and to the third inputs counters 14, 19 and 21.

Line 1 delay, block 2, summing matrix 3, block 4, detector 5, registers 6-1,. . . , 6-v-r, summing matrix 7, generator 8, block 9, distributor 10, block 11, and B-input matching element are made as in the known device.

Counters 14, 19 and 21 can be performed on chips K564IE15, the elements of coincidence 17-1, ..., 17-S can be performed on chip K589IK14. Registers 16-1, ..., 16-S can be performed on one of the known schemes.

The matched filter works as follows.

A pseudo-noise signal is fed to the input of delay line 1, whose taps through block 2 arrive at summing matrix 3 configured for the codes of elementary groups of the composite signal. At the moment the entire code sequence arrives at delay line 1, summing signals from line taps occurs in delay matrix 1.

The outputs of the summing matrix 3 are connected via block 4 to the registers 6-1 ,. , distributor 10, which serve to prevent the distributor from fixing spurious pulses at the moment of incomplete processing of code groups. The distributor 10 alternately switches the folded pulses to one of the counters 12-1, ..., 12-K to set it to the zero state. The decision that the i th pulse (where 1, 2, ..., k) is a trim pulse is made only then.

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when the time interval is lt, between (| -1) th and i-th pulses coincides with j () time intervals of J-pulses preceding the utj th.

Thus, cycle synchronization of the code groups forming the composite signal is performed. The first impulse of convolution of code groups from block 4 sets counters 14 and 19 to the zero state. Simultaneously with writing to registers 6-1, .., 6-tn, pulses through the element OR 15 are written into registers forming pseudo-random sequences 16-1 ,,,, 16-S, each of which forms an M-sequence depending on the inverse register communications. The first l-symbol. The hove recorded in the pseudo-random sequence formation registers determine the initial state of the registers. The counter 14, after 2 clock cycles, at its output sets a single value and thus opens the elements 17-117-S, which compare

pulses from the output of registers 16-1 ,,. 16-S and block 4. In the event of a mismatch, the element 17-1 ,,,., 17-S is turned off and a zero value is generated at its output.

After 2h-t-P clocks, where C is the number of check characters, only one of the elements 17-1.,., 17-S corresponding to the register forming the same pseudo-random sequence as received is taken open, the output of which will be a single value.

The counter 19 through 2h In cycles will go into one state, thus, at the output of the element And 20, a single value will take effect, which will turn on the counter 21, After H- (2 and + P cycles at the output of the counter 21 will form a single value, which should coincide with the formation of a single value at the output of the f input element 13. If the cycle synchronization for the code groups is set correctly, thus two units will act at the input of the second element And 22, a gate pulse will be generated for the detector 5, If and the signal at the output of the detector 5 coincides with the gating pulse and exceeds the threshold

20122,

value, this indicates the installation of frame synchronization on a composite signal, Otherwise, if through N- (2h + f) cycles

5, the output of the second element AND will not be a single value, then the counters 14, 19 and 21 go to the zero state and the synchro nization operation is repeated,

10 Suppose that a composite signal is used in a communication system, co-. This is one of the elements of the M-sequence. Each element of the composite signal is encoded by a sequence with the number of symbols equal to 1000. Considering the possibilities of realization, the minimum length of symbols must be at least 0.5 of the ISS. Then the duration of the element of the composite signal T is 500 MKS, and the duration of the entire composite signal T ,, 63.5 ms. Minimum acquisition time determined by puff (2)

25 equals

TSIIR 2T ,, 127 ms.

In the case of using the proposed device, the time required for 30 to get into synchronism is determined by the expression

  (2h + Ot3.c. For example, when f 20

 (2.7 - "- 20) 0.5 17 ms.

sync

Thus, the proposed device makes it possible to reduce the allocation time of the cyclic frequency of the composite signal by more than 7 times, which leads to a decrease in the time taken to synchronize the communication system.

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Claims (1)

Invention Formula Matched filter according to the author, St., No. 913573, characterized in that, in order to increase speed by reducing the time In the cyclic frequency of the composite signal, the counter of the folded code groups is entered into it, the first input of which is connected to the output of the block of threshold elements, the second input - with the output of the clock pulse generator, the first OR element, whose inputs are connected to the bits of the block of threshold elements. the first and second elements are AND, the second element is OR, S are matching elements, S are registers of pseudorandom sequence formation, the first input of each of which is connected to the corresponding output of the IL element, the second input from the output of the clock generator, and the output to the first input of the corresponding S matching element , the second input of each of which is connected to the output of the first SHSh element, the third input with the output of the minimized code groups counter, and the output with the corresponding input of the second OR element, the first pulse counter, the first input of which is connected to the output of the clock pulse generator, the second input is connected to the output of the block Editor A. Shandor Order 1332/60 Compiled by A. Smirnov Tehred o.Sopko - Corrector T. Kolb Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035s, Moscow, Zh-35, Raushsk nab., 4/5 Fshshal ShSh Patent, Uzhgorod, st. Project, 4 threshold elements, - and the output is co1 „, and is with the first input of the element I, whose second input is connected to the output 5 counters of collapsed code groups, the third input is connected to the output of the second element OR, the second meter of pulses, the first input of which is connected to the output of the clock generator 10 pulses, the second input with the output of the first element I, and the output with the first input of the second element I, the second input of which is connected to the output of the E input element of the match, and 15, the output is connected to the gate input of the maximum signal detector and to the third inputs of the counter of collapsed code groups, the first and second pulse counters 20 owls